This disclosure relates in general to an electronic circuit including a level shifter.
A level shifter is used to transmit signals from a first voltage domain to a second voltage domain different from the first voltage domain. In particular, a level shifter may be used to transmit a control signals that are referenced to a first reference potential, such as ground potential, to a drive circuit of a high-side switch. Usually, the drive circuit receives a supply voltage that is referenced to a second reference potential different from the first reference potential and is configured to generate a drive signal for the high-side switch that is referenced to the second reference potential.
There is a need for an electronic circuit with a level shifter that is capable of transmitting a signal fast and in a reliable manner.
One example relates to an electronic circuit. The electronic circuit includes a level shifter with a level shifter transistor having a load path coupled between a low-side reference node and a high-side supply node of the electronic circuit. The electronic circuit further includes a semiconductor body having a base region of a first doping type, a tub of a second doping type complementary to the first doping type, and a device region of the first doping separated from the base region by the tub. The level shifter transistor is at least partially integrated in the device region. The tub is connected to the high-side supply node, and the base region is connected to the low-side reference node.
Another example relates to an integrated circuit. The integrated circuit includes a semiconductor body having a base region of a first doping type, a tub of a second doping type complementary to the first doping type, and a device region of the first doping separated from the base region by the tub. The integrated circuit further includes a transistor that is at least partially integrated in the device region, wherein the transistor includes a drift region of the second doping type, a drain region of the second doping type adjoining the drift region, a body region of the first doping type adjoining the drift region spaced apart from the drain region, a source region of the second doping type separated from the drift region by the body region, and a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric. The body region, in a horizontal plane of the semiconductor body, forms a closed loop around the drain region, and the drift region is spaced apart from the body region in at least one of a first and second edge region of the transistor.
Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features.
In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
The level shifter transistor TL1 is at least partially integrated in a semiconductor body 100. More specifically, the level shifter transistor TL1 is at least partially integrated in a device region 130 of the semiconductor body 100. The semiconductor body 100 is not illustrated in the circuit diagram shown in
A vertical cross-sectional view and a top view of the semiconductor body 100 including the device region 130 in which the level shifter transistor TL1 is at least partially integrated are schematically illustrated in
The level shifter transistor TL1 is only represented by its circuit symbol in
Referring to
According to one example, a polarity of a voltage between the high-side supply node and N13 and the low-side reference node N11 and the first and second doping types are adapted to one another such that the voltage between the high-side supply node N13 and the low-side reference node N11 reverse biases a PN junction formed between the tub 120 of the second doping type and the base region 110 of the first doping type. According to one example, the voltage between the high-side supply node N13 and the low-side reference node N11 is positive, the first doping type is a P-type, and the second doping type is an N-type. In this example, the PN junction between the tub 120 and the base region 110 is reverse biased by the positive voltage between the high-side supply node N13 and the low-side reference node N11.
According to one example, the electrical potential at the low-side reference node N11 is ground GND. Thus, the low-side reference node N11 may also referred to as ground node in the following.
Referring to the above, the device region 130 is separated from the base region 110 of the semiconductor body 100 by the tub 120. Referring to
According to one example illustrated in
The information included in the input signal Sin and, therefore, the high-side control signal Shs is a switching information for an electronic switch, for example. According to one example, the high-side drive circuit 4 is configured to provide a drive signal Sdrvh based on the high-side control signal Shs at an output N14. The drive signal Sdrvh is also referred to as high-side drive signal Sdrvh in the following. According to one example, the drive signal Sdrvh is a voltage referenced to a high-side reference node N12.
According to one example, the high-side switch 7 is configured to switch on or off dependent on the high-side drive signal Sdrvh received from the high-side drive circuit 4. In the on-state (switched-on-state) of the high-side switch 7 the load supply voltage Vhv essentially drops across the low-side circuit 8. In the off-state of the high-side switch 7, the load supply voltage Vhv essentially drops across the high-side switch 7.
The high-side switch 7 may be implemented as a conventional electronic switch. For illustration purposes only, the high-side switch 7 shown in
According to one example illustrated in
When the high-side switch 7 is in the on-state, the electrical potential at the high-side reference node N12 essentially equals the load supply voltage Vhv, so that the high-side supply potential Vhs is essentially given by the load supply voltage Vhv plus the supply voltage V51 received between the high-side supply node N13 and the high-side reference node N12. When the high-side switch 7 is in the off-state, the potential at the high-side reference node N12 essentially equals ground potential GND, so that the high-side supply voltage essentially equals the voltage V51 provided by the voltage source 51 connected between the high-side supply node N13 and the high-side reference node N12.
The voltage source 51 that provides the supply voltage V51 includes a bootstrap circuit (not illustrated), for example. One example of a voltage source 51 including a bootstrap circuit is explained herein further below.
The drift region 31, the source region 32, the body region 33, and the drain region 34 are also referred to as active device regions of the level shifter transistor TL1 in the following. Forming the active device regions of the level shifter transistor TL1 may include implanting dopant atoms into the device region 130 and may include a thermal process to activate the implanted dopant atoms. The device region 130 has a basic doping of the second doping type. Referring to
According to one example, doping concentrations of the base region 110 and the device region 130 are selected from a range of between 1 E14 cm−3 and 1 E16 cm−3, for example. According to one example, the base region 110 and the device region 130 essentially have the same doping concentration. The doping concentration of the tub 120 is selected from between 1 E18 cm−3 and 1 E20 cm−3, for example. Doping concentrations of the source and drain regions 32, 34 are higher than 1 E19 cm−3 and lower than 1 E21 cm−3, for example. The doping concentration of the drift region 31 is selected from between 1 E16 cm−3 and 1 E18 cm−3, for example, and the doping concentration of the body region 33 is selected from between 1 E17 cm−3 and 1 E19 cm−3, for example.
Referring to
The level shifter transistor TL1 is in an on-state (conducting state) in which there is a conducting channel in the body region 33 between the source region 32 and the drift region 31 when a voltage is applied between the gate electrode 35 and the source region 32 that is higher than a threshold voltage of the level shifter transistor TL1. In an N-type MOSFET, for example, the threshold voltage is a positive voltage, so that the level shifter transistor TL1 is in the on-state whenever a drive voltage higher than the threshold voltage is applied between the gate electrode 35 and the source region 32. The level shifter transistor TL1 is in an off-state (blocking state) when the voltage between the gate electrode 35 and the source region 32 is below the threshold voltage. In this operating state, the conducting channel in the body region 33 is interrupted.
According to one example, the level shifter transistor TL1 further includes a source electrode 221 connected to the source and body regions 32, 33, and a drain electrode 222 connected to the drain region 34. The source and drain electrodes 221, 222 may be spaced apart from the semiconductor body 100 and separated from the semiconductor body 100 by an insulating layer 210. Just for the purpose of illustration, the source and drain electrodes 221, 222 are drawn to be formed on top of the insulating layer 210 in the example illustrated in
Connections between the source electrode 221 and the source and body regions 32, 33 and a connection between the drain electrode 222 and the drain region 34 are only schematically illustrated in
In the example illustrated in
The arrangement illustrated in
Referring to
A second capacitance C2 includes the body region 33 connected to the source node S1, the device region 130, the tub 120, And the PN junction formed between the device region 130 and the tub 120. According to one example, the source node S1 is connected to the low-side reference node N11. In this example, the second capacitance C2, like the first capacitance C1, is connected between the high-side supply node N13 and the low-side reference node N11, so that the charging state of this capacitance varies dependent on the switching state of the high-side switch 7.
A third capacitance C3, which may also be referred to as drain-source capacitance of the level shifter transistor TL1, includes the drain region 34, the drift region 31, the body region 33 connected to the source node S1, sections of the device region 130 adjoining the drift region 31 and the body region 33, a PN junction formed between the body region 33 and the drift region 31, and a PN junction formed between the drift region 31 and the device region 130.
Referring to the above, the high-side control signal Shs is dependent on the switching state of the level shifter transistor TL1, wherein the switching state of the level shifter transistor is dependent on the input signal Sin. The switching speed of the level shifter 2 indicates how fast a signal level of the high-side control signal Shs changes after the signal level of the input signal Sin changes. The shorter a delay time between a change of the signal level of the input signal Sin and a corresponding change of the signal level of the high-side control signal Shs, the higher a switching speed of the level shifter 2. The input signal Sin controls the operating state of the level shifter transistor TL1, so that the switching speed of the level shifter transistor TL1 significantly governs the switching speed of the level shifter 2. The switching speed of the level shifter transistor TL1 indicates how fast the level shifter transistor TL1 changes its operating state (switching state) dependent on the input signal Sin.
The level shifter transistor TL1 can be operated in an on-state (conducting state) or an off-state (blocking state). When the level shifter transistor TL1 changes from the on-state to the off-state the conducting channel in the body region 33 is interrupted and the PN junction between the body region 33 and the drift region 31 and also the PN junction between the drift region 31 and the device region 130 is reverse biased, so that the source-drain capacitance C3 is charged. Equivalently, when the level shifter transistor TL1 changes from the off-state to the on-state, a conducting channel is generated in the body region 33 and the voltage between the body region 33 and the drift region 31 decreases so that the source-drain capacitance C3 is discharged. The switching speed of the level shifter transistor TL1 is significantly governed by how fast the source-drain capacitance C3 is charged when the level shifter transistor TL1 changes from the on-state to the off-state or is discharged when the level shifter transistor TL1 changes from the off-state to the on-state.
Referring to the above, the source-drain capacitance C3 includes the drift region 31 and portions of the device region 130 adjoining the drift region 31. Furthermore, the device region 130 is also part of the second capacitance C2 formed between the body region 33 connected to the source node S1 and the tub region 120 connected to the high-side supply node N13. The PN junction formed between the device region 130 and the tub 120 is always reverse biased, wherein the voltage reverse biasing the PN junction either essentially equals the supply voltage V51 provided by the supply voltage source 51 or equals the supply voltage V51 plus the load supply voltage Vhv. The first operating state is referred to as low-voltage state and the second operating state is referred to as high-voltage state in the following.
In each of these operating states the device region 130 is at least partially depleted of charge carriers, wherein such depletion of charge carriers of the device region 130 reduces a capacitance value of the source-drain capacitance C3. Basically, the larger the portions of the device region 130 that are depleted of charge carriers the lower the capacitance value of the source-drain capacitance C3, so that in the high voltage state the source-drain capacitance C3 is lower than in the low voltage state. Nevertheless, in both operating states, high-voltage state and low-voltage state, the partial depletion of the device region 130 that is due to connecting the tub 120 to the high-side supply node N13 and coupling the source node S1 of the level shifter transistor TL1 to the low-side reference node N11 results in a reduced capacitance value of the source-drain capacitance C3, which results in a high switching speed of the level shifter transistor TL1.
The charging state of each of the first and second capacitances C1, C2 is different in the high voltage state and the low voltage state, so that the charging state of these capacitances C1, C2 changes when the high-side supply voltage Vhs changes. The first and second capacitances C1, C2 are charged or discharged by current provided or received by the load circuit 6. The load circuit 6 is usually capable of providing a high current for changing the charging states of the first and second capacitances C1, C2 so that charging or discharging the first and second capacitances C1, C2 has no significant impact on the switching speed of the level shifter 2.
According to one example, a dimension of the field electrode 37 in the direction in which the body region 33 and the drain region 34 are spaced apart from each other is about 30%, 50%, or 70% of the distance between the body region 33 and the drain region 34.
In the example illustrated in
Referring to
Furthermore, in the transistor device according to
Optionally, the transistor device according to
Referring to
Furthermore, referring to
According to one example illustrated in
According to another example illustrated in
The thickness of the field dielectric 39 is at least 5 times the thickness of the gate dielectric 36, for example. According to one example, the thickness of the field dielectric 39 is less than 100 times the thickness of the gate dielectric 36. According to one example, the thickness of the field dielectric 39 is between 5 times and 30 times the thickness of the gate dielectric 36.
In the level shifter transistor TL1 according to
According to one example, the doped region of the first doping type arranged between the body region 33 and the drift region 31 has a doping concentration different from the doping concentration of the body region 33. According to one example, the doping concentration is lower than the doping concentration of the body region 33, such as less than 50% or less than 10% of the doping concentration of the body region 33.
According to one example, the doped region of the first doping type arranged between the body region 33 and the drift region 31 has a doping concentration that is equal to or lower than the doping concentration of the drift region 31. According to one example, the doping concentration is lower than the doping concentration of the drift region 31, such as less than 50% or less than 10% of the doping concentration of the drift region 31.
According to another example (illustrated in
In the transistor device according to
Referring to the above, the level shifter 2 includes the level shifter transistor TL1 having its load path coupled between the high-side supply node N13 and the low-side reference node N11. An example for coupling the load path of the level shifter transistor TL1 between the high-side supply node N13 and the low-side reference node N11 is illustrated in
According to one example, a voltage limiting element 22 is connected in parallel with the evaluation circuit 21. The voltage limiting circuit 22 is configured to limit (clamp) a voltage across the evaluation circuit 21, so that the voltage across the evaluation circuit does not exceed a predefined voltage threshold. The voltage limiting circuit 22 includes a Zener diode or a series circuit including several Zener diodes connected in series, for example. The voltage threshold (clamping voltage) is selected from between several volts, such as 3V, and 20V, for example.
The evaluation second 21 is configured to detect the operating state (switching state) of the level shifter transistor TL1 and generate the high-side control signal Shs dependent on the detected switching state of the level shifter transistor TL1. According to one example, the evaluation circuit 21 is configured to monitor a transistor current IL1 through the level shifter transistor TL1 and generate the high-side control signal Shs dependent on a detected current level of the transistor current IL1. According to one example, the evaluation circuit 21 is configured to generate the high-side control signal Shs such that the high-side control signal Shs has a first signal level when the monitored current IL1 indicates that the level shifter transistor TL1 is in the on-state and a second signal level when the monitored current IL1 indicates that the level shifter transistor TL1 is in the off-state.
One example of an evaluation circuit 21 that is configured to monitor the transistor current IL1 and generate the high-side control signal Shs dependent on monitored transistor current IL1 is illustrated in
The voltage across the resistor 211 is given by a resistance R211 of the resistor 211 multiplied with a current level of the transistor current IL1,
where R211 denotes the resistance of the resistor 211 and IL1 denotes the current level of the transistor current. Thus, the comparator 212 switches the high-side control signal Shs from the first signal level to the second signal level when the monitored current IL1 falls below a current threshold IL1th that is dependent on the resistance R211 and the reference voltage Vref as follows:
Equivalently, the comparator switches the high-side control signal Shs from the second signal level to the first signal level when the monitored current IL1 rises above the current threshold IL1th according to equation (2).
Referring to
The evaluation circuit 21 is configured to detect the operating state of each of the first and second level shifter transistors TL1, TL2 and generate the high-side control signal Shs dependent on the operating states of the first and second level shifter transistors TL1, TL2. According to one example, the first and second level shifter transistors TL1, TL2 are operated in a complementary (differential) fashion such that, at each time, one of the first and second level shifter transistors TL1, TL2 is in the on-state and the other one of the first and second level shifter transistors TL1, TL2 is in the off-state. In this example, the evaluation circuit 21 is configured to generate the signal level of the high-side control signal Shs dependent on which of the first and second level shifter transistors TL1, TL2 is in the on-state and which of the first and second level shifter transistors TL1, TL2 is in the off-state.
According to one example, active device regions of the first and second level shifter transistors TL1, TL2 are integrated in the same device region 130. This is illustrated in
In the example illustrated in
In the example illustrated in
Referring to
It should be noted that the level shifter 2 is not restricted to be implemented with one or two level shifter transistors. According to another example (not illustrated), the level shifter 2 includes at least one further level shifter transistors each having its load path coupled between the high-side reference node N13 and the low-side reference node N11. The operating state of the further level shifter transistor is controlled by a further input signal. The at least one further level shifter transistor may be used to transmit further information from a control circuit generating the further input signal to the evaluation circuit, wherein this further information may be transmitted from the evaluation circuit 21 to the high-side drive circuit 4.
The control circuit 41 is configured to control operation of the first and second switches 42, 43 in a complementary fashion, so that at each time only one of the first and second switches 42, 43 is switched on. To switch on the high-side switch 7, the control circuit 41, dependent on the high-side control signal Shs, switches on the first switch 42, so that the drive voltage (gate-source voltage) of the high-side switch 7 essentially equals the supply voltage V51 which is suitable to switch on the high-side switch 7. To switch off the high-side switch 7, the control circuit 41 switches on the second switch 43, so that the drive voltage of the high-side switch 7 essentially equals zero, which switches off the high-side switch 7.
The operating state of the low-side switch 81 is controlled by a low-side drive circuit 9 which is part of the electronic circuit 1. Just for the purpose of illustration, the low-side switch 81 according to
The low-side drive circuit 9 may be implemented similar to the high-side drive circuit illustrated in
According to one example illustrated in
Forming a tub 120 of the type illustrated in
Forming the tub 120 may further include forming a second layer 150 on top of the first layer 140 of the semiconductor body 100 and forming the sidewall portions 122 in the second layer 150. Forming the sidewall portions 120 may include implanting dopant atoms via the first surface 101 of the semiconductor body 100 into those regions in which the sidewall portions 122 are to be formed.
According to another example, the second layer 150 includes several sub-layers, wherein after forming each of these sub-layers dopant atoms are implanted into the respective sub-layer to form doped regions. The doped regions in the sub-layers together form the sidewall portions 122 of the top 120.
According to another example, illustrated in dashed lines in
It should be noted that in addition to the level shifter 2 with the one or more level shifter transistors TL1, TL2 further portions of the electronic circuit 1 may be Integrated in the semiconductor body 100. According to one example, the high-side drive circuit 4 is also integrated in the semiconductor body 100. According to another example, the high-side drive circuit 4 and the low-side drive circuit 9 are integrated in the semiconductor body 100.
Some of the examples explained above are briefly summarized in the following with reference to numbered examples.
An electronic circuit, comprising: a level shifter comprising a level shifter transistor having a load path coupled between a low-side reference node and a high-side supply node of the electronic circuit, wherein the electronic circuit further comprises a semiconductor body having a base region of a first doping type, a tub of a second doping type complementary to the first doping type, and a device region of the first doping separated from the base region by the tub, wherein the level shifter transistor is at least partially integrated in the device region, and wherein the tub is connected to the high-side supply node and the base region is connected to the low-side reference node.
The electronic circuit of example 1, wherein the level shifter transistor comprises: a drift region of the second doping type; a drain region of the second doping type adjoining the drift region; a body region of the first doping type adjoining the drift region spaced apart from the drain region; a source region of the second doping type separated from the drift region by the body region; and a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric.
The electronic circuit of example 2, wherein the drain region is embedded in the drift region, wherein the body region comprises a first body region section that is spaced apart from the drain region in a first lateral direction of the semiconductor body, and a second body region section that is spaced apart from the drain region in a second lateral direction opposite the first lateral direction, and wherein the source region comprises a first source region section arranged in the first body region section, and a second source region section arranged in the second body region section.
The electronic circuit of example 3, wherein the first and second source region sections are spaced apart from each other, and wherein the body region, in a horizontal plane of the semiconductor body, forms a closed loop around the drain region.
The electronic circuit of example 4, wherein the body region comprises a third body region section arranged between the first and second body region sections in a first edge region of the level shifter transistor, wherein the body region comprises a fourth body region section arranged between the first and second body region sections in a second edge region of the level shifter transistor, and wherein the drift region adjoins both the third and fourth body region sections.
The electronic circuit of example 4, wherein the body region comprises a third body region section arranged between the first and second body region sections in a first edge region of the level shifter transistor, wherein the body region comprises a fourth body region section arranged between the first and second body region sections in a second edge region of the level shifter transistor, and wherein the drift region is spaced apart from at least one of the third and fourth body region sections.
The electronic circuit of examples 5 and 6, wherein the gate electrode is arranged on top of the third and fourth body region sections and is dielectrically insulated from the third and fourth body region sections by a field dielectric.
The electronic circuit of any one of examples 2 to 7, wherein the drift region is separated from the tub by the device region.
The electronic circuit of any one of examples 1 to 8, wherein the level shifter transistor is a first level shifter transistor, and wherein the level shifter comprises at least one further level shifter transistor having a load path coupled between the low-side reference node and the high-side supply node of the electronic circuit, and wherein the at least one further level shifter transistor is at least partially integrated in the device region.
The electronic circuit of any one of examples 1 to 9, wherein the level shifter further comprises: an evaluation circuit connected in series with the level shifter transistor and connected between the level shifter transistor and the high-side supply node.
The electronic circuit of example 10, wherein the level shifter further comprises: a voltage clamping element connected in parallel with the evaluation circuit.
The electronic circuit of example 10 or 11, wherein the evaluation circuit is at least partially integrated in the semiconductor body.
The electronic circuit of any one of examples 10 to 12, further comprising: a high-side drive circuit connected to the evaluation circuit and configured to receive a high-side control signal from the evaluation circuit and drive a high-side transistor device dependent on the high-side control signal.
The electronic circuit of example 13, wherein the high-side drive circuit is at least partially integrated in the semiconductor body.
An integrated circuit, comprising: a semiconductor body having a base region of a first doping type, a tub of a second doping type complementary to the first doping type, and a device region of the first doping separated from the base region by the tub; and a transistor at least partially integrated in the device region, wherein the transistor comprises: a drift region of the second doping type; a drain region of the second doping type adjoining the drift region; a body region of the first doping type adjoining the drift region spaced apart from the drain region; a source region of the second doping type separated from the drift region by the body region; and a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric, and wherein the body region, in a horizontal plane of the semiconductor body, forms a closed loop around the drain region, and wherein the drift region is spaced apart from the body region in at least one of a first and second edge region of the transistor.
The integrated circuit of example 15, wherein a doped region of the first doping type is arranged between the drift region and the body region in the at least one of the first and second edge regions of the transistor.
The integrated circuit of example 16, wherein a doping concentration of the doped region of the first doping type is different from the doping concentration of the body region.
The integrated circuit of example 17, wherein a doping concentration of the doped region of the first doping type is lower than the doping concentration of the body region.
The integrated circuit of example 15, wherein a section of the device region is arranged between the drift region and the body region in the at least one of the first and second edge regions of the transistor.
The integrated circuit of example 15, wherein a doped region of the second doping type and having a doping concentration equal to or lower than the doping concentration of the drift region is arranged between the drift region and the body region in the at least one of the first and second edge regions of the transistor.
The integrated circuit of any one of examples 15 to 20, wherein the body region comprises a first body region section that is spaced apart from the drain region in a first lateral direction of the semiconductor body, and a second body region section that is spaced apart from the drain region in a second lateral direction opposite the first lateral direction, and wherein the source region comprises a first source region section arranged in the first body region section, and a second source region section arranged in the second body region section, wherein the body region further comprises a third body region section arranged between the first and second body region sections in the first edge region of the transistor, and wherein the body region comprises a fourth body region section arranged between the first and second body region sections in a second edge region of the transistor.
The electronic circuit of any one of examples 15 to 21, wherein the drift region is separated from the tub by the device region.
An electronic circuit including the integrated circuit of any one of examples 15 to 22; and a level shifter including a level shifter transistor formed by the transistor of the integrated circuit and having a load path coupled between a low-side reference node and a high-side supply node of the electronic circuit, wherein the tub of the integrated circuit is connected to the high-side supply node and the base region of the integrated circuit is connected to the low-side reference node.
Number | Date | Country | Kind |
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23215319 | Dec 2023 | EP | regional |