The present disclosure relates to electronic circuits.
A differential transmission technique for performing communication between devices is used in in-vehicle devices mounted on vehicles or the like. In Japanese Unexamined Patent Application Publication No. 2005-318539, a differential transmission circuit that includes a shield line including a pair of signal lines and a shield coating the pair of signal lines is described. In the differential transmission circuit in Japanese Unexamined Patent Application Publication No. 2005-318539, a common mode choke coil is provided between a substrate ground and the shield line.
In an in-vehicle device, a signal ground provided near a signal source and a frame ground connected to a shield may be arranged isolated from each other. Thus, damage can be prevented from occurring to an electronic circuit when external noise such as ESD is applied.
However, in the case where the signal ground and the frame ground are isolated from each other, a loop formed by a path for signal transmission and the grounds is large, and common mode noise is thus likely to be generated. Furthermore, in the case where the common mode choke coil including three lines described in Japanese Unexamined Patent Application Publication No. 2005-318539 is used, in order to obtain a necessary inductance, the size of components needs to be increased, and size reduction may be difficult.
Accordingly, the present disclosure provides an electronic circuit capable of achieving size reduction and effectively reducing noise.
An electronic circuit according to an aspect of the present disclosure includes a shield line that includes a first signal line, a second signal line, and a shield. The first signal line and the second signal line are connected to a signal source, and the shield coating is around the first signal line and the second signal line. The electronic circuit further includes a signal ground that is provided near the signal source; a frame ground that is isolated from the signal ground and is connected to the shield; a common mode choke coil that includes a first coil, a second coil, and a third coil magnetically coupled to one another; and a capacitor that is connected in parallel with the third coil. The first coil is connected in series between the signal source and the first signal line. The second coil is connected in series between the signal source and the second signal line. The third coil and the capacitor that are connected in parallel are connected between the signal ground and the frame ground.
With an electronic circuit according to the present disclosure, size reduction can be achieved, and noise can be effectively reduced.
Hereinafter, electronic circuits according to embodiments of the present disclosure will be described in detail with reference to drawings. The present disclosure is not intended to be limited to the embodiments described below. It is obvious that the embodiments described below are merely examples and configurations illustrated in different embodiments may be partially replaced or combined. In a second embodiment and later embodiments, details common to the first embodiment will not be described and only differences will be described. In particular, similar operational effects achieved by similar configurations will not be repeatedly mentioned in each of the embodiments.
The shield line 10 includes a pair of first signal line 11a and second signal line 11b and a shield 15 coating around the pair of first signal line 11a and second signal line 11b. The shield line 10 transfers signals to and from an external electronic device. The electronic circuit 1 uses a differential transmission method. Signals of different phases are transmitted through the pair of first signal line 11a and second signal line 11b. Furthermore, the pair of first signal line 11a and second signal line 11b are formed as, for example, a twisted pair line. Thus, the shield line 10 can reduce emission of noise. In the explanation provided below, when there is no need to distinguish between the first signal line 11a and the second signal line 11b, the first signal line 11a and the second signal line 11b may be simply referred to as signal lines 11.
The common mode choke coil 20 includes a first coil 21, a second coil 22, and a third coil 23 that are magnetically coupled to one another. That is, the first coil 21 and the second coil 22 are magnetically coupled, the second coil 22 and the third coil 23 are magnetically coupled, and the first coil 21 and the third coil 23 are magnetically coupled. It is desirable that coupling coefficients between the coils be the same. However, coupling coefficients between the coils may be different. The single common mode choke coil 20 is provided for the single shield line 10.
The capacitor 25 is connected in parallel with the third coil 23. Specifically, one end of the capacitor 25 and one end of the third coil 23 are connected, and the other end of the capacitor 25 and the other end of the third coil 23 are connected. For example, a capacitor element such as a chip capacitor may be used as the capacitor 25. The capacitor 25 is a component integrated with the first coil 21, the second coil 22, and the third coil 23. In this embodiment, “integration” represents a case where a component element of the common mode choke coil 20 and a component element of the capacitor 25 are directly in contact with each other or a case where part of a component element of the common mode choke coil 20 and part of a component element of the capacitor 25 are in common.
The signal ground 31 is provided near a signal source 41, that is, provided at a position closer to the signal source 41 than the frame ground 32 is. The signal ground 31 is connected to a reference potential for a signal transmitted through the signal lines 11. The frame ground 32 is provided isolated from the signal ground 31 and is connected to the shield 15 of the shield line 10. The frame ground 32 is connected near a connector to which the shield line 10 is connected and is also referred to as a connector ground. Furthermore, the frame ground 32 is connected to a frame potential for an electronic device on which the electronic circuit 1 is mounted.
The IC 40 includes the signal source 41 that is provided for each shield line 10. The signal source 41 is electrically connected to the pair of signal lines 11 with the common mode choke coil 20 interposed therebetween and supplies a differential signal to the pair of signal lines 11. Furthermore, the IC 40 is connected to the signal ground 31. In
In the common mode choke coil 20, the first coil 21 is connected in series between the signal source 41 and the first signal line 11a. The second coil 22 is connected in series between the signal source 41 and the second signal line 11b. The third coil 23 and the capacitor 25, which are connected in parallel, are connected between the signal ground 31 and the frame ground 32.
In other words, one end of the first coil 21 is connected to the signal source 41, and the other end of the first coil 21 is connected to the first signal line 11a. One end of the second coil 22 is connected to the signal source 41, and the other end of the second coil 22 is connected to the second signal line 11b. One end of the third coil 23 and one end of the capacitor 25 are connected to the signal ground 31, and the other end of the third coil 23 and the other end of the capacitor 25 are connected to the frame ground 32.
In the case where differential signals are supplied from the signal source 41 to the first coil 21 and the second coil 22, a magnetic field generated at the first coil 21 and a magnetic field generated at the second coil 22 cancel each other out. Thus, the common mode choke coil 20 has a low impedance and does not function as a filter. Therefore, the differential signals are transmitted from the signal source 41 through the first coil 21 and the second coil 22 to the first signal line 11a and the second signal line 11b.
The signal ground 31 and the frame ground 32 are connected with an LC filter including the third coil 23 and the capacitor 25 interposed therebetween. Thus, a return path for a signal is formed by the frame ground 32, the LC filter, and the signal ground 31. That is, a return current flows through in the order of the frame ground 32, the LC filter, and the signal ground 31 in a direction indicated by an arrow 54.
As described above, the electronic circuit 1 can secure a return path for a signal. That is, even with the configuration in which the signal ground 31 and the frame ground 32 are isolated from each other, a path starting from the signal source 41, through the pair of signal lines 11, the frame ground 32, and the LC filter, and returning to the signal ground 31 can be shortened. Furthermore, as described later, the LC filter has excellent transmission characteristics in a GHz band. Thus, compared to the configuration in which the capacitor 25 is not provided, a return path for a signal in a GHz band can be secured. As a result, generation of common mode noise can be reduced.
Furthermore, when common mode currents of the same direction flow through the first coil 21, the second coil 22, and the third coil 23, as indicated by arrows 51, 52, and 53, magnetic fields are generated at the first coil 21, the second coil 22, and the third coil 23. The magnetic fields generated at the first coil 21, the second coil 22, and the third coil 23 enhance one another. The common mode choke coil 20 exhibits a high impedance and functions as a filter. Thus, transmission of common mode noise from the signal ground 31 to the shield line 10 can be reduced. As a result, the electronic circuit 1 can reduce emission of noise caused by common mode noise.
Next, simulation results of transmission characteristics obtained when an inductance value L and a capacitance value C in the electronic circuit 1 are varied will be described.
In samples S1, S2, and S3 illustrated in
As illustrated in
In a so-called immunity test for applying external noise to the shield line 10 to investigate malfunction of a device, a noise reduction effect such as 1 MHz or more and 400 MHz or less is required in a relatively low frequency region. As illustrated in
As described above, by varying the capacitance value of the capacitor 25 that is provided in parallel with the third coil 23, the electronic circuit 1 can effectively achieve a noise reduction effect in accordance with the frequency of common mode noise.
Although the case where the capacitance value C is varied while the inductance value L is fixed is illustrated in Graph 1 of
Furthermore, the inductance value L of each coil in the sample S4 is 0.01 μH. The inductance value L of each coil in the sample S5 is 0.02 μH. The inductance value L of each coil in the sample S6 is 0.03 μH. The inductance value L of each coil in the sample S7 is 0.05 μH. The inductance value L of each coil in the sample S8 is 0.3 μH. The inductance value L of each coil in the sample S9 is 30 μH. The inductance value L of each coil in the sample S10 is 300 μH.
As illustrated in
1.6×10−19≤L×C≤2.5×10−14 (1)
However, in order to vary the inductance value L, the number of windings needs to be varied or the size of a core needs to be varied. Thus, due to restrictions regarding the size of the device, the arrangement of the common mode choke coil 20, and the like, it may be difficult to easily vary the inductance value L. Furthermore, in order to increase the inductance value L, the number of windings needs to be increased or the size of the core needs to be increased. Thus, it may be difficult to reduce the size of the device.
In this embodiment, as described above, the LC resonant frequency exhibiting attenuation characteristics can be varied by varying the L×C value. Thus, even in the case where the inductance value L is fixed or the inductance value L can be varied within a small range, an appropriate LC resonant frequency can be set by varying the capacitance value C. Therefore, the size of the electronic circuit 1 can be reduced, and common mode noise at a desired frequency can be reduced effectively.
However, while the first coil 21, the second coil 22, and the third coil 23 are magnetically coupled in the sample S4, the comparative example C2 is configured differently such that the third coil 23 is not magnetically coupled to the first coil 21 and the second coil 22. Specifically, for example, in the sample S4, the first coil 21, the second coil 22, and the third coil 23 are magnetically coupled in such a manner that winding is applied to a common core or a core formed in an integrated manner. In the comparative example C2, the third coil 23 and the capacitor 25 are provided separated from the common mode choke coil 20.
As illustrated in
Next, simulation results regarding transmission characteristics of a return path for a signal including the frame ground 32, the LC filter, and the signal ground 31 will be described.
The inductance values L and the capacitance values C of the samples S1, S2, S3, and S6 and the comparative example C1 illustrated in Graph 5 of
As illustrated in
For example, transmission characteristics of −3 dB or more are required for a GHz band. That is, it is desirable that the capacitance value C be 3 pF or more. As is clear from the above, with the capacitance value C of 3 pF or more, the electronic circuit 1 can secure a return path for a signal. Although the sample S3 exhibits transmission characteristics similar to those of the comparative example C1 at a frequency of 1 GHz, the sample S3 achieves excellent transmission characteristics at a frequency of 1 GHz or more compared to the comparative example C1.
Specifically, in all samples S11, S12, and S13 illustrated in
As illustrated in
C≥3 pF (2)
The common mode choke coil 20 includes a core part 27, a pair of flange parts 28 and 29, and a plurality of wires 21a, 22a, and 23a. The core part 27 and the pair of flange parts 28 and 29 are, for example, ferrite cores. The core part 27 is a column-shaped member extending in a direction parallel to a surface of the substrate 30. The pair of flange parts 28 and 29 are provided at ends of the core part 27 in a direction in which the core part 27 extends. The pair of flange parts 28 and 29 are formed integrated with the core part 27 and made of the same material as that of the core part 27. However, the pair of flange parts 28 and 29 may be formed separated from the core part 27 and made of a material different from that of the core part 27.
The three wires 21a, 22a, and 23a are wound around the core part 27, and the first coil 21, the second coil 22, and the third coil 23 are thus formed, respectively. The winding directions of the three wires 21a, 22a, and 23a are the same. That is, when currents of the same phase flow in the three wires 21a, 22a, and 23a, magnetic fields are generated at the core part 27 such that the magnetic fields enhance one another. When currents of different phases flow in the three wires 21a, 22a, and 23a, magnetic fields are generated at the core part 27 such that the magnetic fields cancel one another out.
A first outer electrode 24a, a second outer electrode 24b, and a third outer electrode 24c are provided on a bottom face of the flange part 29. In a similar manner, a first outer electrode 24a, a second outer electrode 24b, and a third outer electrode 24c are provided on a bottom face of the flange part 28 (in
The capacitor 25 is provided in adjacent to the core part 27 and the plurality of wires 21a, 22a, and 23a and is provided between the pair of facing flange parts 28 and 29. One end of the capacitor 25 is connected to the third outer electrode 24c of the flange part 28, and the other end of the capacitor 25 is connected to the third outer electrode 24c of the flange part 29. As described above, the capacitor 25 is provided as a component integrated with the first coil 21, the second coil 22, and the third coil 23 of the common mode choke coil 20. Thus, compared to the case where the capacitor 25 is provided separated from the common mode choke coil 20, the size of the electronic circuit 1 can be reduced.
The configuration of the common mode choke coil 20 and the capacitor 25 illustrated in
As described above, the electronic circuit 1 according to this embodiment includes the shield line 10, the signal ground 31, the frame ground 32, the common mode choke coil 20, and the capacitor 25. The shield line 10 includes the first signal line 11a, the second signal line 11b, and the shield 15, the first signal line 11a and the second signal line 11b being connected to the signal source 41, the shield 15 coating around the first signal line 11a and the second signal line 11b. The signal ground 31 is provided near the signal source 41. The frame ground 32 is isolated from the signal ground 31 and is connected to the shield 15. The common mode choke coil 20 includes the first coil 21, the second coil 22, and the third coil 23 that are magnetically coupled to one another. The capacitor 25 is connected in parallel with the third coil 23. The first coil 21 is connected in series between the signal source 41 and the first signal line 11a, the second coil 22 is connected in series between the signal source 41 and the second signal line 11b, and the third coil 23 and the capacitor 25 that are connected in parallel are connected between the signal ground 31 and the frame ground 32.
Thus, since the capacitor 25 is provided in parallel with the third coil 23, the electronic circuit 1 exhibits excellent attenuation characteristics in a low frequency band, compared to the case where the capacitor 25 is not provided. Furthermore, by appropriately setting the capacitance value C of the capacitor 25 in accordance with the frequency of common mode noise, the common mode noise can be reduced effectively. Furthermore, the signal ground 31, the LC filter formed by the third coil 23 and the capacitor 25, which are connected in parallel, and the frame ground 32 configure a return path for a signal. Thus, compared to the case where an LC filter is not provided between the signal ground 31 and the frame ground 32, the return path can be shortened. Therefore, generation of common mode noise can be reduced. Accordingly, the size of the electronic circuit 1 can be reduced, and noise in the electronic circuit 1 can be reduced effectively.
Furthermore, in the electronic circuit 1, the capacitor 25 is a capacitor element.
Thus, the capacitance value C of the capacitor 25 can be varied easily in accordance with the frequency of common mode noise.
Furthermore, the first coil 21, the second coil 22, the third coil 23, and the capacitor 25 are integrated into a component in the electronic circuit 1.
Thus, the size of the electronic circuit 1 can be reduced.
Furthermore, in the electronic circuit 1, the common mode choke coil 20 includes the core part 27, the pair of flange parts 28 and 29 that are provided at ends of the core part 27, the first outer electrode 24a, the second outer electrode 24b, and the third outer electrode 24c that are provided at each of the pair of flange parts 28 and 29, and the three wires 21a, 22a, and 23a. The wires 21a, 22a, and 23a are wound around the core part 27 to form the first coil 21, the second coil 22, and third coil 23, respectively. Both ends of the first coil 21 are connected to the first outer electrodes 24a, both ends of the second coil 22 are connected to the second outer electrodes 24b, and both ends of the third coil 23 are connected to the third outer electrodes 24c. The capacitor 25 is provided between the pair of facing flange parts 28 and 29 and is connected to the third outer electrodes 24c.
Thus, the common mode choke coil 20 and the capacitor 25 are integrated into a component. Therefore, the size of the electronic circuit 1 can be reduced.
Furthermore, in the electronic circuit 1, the inductance value L of the common mode choke coil 20 and the capacitance value C of the capacitor 25 are represented by
1.6×10−19≤L×C≤2.5×10−14 and
C≥3 pF.
Thus, the electronic circuit 1 can achieve an excellent noise reduction effect within a range between 1 MHz and 400 MHz, both inclusive, which is required in an immunity test, and can secure a return path for a signal at a frequency of 1 GHz or more.
The embodiments described above are intended to facilitate understanding of the present disclosure and are not intended to be interpreted as limiting the present disclosure. The present disclosure may be modified/improved without departing from the scope of the present disclosure. The present disclosure also encompasses equivalents thereof.
Number | Date | Country | Kind |
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2019-238218 | Dec 2019 | JP | national |
This application claims benefit of priority to International Patent Application No. PCT/JP2020/040451, filed Oct. 28, 2020, and to Japanese Patent Application No. 2019-238218, filed Dec. 27, 2019, the entire contents of each are incorporated herein by reference.
Number | Date | Country | |
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Parent | PCT/JP2020/040451 | Oct 2020 | US |
Child | 17848683 | US |