1. Field of Invention
The present invention relates generally to semiconductor devices and more particularly to semiconductor devices configured for power applications.
2. Related Art
Complementary metal-oxide semiconductor (CMOS) devices designed for radio-frequency (RF) power applications have traditionally required a tradeoff between improved RF performance versus a higher breakdown voltage. For example, the RF performance of a CMOS device may be improved by reducing gate geometries (e.g., by using short channel lengths). A smaller gate geometry, however, reduces the breakdown voltage of the CMOS device. Because the reduced breakdown voltage limits the voltage swing available at the output of the CMOS device in an amplifier configuration, such CMOS devices are less useful in power applications.
In one approach to the breakdown voltage problem, CMOS devices may be designed for greater current drive with a lower voltage swing. Greater current drive may, however, require the width of a transistor in the CMOS device to be made large thus presenting an undesired capacitive load to the driving circuit.
Another approach to the breakdown voltage problem uses Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) transistors. LDMOS transistors have a drift region between an active region and a drain. The drift region is lightly doped and experiences the largest voltage swings. Because the doping concentration in the drift region is limited by the breakdown voltage requirements, LDMOS devices tradeoff a higher breakdown voltage for a higher total resistance of the drain-current flowing between the drain and the source terminals (known as the on-state resistance).
Another approach to the breakdown voltage problem uses devices with thicker and higher resistivity substrates. These devices may offer higher-voltage performance but also introduce higher on-state losses. These devices include Reduced Surface Field (RESURF) devices in which the depletion region of the substrate diode interacts with the depletion region of the lateral diode to reduce the surface field. In these devices, the voltage breakdown is increased because of the lateral widening of the depletion zone.
There is, therefore, a need for a high breakdown voltage semiconductor device that provides improved RF capability and higher power as compared to conventional semiconductor devices.
The present invention provides various electronic circuits for use as power amplifiers for amplifying input signals. An exemplary circuit comprises a MOSFET and a JFET, both including a source and a drain, where the source of the JFET is directly coupled to the drain of the MOSFET. The MOSFET also includes a gate, while the JFET also includes both a top gate and a bottom gate. The gates of the MOSFET and of the JFET, in some embodiments, have different widths. In various embodiments the source and drain of both the MOSFET and JFET, and the top and bottom gates of the JFET, are defined within the substrate, while the gate of the MOSFET gate is disposed on the substrate. In some instances the substrate comprises a silicon on insulator wafer having a silicon layer over an insulator layer, and in these embodiments the features defined within the substrate are defined within the silicon layer.
In various embodiments the top gate of the JFET is coupled to the gate of the MOSFET. In some of these embodiments the bottom gate of the JFET is also coupled to the gate of the MOSFET, and in some of these embodiments the top and bottom gates of the JFET are both coupled to a DC bias source.
In various embodiments of the exemplary circuit the top gate of the JFET is coupled to the bottom gate of the JFET and both gates are independent of the gate of the MOSFET. In some of these embodiments the top and bottom gates of the JFET are both coupled to a DC bias source, while in other of these embodiments the top and bottom gates of the JFET are both coupled to ground. In still further of these embodiments the top gate of the JFET is coupled to a first DC bias source and/or the bottom gate of the JFET is coupled to a second DC bias source or ground.
The present invention is also directed to various devices. An exemplary device comprises a transceiver coupled to a power amplifier as set forth above. The transceiver, in various embodiments, is configured to produce a signal having a frequency in the range of about 700 MHz to about 2.5 GHz or to produce a signal having a frequency in the range of about 150 MHz to about 6 GHz. In some embodiments the transceiver is disposed on a same substrate as the MOSFET and the JFET. Various embodiments further comprise an output matching circuit coupled to the drain of the JFET.
Further, the present invention also provides methods for signal amplification. An exemplary method comprises controlling a gate of a MOSFET with a first signal, controlling a top gate of a JFET with a second signal, and controlling a bottom gate of the JFET with a third signal, where the JFET is in a cascode configuration with the MOSFET. In various embodiments the second signal is dependent on the first signal and in some of these embodiments the third signal is dependent on the second signal. Similarly, in various embodiments the second signal is independent on the first signal and in some of these embodiments the third signal is dependent on the second signal.
The present invention further provides methods of making electronic circuits. An exemplary method comprises providing a silicon on insulator wafer having a silicon layer over an insulator layer embedded within the wafer, defining within the silicon of the wafer, such as by ion implantation, a MOSFET including a source and a drain defining within the silicon of the wafer a JFET including a source, a drain, a top gate, and a bottom gate, and forming a gate of the MOSFET on the silicon, such as by photolithography. In various embodiments the method further includes forming a metal layer in electrical communication with both the source of the JFET and the drain of the MOSFET so that the source of the JFET is directly coupled to the drain of the MOSFET.
Elements in the figures are illustrated for simplicity and clarity and are not drawn to scale. The dimensions of some of the elements may be exaggerated relative to other elements to help improve the understanding of various embodiments of the invention.
The present disclosure is directed to double-gate semiconductor devices characterized by high breakdown voltages that allow for a large excursion of the output voltage, making these semiconductor devices useful for power applications, such as power amplification. The double-gate semiconductor devices disclosed herein comprise a metal-oxide-semiconductor (MOS) gate and a junction gate, in which the bias of the junction gate may be a function of the gate voltage of the MOS gate. The breakdown voltage of such a double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. Because an individual junction gate has an intrinsically high breakdown voltage, the breakdown voltage of the double-gate semiconductor device is higher than the breakdown voltage of an individual MOS gate.
The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional complementary metal-oxide semiconductor (CMOS) devices. The double-gate semiconductor device may be fabricated substantially on and/or in a substrate using techniques of semiconductor fabrication known in the art and may use standard fabrication processes for CMOS and logic devices with minor modifications in the process flow.
A MOS gate may include a metal-oxide-semiconductor structure that, when a voltage is applied to the MOS gate, modifies the charge distribution in a semiconductor structure, thus controlling the conductive characteristics of the semiconductor structure. The MOS gate can thus function as an electrically-controlled gate or switch. This type of gate may be found in a metal-oxide-semiconductor field effect transistor (MOSFET) device. A junction gate includes a region of a channel of semiconductor material that has doping characteristics that are opposite that of the rest of the channel such that when a voltage is applied to the junction gate the charge distribution in the channel is modified and thereby controls the conductive characteristics of the channel. The junction gate can thus function as an electrically-controlled gate or switch. This type of gate may be found in a junction field effect transistor (JFET). The effective resistance of the junction gate is the resistance of the channel as controlled by the voltage of the junction gate.
Double-gate semiconductor devices disclosed herein may be fabricated to include one or more implantation regions between the MOS gate and the junction gate. Embodiments without an implantation region between the MOS gate and the junction gate may provide a higher spatial density configuration for the double-gate semiconductor device than embodiments that include one or more implantation regions between the MOS gate and the junction gate. The principles of operation of these various embodiments are similar, except that a depletion region between the MOS gate channel and a drift region is modified.
Double-gate semiconductor device 100 comprises P− substrate 110, a N− well 120 formed in the P− substrate 110, N+ source 130, gate 140, oxide layer 150, N+ region 160, N+ region 162, P+ gate 170, and N+ drain 180. As used herein, the “+” symbol indicates strong doping of the conductivity type indicated (e.g., N+ indicating N type, strong doping) and the “−” symbol indicates weak doping of the conductivity type indicated (e.g., P− indicating P type, weak doping).
Electrical signals, such as Vg1 and control voltage Vg2, may be coupled to gate 140 and P+ gate 170, respectively. Electrical signals may also be coupled to N+ source 130, N+ region 160, N+ region 162 and N+ drain 180 using additional polysilicon layers (not shown) or metal layers (not shown) disposed on a surface of each of the N+ source 130, N+ region 160, N+ region 162 and N+ drain 180 using semiconductor fabrication techniques known in the art.
Double-gate semiconductor device 100 includes an N-type MOS Field Effect Transistor (also known as a N-channel MOSFET) formed by P− substrate 110, N+ source 130, and N+ region 160, gate 140, and oxide layer 150. The double-gate semiconductor device 100 also includes an N-channel Junction Field Effect Transistor (also known as an N-type JFET) formed by P− substrate 110, N− well 120, N+ region 162, P+ gate 170 and N+ drain 180. In this embodiment, N+ region 160 and N+ region 162 are adjacent and N+ region 162 is disposed substantially in N− well 120.
Alternatively, the elements of the double-gate semiconductor device 100 may be configured so that the double-gate semiconductor device 100 comprises a P-type MOS gate including a P-channel junction gate. In such an embodiment, some of the regions and/or layers of doped silicon may have a different doping, according to semiconductor fabrication techniques known in the art.
The double-gate semiconductor device 100 may be considered to operate in two modes. A first mode, illustrated in
Returning to
When a control voltage Vg2 is applied to P+ gate 170 such that |Vg2−VPI|≈0 (corresponding to the first mode), the channel is open and a current of majority carriers may flow between N+ region 162 and N+ drain 180. The P+ gate 170 (the junction gate) may, therefore, behave equivalently to a variable resistor with a high effective resistance, Roff, that allows little or no current flow between N+ source 130 and N+ drain 180 when |Vg2−VPI|>Voff, and a low effective resistance, Ron, allowing maximum current flow when |Vg2−VPI|≈0.
The double-gate semiconductor device 100 may include a device with a double gate in which the control voltage Vg2 at P+ gate 170 (the junction gate) may be a function of the voltage Vg1 at gate 140 (the MOS gate). The MOS gate and the junction gate may both be dynamically biased in the “on” state or “off” state at the same time using a control circuitry described with reference to
The high effective resistance, Roff, in the second mode of operation allows the P+ gate 170 to sustain a high voltage and limits the voltage potential between gate 140 and N+ region 160 to less than the MOS gate breakdown voltage. Because the breakdown voltage of the double-gate semiconductor device 100 is the sum of the breakdown voltages of the MOS gate and the P+ gate 170, the intrinsically high breakdown voltage of the P+ gate 170 provides the high breakdown voltage of the double-gate semiconductor device 100.
The control voltage Vg2 may be adjusted using the control circuitry and may depend on the pinch-off voltage, Voff. The control circuitry may comprise a capacitor (not shown) configured to couple a RF signal from gate 140 to P+ gate 170. To limit the distance between gate 140 and P+ gate 170, the capacitor may be implemented with multiple stacked metal layers in parallel between the gate 140 and P+ gate 170.
Double-gate semiconductor device 200 comprises P− substrate 110, a N− well 120 formed in the P− substrate 110, N+ source 130, gate 140, oxide layer 150, N+ region 260, N+ region 262, conducting layer 265, P+ gate 170, and N+ drain 180. Conducting layer 265 may be a polysilicon layer, a metal layer or another conducting layer known in the art. As illustrated in
As discussed herein with respect to double-gate semiconductor device 200, electrical signals, such as Vg1 and control voltage Vg2, may be coupled to gate 140 and P+ gate 170, respectively. Electrical signals may also be coupled to N+ source 130, N+ region 260, N+ region 262 and N+ drain 180 using additional polysilicon layers (not shown) or metal layers (not shown) disposed on a surface of each of the N+ source 130, N+ region 260, N+ region 262 and N+ drain 180 using semiconductor fabrication techniques known in the art.
Double-gate semiconductor device 200 includes an N-type MOSFET formed by P− substrate 110, N− well 120, N+ source 130, and N+ region 260, gate 140, and oxide layer 150. The double-gate semiconductor device 200 also includes an N-channel JFET formed by P− substrate 110, N− well 120, N+ region 262, P+ gate 170 and N+ drain 180. In this embodiment, N+ region 260 and N+ region 262 are coupled using conducting layer 265.
Alternatively, the elements of the double-gate semiconductor device 200 may be configured so that the double-gate semiconductor device 200 comprises a P-type MOS gate including a P-channel junction gate or an N-type MOS gate including a P-channel junction gate or a P-type MOS gate including a N-channel junction gate. In such an embodiment, some of the regions and/or layers of doped silicon may have a different doping, according to semiconductor fabrication techniques known in the art.
The double-gate semiconductor device 200 may be considered to operate analogously to the two modes as described herein with respect to
When a control voltage Vg2 is applied to P+ gate 170 such that |Vg2−VPI|≈0 (corresponding to the first mode), the channel is open and a current of majority carriers may flow between N+ region 262 and N+ drain 180. The P+ gate 170 (the junction gate) may, therefore, behave equivalently to a variable resistor with a high effective resistance, Roff, that allows little or no current flow between N+ source 130 and N+ drain 180 when |Vg2−VPI|>≈Voff, and a low effective resistance, Ron, allowing maximum current flow when |Vg2−VPI|≈0.
The double-gate semiconductor device 200 may include a device with a double-gate in which the control voltage Vg2 at P+ gate 170, the junction gate, may be a function of the voltage Vg1 at gate 140. The MOS gate and the junction gate may both be dynamically biased in the “on” state or “off” state at the same time using a control circuitry described with reference to
In the second mode of operation, the high effective resistance, Roff, allows the P+ gate 170 to sustain a high voltage and limits the voltage potential between gate 140 and N+ region 260 to less than the MOS gate breakdown voltage. Because the breakdown voltage of the double-gate semiconductor device 200 is the sum of the breakdown voltages of the MOS gate and the P+ gate 170, the intrinsically high breakdown voltage of the P+ gate 170 provides the high breakdown voltage of the double-gate semiconductor device 200.
As described with reference to
Double-gate semiconductor device 300 includes an N-type MOS gate formed by P− substrate 110, gate 140, and oxide layer 150. The double-gate semiconductor device 300 also includes an N-channel JFET formed by P− substrate 110, N− well 120, N+ region 360, P+ gate 170 and N+ drain 180. In this embodiment, the N+ region 360 is a source of the N-channel JFET and abuts the N-type MOS gate, the N-type MOS gate comprising gate 140 and oxide layer 150.
The double-gate semiconductor device 300 may be considered to operate analogously to the two modes as described herein with respect to
When a control voltage Vg2 is applied to P+ gate 170 such that |Vg2−VPI|≈0 (corresponding to the first mode), the channel is open and a current of majority carriers may flow between N+ region 360 and N+ drain 180. The P+ gate 170 (the junction gate) may, therefore, be considered as behaving equivalently to a variable resistor with a high effective resistance, Roff, that allows little or no current flow between N+ source 130 and N+ drain 180 when |Vg2−VPI|>Voff, and a low effective resistance, Ron, allowing maximum current flow when |Vg2−VPI|≈0.
As described with reference to
In the second mode of operation, the high effective resistance, Roff, allows the P+ gate 170 to sustain a high voltage and limits the voltage potential between gate 140 and N+ region 360 to less than the MOS gate breakdown voltage. Because the breakdown voltage of the double-gate semiconductor device 300 is the sum of the breakdown voltages of the MOS gate and the P+ gate 170, the intrinsically high breakdown voltage of the P+ gate 170 provides the high breakdown voltage of the double-gate semiconductor device 300.
In the second mode of operation, the voltage Vg1 applied to gate 140 is lower than the threshold voltage, Vth, so that the MOS gate is “off.” A control voltage Vg2 is applied to the P+ gate 170 so that the junction gate is biased near the pinch-off voltage, Voff, by using a high potential difference between Vg2 and a voltage VPI of the N+ region 360. The P+ gate 170 thus presents a high effective resistance, Roff, to the current flow in a drift region, such as drift region 420 illustrated in
The high effective resistance, Roff, in the second mode of operation allows the P+ gate 170 to sustain a high voltage and limits the voltage swing at gate 140 to less than the MOS gate breakdown voltage. The second mode of operation effectively protects the gate 140 from voltages greater than the breakdown voltage. Because the breakdown voltage of the double-gate semiconductor device 300 is the sum of the breakdown voltages of the MOS gate and the P+ gate 170, the intrinsically high breakdown voltage of the P+ gate 170 provides the high breakdown voltage of the double-gate semiconductor device 300.
The control circuitry 530 provides the control voltage Vg2 to bias N-channel JFET 510 so that the Roff effective resistance is a maximum value when the N-channel MOSFET is “off” (i.e., Vg1<Vth). Typically, the control voltage Vg2 biases N-channel JFET 510 close to the pinch-off voltage, Voff. When the N-channel MOSFET 520 is “on” (i.e., Vg1>Vth), then control circuitry 530 provides the control voltage Vg2 to bias N-channel JFET 510 so that the Ron effective resistance is minimal and the current flow is a maximum. A large range of Ron to Roff effective resistance variation allows a large excursion of voltage at the drain of the N-channel JFET 510 and a corresponding high power capability for the double-gate semiconductor devices described with reference to
Double-gate semiconductor device 600 may be formed from regions and/or layers of doped silicon, polysilicon, metal, and insulating layers using semiconductor fabrication techniques known in the art. The double-gate semiconductor device 600 comprises P− substrate 110, a N− well 120 formed in the P− substrate 110, N+ source 130, gate 140, oxide layer 150, P+ gate 170 and N+ drain 180.
Electrical signals, such as Vg1 and control voltage Vg2, may be coupled to gate 140, and P+ gate 170, respectively. Electrical signals may be coupled to N+ source 130 and N+ drain 180 using additional polysilicon layers (not shown) or metal layers (not shown) disposed on a surface of each of the N+ source 130 and N+ drain 180 using semiconductor fabrication techniques known in the art.
The double-gate semiconductor device 600 may be considered to operate analogously to the two modes of operation described with reference to
In the second mode of operation, the voltage Vg1 applied to gate 140 is lower than a threshold voltage, Vth and a control voltage Vg2 is applied P+ gate 170, thus presenting a high effective resistance, Roff, to the current flow. The high effective resistance, Roff, results from a depletion region, similar to the depletion region 410 described with reference to
The MOSFET 705 and dual-gate JFET 710 are distinct transistors. As used herein, two transistors are defined as distinct unless the transistors share a common implantation region. As an example, N+ regions 260 and 262 (
The MOSFET 705 includes a drain and a source, and in operation the source is coupled to a power supply such as VDD. The MOSFET 705 is controlled by a gate which, in operation, receives an input signal, for example an RF signal, from a signal source such as transceiver 715. Various embodiments of circuit 700 include an input matching circuit 720 between the transceiver 715 and the gate of the MOSFET 705 to match the impedances on either side thereof. An exemplary matching circuit 720 comprises a capacitor and an inductor where the capacitor is coupled between ground and a node between the transceiver 715 and the gate of the MOSFET 705, and the inductor is disposed in-line between the node and the gate of the MOSFET 705. In various embodiments the gate length of the MOSFET 705, i.e. the length of the gate implant located between the source and the drain, is less than one micron. It is noted that gate width is the dimension of the gate in the plane of the substrate measured perpendicular to the gate length. In various embodiments, the MOSFET 705 can be a NMOSFET or a PMOSFET.
The signal source, such as transceiver 715, is disposed on the same substrate as the MOSFET 705 and the dual-gate JFET 710, in some embodiments. In further embodiments, the signal source produces a signal with a frequency in the range of about 700 MHz to about 2.5 GHz. In further embodiments, the signal source produces a signal with a frequency in the range of about 150 MHz to about 6 GHz.
The dual-gate JFET 710 comprises a source and a drain electrically connected by a channel that is controlled by two gates, a top gate 725 and a bottom gate 730 disposed above and below the channel, respectively. In various embodiments, the dual gate JFET 710 can be a NJFET or a PJFET. In various embodiments the dual-gate JFET 710 comprises a sub-micron gate length. The drain of the dual-gate JFET 710 is coupled to an antenna 735 or another device configured for signal transmission. In some embodiments the antenna 735 is coupled to the drain of the dual-gate JFET 710 by an output matching circuit 740 formed with passive networks, also provided to match impedances.
The source of the dual-gate JFET 710 is coupled to the drain of the MOSFET 705. In some embodiments, the source of the dual-gate JFET 710 is directly coupled to the drain of the MOSFET 705. As used herein, “directly coupled” means that there are no active components in electrical communication between the coupled transistors. In some embodiments, the source of the dual-gate JFET 710 is coupled to the drain of the MOSFET 705 through vias and a trace such as conducting layer 265 (
As noted above, the JFET 710 is controlled by a top gate 725 and a bottom gate 730. In various embodiments, the top and bottom gates 725, 730 are dependent (e.g. commonly controlled) or independent, and can be controlled by ground, a DC bias, the input signal applied to the gate of the MOSFET 705, or the input signal plus a DC bias. Various exemplary ways to control the top and bottom gates 725, 730 are discussed with reference to
The JFET gate circuit 745 serves to improve the performance of embodiments of the invention that are used as a power amplifier. The bias of the bottom gate 730 determines the voltage of the top gate 725 to pinch off the JFET 710 where the pinch-off voltage of the JFET 710 is the limit value for the drain of the MOSFET 705. An appropriate value for the bottom gate 730 bias is one that allows that the pinch-off voltage of the JFET 710 to protect the MOSFET 705 in its reliable zone. In some embodiments the top gate 725 of the JFET 710 is maintained at 0V. But the large gate-to-source and gate-to-drain capacitances couple the large voltage of the drain and of the source onto the gate voltage, reducing the efficiency of the Roff and Ron variation of the JFET 710. The function of the JFET gate circuit 745 is to cancel these signals on the top gate 725 by applying an opposing signal.
As shown in
The JFET 810 additionally comprises a drain 835, a top gate 840, and a bottom gate 845. The top gate 840 and bottom gate 845 are disposed above and below an N channel 850 that couples the source 815 to the drain 820 of the JFET 810. The bottom gate 845 is bounded by two P wells 855 that provide an electrical connection to the bottom gate 845. The JFET 810 is disposed within an N well region that comprises two N wells 860 and an N isolation layer 865. The P wells 855 also serve to isolate the N channel 850 from the N wells 860 in these embodiments.
As shown in
Embodiments of electronic circuits illustrated by
In various embodiments, the second signal is dependent upon the first signal and in some of these embodiments the two signals are the same, for example, where the gate of the MOSFET and the top gate of the JFET are capacitively coupled. In some of these embodiments the third signal is also dependent on the first and second signals, such as is illustrated by
In various embodiments the second signal is independent of the first signal, such as is illustrated by
In various embodiments the first signal comprises the sum of the input signal and a DC bias. Also in various embodiments either or both of the second and third signals can be a fixed DC bias, either positive or negative, or ground.
The embodiments discussed herein are illustrative of the present invention. As these embodiments are described with reference to illustrations, various modifications or adaptations of the methods or specific elements described may become apparent to those skilled in the art. All such modifications, adaptations, or variations that rely on the teachings of the present invention, and through which these teachings have advanced the art, are considered to be in the spirit and scope of the present invention. Hence, these descriptions and drawings should not be considered in a limiting sense, as it is understood that the present invention is in no way limited to only the embodiments illustrated.
This application is a Continuation-In-Part of U.S. patent application Ser. No. 13/443,611 filed on Apr. 10, 2012 which is a Continuation of U.S. patent application Ser. No. 13/107,411 filed on May 13, 2011, now U.S. Pat. No. 8,179,197 issued on May 15, 2012, which is a Divisional application of U.S. patent application Ser. No. 12/686,573 filed on Jan. 13, 2010, now U.S. Pat. No. 7,969,243 issued on Jun. 28, 2011, all three entitled “Electronic Circuits including a MOSFET and a Dual-Gate JFET;” U.S. patent application Ser. No. 12/686,573 claims the benefit of U.S. Provisional Patent Application No. 61/171,689 filed on Apr. 22, 2009 and entitled “Electronic Circuits including a MOSFET and a Dual-Gate JFET and having a High Breakdown Voltage;” each of the above patent application are incorporated herein by reference. This application is also related to U.S. patent application Ser. No. 12/070,019 filed on Feb. 13, 2008 and entitled “High Breakdown Voltage Double-Gate Semiconductor Device,” now U.S. Pat. No. 7,863,645 issued on Jan. 4, 2011, which is also incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
4228367 | Brown | Oct 1980 | A |
4255714 | Rosen | Mar 1981 | A |
4353036 | Hoover | Oct 1982 | A |
4523111 | Baliga | Jun 1985 | A |
4811075 | Eklund | Mar 1989 | A |
4864454 | Wolfe | Sep 1989 | A |
5061903 | Vasile | Oct 1991 | A |
5126807 | Baba et al. | Jun 1992 | A |
5296400 | Park et al. | Mar 1994 | A |
5537078 | Strong | Jul 1996 | A |
5543643 | Kapoor | Aug 1996 | A |
5559049 | Cho | Sep 1996 | A |
5677927 | Fullerton et al. | Oct 1997 | A |
5898198 | Herbert et al. | Apr 1999 | A |
5912490 | Hebert et al. | Jun 1999 | A |
5969582 | Boesch et al. | Oct 1999 | A |
6061008 | Abbey | May 2000 | A |
6061555 | Bultman et al. | May 2000 | A |
6081159 | Kim et al. | Jun 2000 | A |
6088484 | Mead | Jul 2000 | A |
6242978 | Danielsons | Jun 2001 | B1 |
6275177 | Ho et al. | Aug 2001 | B1 |
6300835 | Seely et al. | Oct 2001 | B1 |
6384688 | Fujioka et al. | May 2002 | B1 |
6414545 | Zhang | Jul 2002 | B1 |
6503782 | Casady et al. | Jan 2003 | B2 |
6535050 | Baudelot et al. | Mar 2003 | B2 |
6570518 | Riley et al. | May 2003 | B2 |
6600369 | Mitzlaff | Jul 2003 | B2 |
6614281 | Baudelot et al. | Sep 2003 | B1 |
6633195 | Baudelot et al. | Oct 2003 | B2 |
6703684 | Udrea et al. | Mar 2004 | B2 |
6784470 | Davis | Aug 2004 | B2 |
7049669 | Ma et al. | May 2006 | B2 |
7162042 | Spencer et al. | Jan 2007 | B2 |
7259621 | Kusunoki et al. | Aug 2007 | B2 |
7312481 | Chen et al. | Dec 2007 | B2 |
7348826 | Klein et al. | Mar 2008 | B1 |
7378912 | Tanahashi et al. | May 2008 | B2 |
7522079 | Wu | Apr 2009 | B1 |
7554397 | Vitzilaios et al. | Jun 2009 | B2 |
7656229 | Deng et al. | Feb 2010 | B2 |
7679448 | McAdam et al. | Mar 2010 | B1 |
7808415 | Robbe et al. | Oct 2010 | B1 |
7863645 | Masliah et al. | Jan 2011 | B2 |
7952431 | Quack et al. | May 2011 | B2 |
7969243 | Bracale et al. | Jun 2011 | B2 |
7969341 | Robbe et al. | Jun 2011 | B2 |
20010015676 | Takikawa et al. | Aug 2001 | A1 |
20010050589 | Baudelot et al. | Dec 2001 | A1 |
20020058410 | Sung et al. | May 2002 | A1 |
20020093442 | Gupta | Jul 2002 | A1 |
20020094795 | Mitzlaff | Jul 2002 | A1 |
20020105360 | Kim et al. | Aug 2002 | A1 |
20020113650 | Kim et al. | Aug 2002 | A1 |
20020145170 | Murakami | Oct 2002 | A1 |
20030073269 | Tran et al. | Apr 2003 | A1 |
20040085127 | Matsuyoshi | May 2004 | A1 |
20040248529 | Park | Dec 2004 | A1 |
20050007200 | Inoue et al. | Jan 2005 | A1 |
20050212583 | Pai | Sep 2005 | A1 |
20050285189 | Shibib et al. | Dec 2005 | A1 |
20050287966 | Yoshimi et al. | Dec 2005 | A1 |
20060228850 | Tsai et al. | Oct 2006 | A1 |
20070018865 | Chang et al. | Jan 2007 | A1 |
20070178856 | Mitzlaff et al. | Aug 2007 | A1 |
20070182485 | Ko | Aug 2007 | A1 |
20080031382 | Aoki | Feb 2008 | A1 |
20080291069 | Inukai et al. | Nov 2008 | A1 |
20090066549 | Thomsen et al. | Mar 2009 | A1 |
20090286492 | Mallet-Guy et al. | Nov 2009 | A1 |
20100026393 | Keerti et al. | Feb 2010 | A1 |
Number | Date | Country |
---|---|---|
2006009009 | Jan 1996 | EP |
2336485 | Oct 1999 | GB |
125022 | Sep 2001 | IL |
0399466 | Apr 1991 | JP |
10107214 | Apr 1998 | JP |
9956311 | Nov 1999 | WO |
0139451 | May 2001 | WO |
2006054148 | May 2006 | WO |
2007042850 | Apr 2007 | WO |
2007075759 | Jul 2007 | WO |
2008037650 | Apr 2008 | WO |
Entry |
---|
Gautier, D., et al., “Improved Delta Sigma Modulators for High Speed Applications,” Acco Semiconductors, Mar. 25, 2009. |
Azakkour, A. et al., “Challenges for a new integrated Ultra-wideband (UWB) source,” IEEE, 2003 pp. 433-437. |
Azakkour, A. et al., “A new integrated moncycle generator and transmitter for Ultra-wideband (UWB) communications,” IEEE Radio Frequency Circuits Symposium, 2005 pp. 79-82. |
Choi, Y. H. et al., “Gated UWB Pulse Signal Generation,” IEEE, 2004 pp. 122-124. |
PCT/US2008/001938 Int'l Search Report and Written Opinion, Jun. 26, 2008. |
PCT/IB05/003426 Int'l Search Report, Mar. 20, 2006. |
PCT/IB05/003426 Written Opinion, May 16, 2007. |
PCT/IB05/003029 Int'l Search Report, Jul. 6, 2006. |
PCT/IB05/003029 Written Opinion, Mar. 12, 2008. |
PCT/US10/27921 Int'l Search Report and Written Opinion, May 10, 2010. |
PCT/US10/30770 Int'l Search Report and Written Opinion, Jun. 16, 2010. |
PCT/US10/041985 Int'l Search Report and Written Opinion, Sep. 9, 2010. |
PCT/US11/32488 Int'l Search Report and Written Opinion, Jun. 28, 2011. |
Vaes,H. M. J. et al., “High Voltage, High Current Lateral Devices,” IEDM Technical Digest, 1988, pp. 87-90. |
Pocha, Michael D. et al. “Threshold Voltage Controllability in Double-Diffused MOS Transistors,” IEEE Transactions on Electronic Devices, vol. ED-21, No. 12, Dec. 1994. |
U.S. Appl. No. 12/951,958 Non-Final Office Action, mailed Dec. 29, 2010. |
U.S. Appl. No. 12/951,958 Applicants' Amendment A, submitted Mar. 22, 2011. |
U.S. Appl. No. 12/951,958 Final Office Action, mailed May 20, 2011. |
U.S. Appl. No. 12/951,958 Applicants' Amendment B, submitted Jul. 26, 2011. |
U.S. Appl. No. 12/070,019 Pre-Interview First Office Action, mailed Jul. 12, 2010. |
U.S. Appl. No. 12/070,019 Applicants' Amendment A, submitted Jul. 21, 2010. |
U.S. Appl. No. 12/951,972 non-final Office action, mailed Aug. 5, 2011. |
U.S. Appl. No. 12/951,972 Applicants' Amendment B, submitted Sep. 9, 2011. |
U.S. Appl. No. 12/951,972 final Office action, mailed Oct. 19, 2011. |
U.S. Appl. No. 12/951,972 Applicants' Amendment C, submitted Nov. 17, 2011. |
U.S. Appl. No. 12/951,972 Advisory Action, mailed Nov. 29, 2011. |
U.S. Appl. No. 12/951,972 Pre-Brief Conference Request, submitted on Apr. 17, 2012. |
U.S. Appl. No. 12/951,958 non-final Office action, mailed Aug. 9, 2011. |
U.S. Appl. No. 12/951,958 Applicants' Amendment C, submitted Sep. 9, 2011. |
U.S. Appl. No. 12/951,958 final Office action, mailed Oct. 28, 2011. |
U.S. Appl. No. 12/951,958 Applicants' Amendment D, submitted Jan. 30, 2012. |
U.S. Appl. No. 12/951,958 Advisory Actions and Interview Summaries, Feb. to Mar. 2012. |
Search Report for Taiwan Patent Application No. 099112711, completed Aug. 23, 2011. |
Jackel, Lawrence D., et al., “CASFET: A MOSFET-JFET Cascode Device with Ultralow Gate Capacitance,” IEEE Transactions on Electron Devices, IEEE SErvice Center, Pisacataway, NJ, vol. ED-31, No. 12, Dec. 1, 1984, pp. 1752-1754. |
EP 10767521.7 Extended European Search Report mailed Feb. 6, 2013. |
EP 10767521.7 Reply to Extended European Search Report, submitted Jul. 18, 2013. |
JP 2012-507253 First Office Action, mailed May 28, 2013. |
KR 10-2011-7027746 Notice of Preliminary Rejection, mailed Jul. 24, 2013. |
CN 201080017947.3 Office Action, Nov. 5, 2013. |
EP 10767521.7 Article 94(3) EPC Communication, mailed Nov. 27, 2013. |
EP 10767521.7 Applicants' Reply to Article 94(3) EPC Communication, submitted Mar. 24, 2014. |
CN 201080017947.3 Response to First Office Action, submitted Mar. 20, 2014. |
CN 201080017947.3 Second Office Action, mailed Jul. 21, 2014. |
JP 2012-507253 Response to First Office Action, submitted Aug. 28, 2013. |
CN 201080017947.3 Response to Second Office Action, submitted Sep. 24, 2014. |
Number | Date | Country | |
---|---|---|---|
20130248945 A1 | Sep 2013 | US |
Number | Date | Country | |
---|---|---|---|
61171689 | Apr 2009 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 12686573 | Jan 2010 | US |
Child | 13107411 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 13107411 | May 2011 | US |
Child | 13443611 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 13443611 | Apr 2012 | US |
Child | 13803792 | US |