Electronic control system for sewing machines

Abstract

A first memory stores stitch control signals. A second memory stores these signals temporarily and reads them out to enable stitches to be formed. As a pattern is stitched, the first memory is readdressed and stitch control signals are successively written into and read out of the second memory. In one embodiment, the second memory is a RAM--in a second embodiment, the second memory is a shift register. Monostable multivibrators are used to operate the memories.

Description

BRIEF DESCRIPTION OF THE INVENTION

This invention relates to an electronic control for a sewing machine of the type which has a pattern forming device for stitching patterns by varying relative positions of the fabric to be stitched and the needle. More particularly, this invention relates to an electronic control system for a sewing machine which is of simple structure and is able to stitch a large number of patterns.

It is, therefore, a primary object of the invention to store fixed pattern stitch control signals in a first semiconductor memory, and to produce many patterns without being limited to the signals so stored, by providing a second semiconductor memory for receiving signals transferred from the first semiconductor memory or from external sources such as magnetic tape or punch cards.

It is a second object of the invention to carry out exact electronic control of such sewing machine by means of a relatively simplified circuit structure.

The other features and advantages of the invention will be apparent from the following description of the invention in reference to the preferred embodiments as shown in the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a sewing machine in which the present invention is installed; and

FIGS. 2A-B and 3A-B are block diagrams of two preferred embodiments of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In FIG. 1 reference numeral 1 is a machine housing, while reference numeral 2 is an upper shaft of the sewing machine driven by a machine motor (not shown) for vertically reciprocating needle bar 3 and needle 4.

The reference figure PG is a pulse generator which is synchronized with the upper shaft 2 to produce periodic pulses. Pulse generator PG is composed, as is generally known, of a U-shaped element 5 secured to machine housing 1 and carring a light-emitting diode (not shown), a phototransistor (not shown) opposite thereto, and a photo-interrupter 6 secured to upper shaft 2 and rotating therewith. Thus, pulse generator PG issues one positive signal for each rotation of upper shaft 2 when needle 4 is positioned above a needle plate (not shown). SW.sub.1 -SW.sub.5 are pattern selecting switches, and 7 is a control system, 8 is a pulse motor for needle bar 3 laterally connecting rod 9 during rotation of pulse motor 8. Numeral 10 is a pulse motor for feeding the fabric, and controls horizontal movement of feed dog 16 via link 11, feed adjuster 12, fork rod 13, connecting link 14 and a horizontal feeding shaft 15. Numeral 17 is a lower shaft of the sewing machine. Lower shaft 17 rotates in synchronism with upper shaft 2 to rotate a loop taker (not shown).

FIGS. 2A-2B are a block diagram of a first embodiment of the invention, which is shown at 7 in FIG. 1. PS is a pattern selecting device including pattern selecting switches SW.sub.1 -SW.sub.5 shown in FIG. 1. When a pattern is selected, that pattern is latched into latch circuit L.sub.1 in the form of a 3-bit encoded signal. MM.sub.1 is a monostable multivibrator which receives a selection control signal from pattern selecting device PS, and issues a signal in response. C.sub.8, used throughout, denotes a gate terminal of that element in which it is shown. ROM is an electronic read-only memory storing stitch control signals, which has 8 address terminals D.sub.1 -D.sub.4 and 16 output terminals E.sub.1 -E.sub.3. E.sub.1 outputs 6 bits for successively addressing ROM itself, E.sub.2 outputs 5 bits for controlling fabric feed, and E.sub.3 outputs 5 bits for swinging needle 3. MP.sub.1 is a multiplexer having a mode input terminal M. Multiplexer MP.sub.1 connects terminal D2 of memory ROM to an input signal at A issued from latch circuit L.sub.1 when mode input terminal M is logically high and connects terminal D2 to an input signal at B issued from timing buffer TB when mode input terminal M is logically low. Timing buffer TB receives the address changing output at terminals E.sub.1 and addresses inputs D.sub.1 and D.sub.2 of memory ROM. Timing buffer TB is reset when it receives at reset terminal R a pattern selection signal via OR gate OR.sub.1, which signal is generated by monstable multivibrator MM.sub.1. Timing buffer TB then receives an astable signal from monostable multivibrator MM.sub.4 via OR-gate OR.sub.2 and successively transmits the address changing signal at terminals E.sub.1 to address input terminals D.sub.1 and D.sub.2 each time the astable signal falls prior to actual stitching. Read-only memory ROM then transfers all the signals of the selected pattern which appear at terminals E.sub.2 and E.sub.3 to a random access memory RAM. The oscillation velocity of the astable signal from monostable multivibrator MM.sub.4 is, therefore, the readout velocity of read-only memory ROM. FF.sub.1 and FF.sub.2 are flip-flops and receive the output of monostable multivibrator MM.sub.1 at their set terminals S. Flip-flop FF.sub.1 receives the astable signal from monostable multivibrator MM.sub.4 at its reset terminal R, and has an its output Q connected to the mode input M of multiplexer MP.sub.1. Flip-flop FF.sub.2 has a true output Q connected to an enable terminal OE.sub.M of read-only memory ROM. Therefore, flip-flop FF.sub.2 is set by the pattern selection signal from monostable multivibrator MM.sub.1 to activate read-only memory ROM and to read out the data therein. MM.sub.2, MM.sub.3, and MM.sub.4 are monostable multivibrators each connected, via OR gate OR.sub.3, to the output of MM.sub.1 and are triggered on negative flanks of signals thereat. Monostable multivibrator MM.sub.3 has an output connected to write-in terminal W of memory RAM, and monostable multivibrator MM.sub.4 has an output connected to one input of AND-gate AND.sub.1. True output Q of flip-flop FF.sub.2 is connected to another input of AND.sub.1 and is connected to an input terminal of monostable multivibrator MM.sub.2 via OR-gate OR.sub.3. Thus MM.sub.2, MM.sub.3, and MM.sub.4 begin oscillating upon negative flanks of the signal from monostable multivibrator MM.sub.1, and continue during the set period of flip-flop FF.sub.2. Flip-flop FF.sub.1, receiving the oscillating signal from MM.sub.4 at resetting terminal R, is set by a pattern selecting signal from MM.sub.1, and is reset by the following signal from MM.sub.4. Thus, just after the pattern selection, the multiplexer MP.sub.1 is caused route the signal at terminal A of the latch circuit L.sub.1 to address terminal D.sub.2 of the ROM. Thereafter, multiplexer MP.sub.1 is caused to similarly route the signal at terminal B, which signal is successively issued via timing buffer TB. Of the address signals for reading out an initial stitching signal of the pattern, the data at terminals D.sub.1 are all initially 0. The address changing signal at terminals E.sub.1, as compared with the final stitching signal has, at this time, an uppermost 1 bit which is identical with the signal at input A of the multiplexer MP.sub.1, all other bits being 0. AND-gate AND.sub.3 receives an output signal from exclusive OR-gate ExOR for detecting whether or not these signals are the same, and likewise receives an output from AND-gate AND.sub.2 for detecting whether or not they are both 0. AND.sub.3 is connected to resetting terminal R of flip-flop FF.sub.3 via OR.sub.4 and AND.sub.4 (which is also connected at an input to the output of MM.sub.4) and resets the flip-flops when ROM reads out the final stitching signal. FF.sub.3 is a flip-flop which is reset together with flip-flop FF.sub.2. The output of AND-gate AND.sub.5 (which has inputs connected to complement outputs Q of FF.sub.2 and FF.sub.3) is connected to an input of MM.sub.5. The output of MM.sub.5 is connected to the resetting terminals R of MM.sub.2, MM.sub.3 and MM.sub.4 and also is connected to the other input of OR.sub.1 so as to reset MM.sub.2, MM.sub.3 and MM.sub.4 and the timing buffer TB when the final stitching signal is produced. C is a counter, and the output of AND.sub.6 (which has inputs connected to the output of OR.sub.4 and the output of MM.sub.3) and the output of AND.sub.5 are both connected to its resetting terminal R via OR.sub.5. Counter C is counted up by output of MM.sub.2, and its 6-bit output is connected to the address changing terminals C.sub.1 of the RAM to be stored matching pattern input data of inputs F.sub.2 and F.sub.3 of RAM, as well being connected to the address signal terminal G of RAM via latch circuit L.sub.2 and multiplexor MP.sub.2, so that the counter C may write in the RAM. Latch circuit L.sub.2 receives the outputs of AND.sub.5 and MM.sub.4 via OR.sub.6 at its gate terminal C.sub.p. The multiplexer MP.sub.2 receives the output of AND.sub.5 at its mode input M, and when mode input M is logically low, MP.sub.2 transmits the signal at inputs C.sub.2 from counter C to serve as an address signal at G for writing in RAM. When mode input M is logically high, MP.sub.2 transmits at inputs H'.sub.1 from the 6 bit output H.sub.1 of RAM for use as an address signal to G. RAM operates substantially the same as does ROM in readout mode, and timing buffer TB is used both with ROM and with RAM. However, at their gate inputs, ROM receives the astable signal from MM.sub.4, while RAM receives signals from pulse generator PG (shown in FIG. 1) via OR.sub.3. Terminals H.sub.2 and H.sub.3 of 5 bits each are connected to pulse motor driving device DV to drive it with stitching signals which are produced in the same order as the fabric feed controlling signals from outputs E.sub.2 or K.sub.2 and needle swinging amplitude signals from E.sub.3 or K.sub.3, i.e. from ROM or an external memory reader device ExR. OE.sub.A of RAM is an enable terminal connected to the output of AND.sub.5 so as to read out the RAM when OE.sub.A is logically high. ExR is an external memory reader which employes magnetic tape or punch cards, and 5 bit stitching signal outputs K.sub.2 and K.sub.3 are connected to outputs E.sub.2 and E.sub.3 of ROM and thus to inputs F.sub.2 and F.sub.3 of RAM. Terminal RD carries a readout signal which is produced in response to manual operation when reader ExR is used, and this readout signal is delivered to set terminal S of FF.sub.3. True output terminal Q of FF.sub.3 is connected to the terminal OE.sub.X of RAM, and manual operation causes a readout of ExR and a write in of RAM until such readout ceases, as is the case with the ROM. SY is a synchronous signal output terminal which carries a signal generated in response to each of the stitching signals. This signal is delivered to an input of OR.sub.3 so as to cause MM.sub.2, MM.sub.3, MM.sub.4 to issue a one shot pulse each time the signal is produced, so as to count up counter C and to activate terminal W of RAM and latch circuit L.sub.2. END is an ending signal output terminal matched with said stitching signals K.sub.2, K.sub.3 for recognizing end of readout by detecting an 11th bit of data, and is connected to an input of OR.sub.4. END is reset along with FF.sub.3, by the ending signal matching control signal of the final stitch so as to stop readout of ExR and write in into the RAM.

In this first embodiment when any of the pattern selecting switches SW.sub.1 -SW.sub.5 in pattern selector PS is operated in order to stitch the corresponding pattern according to data stored in ROM, a 3 bit code designating the pattern is produced, and this code is latched into latch circuit L.sub.1 while MM.sub.1 operates FF.sub.1 sets and multiplexer MP.sub.1 transmits a 3 bit address code to inputs D.sub.2, D.sub.3 and D.sub.4 of ROM to serve as a pattern code. Since TB is reset via OR.sub.1, the address bits at D.sub.1 of ROM are all 0, and the code composed of the address data at D.sub.1, D.sub.2, D.sub.3 and D.sub.4 is set to generate the initial stitching signals at E.sub.2 and E.sub.3, with FF.sub.2 being concurrently set for producing the address signal for reading out the second addressing signal at E.sub.1 to cause the enable terminal OE.sub.M to readout the ROM. The pattern selecting signal causes MM.sub.2 to issue a one shot pulse via OR.sub.3 and counts counter C to a decimal code 1 on the negative pulse flank. This makes the address changing date at C.sub.1 match the initial stitching signals E.sub.2 and E.sub.3 of the RAM for addressing the next (i.e. the second) stitch. MM.sub.3 issues a one shot pulse at the negative flank of the pulse from pulse terminal W of the RAM, beginning write in. The address data at G is all 0's at this time, since mode input M of MP.sub.2 is at logically low via AND.sub.5 and does not receive the gate signal at Cp of latch circuit L.sub.2, and the address data at G stores a signal which matches the initial stitching signal and the 2nd stitch addressing signal at the 0 address. Subsequently, MM.sub.4 issues a one shot upon a negative flank of the pulse from MM.sub.3. FF.sub.1 is thus reset by this signal and MP.sub.1 transfers the data at B (which has passed through TB) to input D.sub.2 of ROM. Latch circuit L.sub.2 receives the gate signal at Cp via OR.sub.6 and latches decimal code 1 from the counter C, to cause the address data at G of RAM to correspond to an address of 1. The rising output signal from MM.sub.4 gives a signal to the gate Cp of TB and transfers the addressing signals E.sub.1 for the 2nd stitch to address terminals D.sub.1 and D.sub.2 of ROM. A match of the signals at address terminals D.sub.1 and D.sub.2 and signals at D.sub.3 and D.sub.4 from PS forms an address signal for reading out the 2nd stitch signals at E.sub.2 and E.sub.3 and the addressing signal to the third stitch. MM.sub.2 then issues another one shot pulse via AND.sub.1 and OR.sub.3 upon the negative flank of the output signal from MM.sub.4. Subsequently MM.sub.2, MM.sub.3 and MM.sub.4 successively advance one shot pulses and repeat them to read out the ROM write in RAM. The address changing signal at E.sub.1 coincides at its uppermost bit with the lowest bit from latch circuit L.sub.1. ROM reads out final stitching signals at E.sub.2 and E.sub.3 in accordance with the address signals appearing at D.sub.1 and D.sub.2, which address signals pass through TB as the output signal from MM.sub.4 rises. Since the lower 5 bits at E.sub.1 remain 0, the output of AND.sub.2 is brought logically high. Moreover, the output of ExOR is low, so that the output of AND.sub.3 goes high and the output of OR.sub.4 goes logically high.

Meanwhile, the output from MM.sub.4 drops, causing the output of MM.sub.2 to drop, causing counter C to count up one count. A subsequent pulse from MM.sub.3 resets counter C via AND.sub.6 and OR.sub.5, since the output of OR.sub.4 is still logically high. Thus, the data appearing at RAM inputs C.sub.1 is all zero. Since terminal W of RAM is logically high, RAM is placed in the writein mode, and the latter serves as an initial stitch addressing signal enabling the data at ROM outputs E.sub.2 and E.sub.3 to be written into RAM. A subsequent output signal from MM.sub.4 resets FF.sub.2 and FF.sub.3 via AND.sub.4 (which receives the logically high output of OR.sub.4), resets MM.sub.2, MM.sub.3 and MM.sub.4 via AND.sub.5 and MM.sub.5, and further resets TB via OR.sub.1 so that transfer of data from ROM to RAM is completed. The high output of AND.sub.5 is delivered to enable terminal OE.sub.A of RAM to cause RAM to operate in the readout mode. The high output of AND.sub.5 is delivered via OR.sub.5, to terminal R of counter C, to reset counter C and to start writein in RAM.

The ending of such writein causes RAM to give an initial stitch control signal to the pulse motor driving device DV. The mode of the multiplexer MP is changed by the logically high output of AND.sub.5 and the address signal at G of RAM turns into a signal passing through TB, but TB designates the 0 address upon resetting and issues an output of an initial stitching signal. When the sewing machine is driven, the pulse generator PG issues one pulse for early rotation of the sewing machine, and the timing buffer TB transfers addressing data at H.sub.1 of RAM to the addressing terminal G upon each rotation to advance the stitching signals at H.sub.2 and H.sub.3. When the stitching pattern is finished, the pattern i- returned to its initial state, and TB repeatedly delivers a stitch controlling signal to the pulse motor driving device DV so as to drive the pulse motors 10 and 8 for controlling the needle swing and fabric feed.

With respect to the data transfer to RAM from the external storing device ExR, for reading magnetic tape or punched cards when the reader is operated, the readout command signal at RD sets FF.sub.3 and gives a signal to the enable terminal OE.sub.X to make the pattern controlling signals at K.sub.2 and K.sub.3 available to RAM. When the pattern controlling signal is produced, the synchroneous signal SY is produced synchronously therewith to cause MM.sub.2, MM.sub.3 and MM.sub.4 to issue one shot pulses in succession. ExR like ROM during readout, stores only one stitching signal, and a subsequent signal at SY causes a following stitching signal to be stored, and when storage of all the stitches is finished an end signal at END resets FF.sub.3 via OR.sub.4 to finish readout operation and writein in RAM, so that RAM can subsequently be read out.

The second embodiment of the invention shown in FIG. 2 employes the random access memory RAM for temporary storage, while the second embodiment uses a shift register SR. Parts common to those in FIG. 2 are designated with the same reference characters and explanation thereof will be omitted. ROM is read out in the same fashion as in FIG. 2. For simplicity the 5 bit pattern control signal terminals E.sub.2 and E.sub.3 and terminals connected thereto are shown as one terminal and one connecting line. SR is a shift register in which input terminals V.sub.2 and V.sub.3 of 5 bits each receive stitch control signals from E.sub.2 and E.sub.3 of ROM and stitching control signals from K.sub.2 and K.sub.3 of ExR. SR is composed of parallel connections of 11 bits between input terminals V.sub.2 and V.sub.3, output terminals W.sub.2 and W.sub.3 (of 5 bits each) an input terminal V.sub.1 for determining whether or not data entering from input terminals V.sub.2 and V.sub.3 are stitching signals, and output terminal W.sub.1. The shift register has a resetting terminal R receiving an output signal from MM.sub.1 and from RD of ExR via OR.sub.7, and also has a shift pulse input terminal Cp. Output terminals W.sub.1, W.sub.2 and W.sub.3 provide 11-bit data to input terminals V.sub.1, V.sub.2 and V.sub.3, and the signals at terminals W.sub.2 and W.sub.3 compose the stitch control signal and are connected to DV via a latch circuit L.sub.3. Shift register ST of the input terminals V.sub.1, V.sub.2, V.sub.3 and the output terminals W.sub.1 , W.sub.2, W.sub.3 of respective 11 tracks at both sides, has the bit number (step number) which is more than the maximum stitch number of the pattern to be selected and is the same number. Shift register SR stores the pattern signals E.sub.2 and E.sub.3 or K.sub.2 and K.sub.3 at the shift pulse terminal Cp, and receives the output of MM.sub.4 via OR.sub.8 in order to shift said pattern signals. AM is an astable multivibrator whose enable terminal OE.sub.0 receives the output signal at W.sub.1 or SR via inverter IN so as to oscillate when output W.sub.1 is logically low that is, when the signals are not stitching signals. AND.sub.7 receives both an input signal to and an output signal from AM the output from AND.sub.5, and provides a signal to shift pulse terminal Cp of shift register SR via OR.sub.8. This construction shifts the data stored in SR until output W.sub.1 goes logically high, i.e. until signals at W.sub.2 and W.sub.3 respond to stitching signals, after the data transfer from ROM to SR is complete and the output of AND.sub.5 becomes logically high. The output of the pulse generator PG is rated to MM.sub.6 via AND.sub.8 (which also receives the output signal from AND.sub.5 at its other input), and causes a shift signal to appear at shift pulse terminal Cp of shift register SR via OR.sub.8 so as to shift the signal within shift register SR each time the sewing machine rotates to saw a stitch. AND.sub.9 receives both the output signal from AND.sub.5 and the signal at W.sub.1 of SR, and when the signal at W.sub.1 is high, AND.sub.9 causes latch circuit L.sub.3 to deliver the signals at W.sub.2 and W.sub.3 SR to DV.

In the embodiment shown in FIG. 3, the output of MM.sub.1 (determined in accordance with operation of pattern selector PS) resets TB via OR.sub.1 and resets shift register SR via OR.sub.7. The rising flank of a first signal from MM.sub.4 provides a shift pulse to SR via OR.sub.8, and simultaneously causes a logically high signal to appear at input terminal V so as to store it in first bit cell and to thereby store, at that 0 address stitching signals at E.sub.2 and E.sub.3 for a first stitch which latter signal appears at input terminals V.sub.2 and V.sub.3. Due to the rising signal of MM.sub.4, the outputs at E.sub.2 and E.sub.3 of ROM become signals for a second stitch, and upon receipt of a subsequent rising signal from MM.sub.4, the signal stored in the first bit cell is shifted to a second bit cell, and the first bit cell corresponding to terminals V.sub.1, V.sub.2 and V.sub.3 of shift register SR stores the first and second stitching signals as a stitching signal for a second stitch. This shifting is repeated in succession, and when the logically high signal and the final stitching signal are stored in the first bit cell, the signal for the first stitch and the first stitching signal are shifted by the stitching number composed of the stitch pattern. Since the step number of the shift register SR is increased higher than this stitching number, these signals do not reach output terminals W.sub.1, W.sub.2 and W.sub.3. When ROM issues the output of the final stitching signal, FF.sub.2, FF.sub.3, TB, MM.sub.3 and MM.sub.4 are reset, the signal at OE.sub.N of ROM becomes low and ROM accordingly, becomes inoperative. The output of AND.sub.5 is then logically high. When a signal for stitching a seam does not reach output terminals W.sub.1, W.sub.2 and W.sub.3, terminal W.sub.1 is low, and AM oscillates. This oscillation delivers shift pulses to shift register SR via AND.sub.7 and OR.sub.8, and shifts the stitching data until output signal at W.sub.1 becomes high, that is, until the initial stitching signal reaches output terminals W.sub.2 and W.sub.3. When the output signal at W.sub.1 becomes high, AM provides a clock pulse to latch circuit L.sub.3 via AND.sub.9, and causes initial stitching signals at W.sub.2 and W.sub.3 to be delivered to DV. When the sewing machine is rotated, pulse generator PG issues a signal for each rotation, and the shift register SR successively shifts the data to advance it to output terminals W.sub.2 and W.sub.3. When the stitching signal ends and output signal at W.sub.1 becomes low again, AM oscillates to shift shift register SR and to provide an initial stitch signal for pattern repetition. Thus, stitch patterns are repeated.

Readout from ExR and from ROM to SR is the same as in FIG. 2, and ROM operation is carried out here in the same fashion as has been described there.

As mentioned above, the present invention enables patterns to be formed by the stitching signals stored in ROM, and also enables patterns stored in ROM, and also enables patterns to be formed by reading magnetic tape and punched cards in reader ExR. Since address data for ROM are based on the output data from the ROM, the elements which control readout of ROM, readout of of ExR, operation of RAM, and the writing-in timing to shift register SR, may be used in common. Accordingly, the circuit structure is relatively simple and exact in operation.

Claims

1. An electronic control system for use in sewing machines which vary needle position and fabric feed in order to stitch a plurality of stitch patterns in accordance with stitch control signals, comprising: a pulse generator issuing pulses in synchronism with rotation of the sewing machine; a first memory storing a plurality of stitch control signals; a user-operable pattern selector for selecting an initial address within the first memory; a plurality of monostable multivibrators which are connected to each other and to the pattern selector in a manner that the monostable multivibrators oscillate when the pattern selector is operated; and a second memory connected to the pulse generator, the first memory and said plurality of monostable multivibrators, the second memory operating in a manner that each time an oscillation of the monostable multivibrators takes place, a stitch control signal is read out of the first memory and temporarily stored in the second memory, and each time the pulse generator generates a pulse, a stitch control signal temporarily stored in the second memory is read out therefrom and used to vary needle position and fabric feed.

2. The electronic control system defined by claim 1, wherein the first memory is a read-only memory with 8 address bits.

3. The electronic control system defined by claim 2, wherein the first memory has 6 first output terminals for readdressing the first memory, wherein the first memory has 5 second output terminals for controlling fabric feed, and wherein the first memory has 5 third output terminals for controlling needle sewing amplitude.

4. The electronic control system defined by claim 1, wherein the pattern selector incudes a plurality of user-operable pattern selecting switches, a 3 bit encoder connected thereto, and a latch circuit connected to the encoder, the pattern selector operating in a manner that when a pattern selecting switch is operated, a 3 bit code is encoded by the encoder and latched into the latch circuit.

5. The electronic control system defined by claim 1, wherein the plurality of monostable multivibrators includes a first monostable multivibrator, a second monostable multivibrator, a third monostable multivibrator and a fourth monostable multivibrator, wherein each of the monostable multivibrators have an input and an output, the output of the first monostable multivibrator being connected to an input of an OR-gate, an output of the OR-gate being connected to the input of the second monostable multivibrator, the output of the second monostable multivibrator being connected to the input of the third monostable multivibrator, the output of the third monostable multivibrator being connected to the input of the fourth monostable multivibrator, the output of the fourth monostable multivibrator being connected to an input of an AND-gate which has an output connected to another input of the OR-gate, the output of the first monostable multivibrator being further connected to the set input of a flipflop which also has an output, the output of the flipflop being connected to another input of the AND-gate, and the output of the third monostable multivibrator being further connected to the second memory to allow a stitch control signal to be stored therein upon oscillation of the monostable multivibrators.

6. The electronic control system defined by claim 3, wherein the second memory has 5 second input terminals connected to the second output terminals of the first memory, wherein the second memory has 5 third input terminals connected to the third output terminals of the first memory, wherein the second memory has 5 second output terminals and 5 third output terminals whereby fabric feed and needle swing amplitude can be controlled by the second memory in an order identical to that order in which signals appear at the second and third output terminals of the first memory, and wherein the control system further includes a pulse motor driving device connected to the second and third output terminals of the second memory.

7. The electronic control system defined by claim 1, wherein the second memory has an enable terminal which is connected to an output of an AND-gate, and which, when in a logically high state, causes the second memory to read out stitch control signals.

8. The electronic control system defined by claim 1, wherein the second memory is an 11 bit shift register with a discriminating input connected to one of said plurality of monostable multivibrators, the discriminating input indicating presence of and lack of presence of stitch control signals at the shift register.

9. The electronic control system defined by claim 8, wherein the electronic control system further includes a pulse motor driving device controlled by the second memory via a latch circuit, and wherein the electronic control system further includes an external reader connected to the second memory for enabling stitch control signals to be introduced from an external source.

10. The electronic control system defined by claim 1, further including a timing buffer connected to the pulse generator and the second memory, the timing buffer cyclicly advancing the stitch control signals in response to receipt of a pulse from the pulse generator, whereby after a stitch pattern is completed the stitch pattern is repeated.

11. The electronic control system defined by claim 8, wherein the pulse generator is connected to the shift register and shifts data therein each time the pulse generator generates a pulse, and wherein the electronic control system further includes an astable multivibrator which is connected to the shift register and oscillates after a stitch pattern is completed, whereby the stitch pattern can be repeated once again.