Patent Application
20070278212
Electronic device 1 has heating structure 10 configured by mounting LED chip 2 on sub-mount 3 on heat releasing structure 20 comprising first metal layer 6 and graphite layer 5. Second metal layer 7 is provided on graphite layer 5. Heating structure 10 and heat releasing structure 20 are brought into junction with second solder layer 4b. That is, sub-mount 3 of heating structure 10 and second metal layer 7 of heat releasing structure 20 are brought into junction with second solder layer 4b.
Heat releasing structure 20 is for diffusing heat from LED chip 2 to the exterior atmosphere and includes first metal layer 6 made of metal with good heat conductivity and graphite layer 5 with good heat conductivity in the plane direction. Graphite layer 5 is provided by being stacked on the plane on the side of first metal layer 6 where LED chip 2 is mounted.
In heating structure 10, LED chip 2 and sub-mount 3 are brought into junction with first solder layer 4a made of AuSn or the like. Heating structure 10 is arranged inside opening 40 formed in insulating layer 32 and wiring layer 31 which are stacked on heat releasing structure 20. Wiring layer 31 and sub-mount 3 are connected by wire 33. Heat releasing structure 20 and heating structure 10 are brought into junction with second solder layer 4b whose melting point is lower than first solder layer 4a. LED chip 2 is coated by resin not illustrated in the drawing.
Next, respective layers in heating structure 10 will be described.
Sub-mount 3 is a pedestal where LED chip 2 is mounted. In order that stress, distortion and the like will not take place due to difference in the heat expansion coefficient, there used as sub-mount 3 is an insulating substrate made of ceramics such as AlN, SiC and the like with good heat conductivity is used as material for sub-mount 3, this material being comparatively similar to the substrate material of LED chip 2 in the heat expansion coefficient.
LED chip 2 is brought into junction on sub-mount 3 with first solder layer 4a. As first solder layer 4a, solder made of AuSn with Au as main material is preferable. In the case of using AuSn as main material, the melting point will be approximately 280° C.
As second solder layer 4b, Sn-based solder whose melting point is lower than first solder layer 4a is preferable as second solder layer 4b.
Next, respective layers of heat releasing structure 20 will be described.
Material, for example, such as copper, aluminum and the like is used for first metal layer 6. Here, the thermal conductivity of copper is 390 (W/m·K) and the heat expansion coefficient thereof is 1.0 to 1.4 (cm2/s). On the other hand, the thermal conductivity of aluminum is 230 (W/m·K) and the heat expansion coefficient thereof is 0.9 (cm2/s).
Graphite layer 5 is a graphite sheet with graphite as the main material and “Super λ GS®: produced by Taica Corporation”, for example, is used. In the case of Super λ GS®, thermal conductivity in the plane direction is 400 (W/m·K) and the heat expansion coefficient thereof is 3.0 to 3.2 (cm2/s).
Second metal layer 7 is intended to reduce thermal resistance between heating structure 10 and heat releasing structure 20 to effectuate heat expansion properties of graphite layer 5 sufficiently. For second metal layer 7, metal film made of metal with good heat conductivity such as copper is preferably used. Even if graphite layer 5 and sub-mount 3 are to be brought into junction by means of a solder layer, wettability for both solders is not good. Therefore it is extremely difficult to bring both into direct junction by soldering. Here in the present embodiment, second metal layer 7 is provided on graphite layer 5. Thereby, wettability for solder is improved. That is, in electronic device 1 of the present embodiment, the presence of second metal layer 7 enables a junction between heating structure 10 and heat releasing structure 20 by using second solder layer 4b.
The thermal conductivity of second metal layer 7 and second solder layer 4b is generally higher than that of heat conductive grease and, therefore, can transfer heat from heating structure 10 to heat releasing structure 20 effectively. In addition, preferably second metal layer 7 is thin film that has been formed as thin as possible to such an extent as to secure workability at the occasion of stacking on to graphite layer 5 and junction to heating structure 10. Moreover, in the case of using material such as copper, that is apt to become oxidized, for second metal layer 7, a rust preventing treatment such as gold plating is preferably implemented in order to maintain heat transfer properties. Here, in the case of using aluminum for second metal layer 7, the heat conductive property is good but the for solder wettability is not good. Therefore, it is necessary to implement plating treatment on the surface so as to improve solder wettability.
Next, a method for manufacturing electronic device 1 will be described schematically.
Electronic device 1 of the present embodiment is manufactured by individually producing heat structure 10 and heat releasing structure 20 in advance, then finally, by joining them.
A method of producing heating structure 10 is as follows. First solder layer 4a made of AuSn is formed on sub-mount 3 beforehand. Subsequently, first solder layer 4a is melted beforehand. In that state, LED chip 2 is placed on first solder layer 4a. First solder layer 4a is cooled and solidified. Thereby LED chip 2 is mounted on sub-mount 3 to complete heating structure 10.
A method of producing heat releasing structure 20 is as follows.
At first, graphite layer 5 is stacked onto first metal layer 6.
Subsequently, second metal layer 7 is stacked onto a plane of graphite layer 5 on the opposite side to the plane where first metal layer 6 is stacked to complete heat releasing structure 20.
Next, insulating layer 32 and wiring layer 31 where opening 40 is formed are sequentially stacked onto second metal layer 7 of heat releasing structure 20 that includes second metal layer 7.
Next, second solder layer 4b made of Sn as the main material is formed on second metal layer 7 of opening 40. Since second metal layer 7 has good wettability with solder, second solder layer 4b is formed on second metal layer 7 in a good state.
Heating structure 10 is disposed on second solder layer 4b which has been formed as described above so that sub-mount 3 faces second solder layer 4b. Then heat is applied until the melting point of second solder layer 4b is reached. Here, since the melting point of first solder layer 4a is higher than the melting point of second solder layer 4b, no melting will take place when heat is applied.
Incidentally, the melting point of second metal layer 4b will not be limited a melting point lower than first solder layer 4a but any of the layers having the same melting point can be used. Even if the solder with the same melting point is adopted, first solder layer 4a will not be melted by the relevant application of heat. The reason thereof is as follows.
A gold pattern (not illustrated in the drawing) is formed on sub-mount 3. Heat for melting second solder layer 4b is transferred through sub-mount 3 to melt that gold pattern. When the gold pattern melts, it melts into first solder layer 4a. Thereby the gold content of first solder layer 4a will increase. Increase in the gold content will raise the melting point of first solder layer 4a. Thereby, the melting point of first solder layer 4a will become higher than that of second solder layer 4b and, therefore, will not melt when heat is applied to melt second solder layer 4b.
Lastly, sub-mount 3 and wiring layer 31 are brought into connection with wire 33 for wiring to complete electronic device 1.
Next, a schematic route for the transfer of heat generated in LED chip 2 in electronic device 1 of the present embodiment will be described.
Heat generated by operation of LED chip 2 is conducted at first through first solder layer 4a and then transferred to sub-mount 3.
The heat transferred to sub-mount 3 is conducted through second solder layer 4b, transferred to second metal layer 7 and then transferred to graphite layer 5. Thus, heat transfer from sub-mount 3 to graphite layer 5 is carried out by conduction through second solder layer 4b and second metal layer 7. In the case of the present embodiment, second metal layer 7 is provided on graphite layer 5. Thereby, a junction between heating structure 10 and heat releasing structure 20 using second solder layer 4b and having good heat conductivity can be created. Therefore, that enables thermal resistance between heating structure 10 and heat releasing structure 20 to be reduced as much as possible. Consequently, heat generated in LED chip 2 can be effectively transferred to graphite layer 5.
Heat transferred from LED chip 2 to graphite layer 5 in the stacking direction is conducted in the plane direction with graphite layer 5. Heat widely diffused in the plane direction with graphite layer 5 is transferred to first metal layer 6 and is efficiently diffused from the surface of first metal layer 6 into the air. Here, in the case where electronic device 1 is installed in another apparatus, the relevant apparatus is caused to function as a heat releasing member to enable the heat radiation area to become widened. For example, consider the case electronic device 1 is attached to the main body of a luminaire comprising a metal enclosure. In the case in which the side of first metal layer 6 is attached to the main body of the luminaire, heat will be transferred from first metal layer 6 to the main body of the luminaire and radiated from the surface of the main body of the luminaire into the air. Here, there likewise is the case where first metal layer 6 is attached to a radiating fin or to a heating pipe in order to enhance heat radiation efficiency.
Graphite layer 5 is caused to intervene between sub-mount 3 and first metal layer 6 to enhance the heat conductive property in the plane direction. Thereby, this will allow the effective heat radiation area of first metal layer 6 to become widened and therefore effective cooling of heating elements such as an LED and the like will become possible. However, because significant thermal resistance was left to intervene between heating structure 10 and heat releasing structure 20, as in the above described conventional example and the like, it could not take adequate advantage of the properties of graphite.
In contrast, in the patent application of the present invention, second metal layer 7, that has high wettability with solder, is formed on graphite layer 5. Thereby, junction between heating structure 10 and heat releasing structure 20 is realized with second solder layer 4b. Then, it becomes possible to maintain low thermal resistance between heating structure 10 and heat releasing structure 20. In addition, by adopting a metal film with high thermal conductivity for second metal layer 7, thermal resistance is kept lower.
Here, another configuration of the-present embodiment is illustrated in
In the configuration illustrated in
In addition, still another configuration of the present embodiment is illustrated in
Each electronic device 1 in
As described above, according to the present embodiment, it is possible to take adequate advantage of high heat diffusion property of graphite in the plane direction. Therefore, desired cooling properties can be implemented in an electronic device.
A schematic section illustrating configuration of electronic device 51 of the present embodiment is illustrated in
As LED chip 52 of electronic device 51 of the present embodiment is configured by P pole 52a and N pole 52b provided on the upper plane and is mounted directly on second metal layer 7 without intervention of a sub-mount. Since the other basal configuration is the same as in the first embodiment described above, detailed description will be omitted.
On the lower plane of LED chip 52 where P pole 52a and N pole 52b are not provided, a plating layer (for example, gold plating) is formed so that there will be good solder wettability. LED chip 52 causes plane to face second metal layer 7 and is brought into junction by means of solder layer 4c. P pole 52a is electrically connected to first wiring layer 31a by first wiring wire 33a. In addition, N pole 52b is electrically connected to second wiring layer 31b by second wiring wire 33b.
The first embodiment was exemplified by a configuration suitable for mounted LED chip 2 comprising P pole (or N pole) on the upper plane and N pole (or P pole) on the lower plane. In the case of LED chip 2 where the P and N poles are arranged on the upper and the lower planes, it is necessary to insulate second metal layer 7 on heat releasing structure 20. Therefore, LED chip 2 which is mounted on sub-mount 3, is mounted onto second metal layer 7. Therefore, heat generated by LED chip 2 will be transferred to second metal layer 7 via first solder layer 4a, sub-mount 3 and second solder layer 4b.
In contrast, in the case of the present embodiment, as described above, P pole 52a and N pole 52b in LED chip 52 are formed on the upper plane of LED chip 52 and are not formed on the lower planer. Therefore, insulation by the sub-mount is not required. Also in the first embodiment, a sufficiently good heat radiation property is attainable. However, in the case of the present embodiment, LED chip 52 is mounted directly onto second metal layer 7 so that the sub-mount and first solder layer 4a can be omitted. Therefore, in the case of the present embodiment, thermal resistance from LED chip 52 to graphite layer 5 can be reduced. Therefore, it is possible to take sufficient advantage of the high heat diffusion property of graphite in the plane direction and, at the same time, better heat radiation can be achieved.
In addition, in the case of the first embodiment, a step for manufacturing heating structure 10 comprising LED chip 2 and sub-mount 3 that is brought into junction with first solder layer 4a is required. That is, steps for providing sub-mount 3 with first solder layer 4a, bringing first solder layer 4a into the melted state, integrating sub-mount 3 and LED chip 52 by cooling and solidifying first solder layer 4a after mounting LED chip 52 onto first solder layer 4a in the melted state are required.
In contrast, LED chip 52 of the present embodiment does not require the sub-mount and the first solder layer. Therefore, production of a heating structure is not required. Thereby, manufacturing steps can be simplified and also the number of parts in an apparatus can be reduced.
In addition, in the case of a heating structure comprising a sub-mount, it is necessary to extract the wiring wire from the sub-mount. Therefore, in order to secure the region for connection of the wiring wire, it is necessary to make the area of the sub-mount larger than the area of the LED chip. This causes the size of the apparatus to become larger. it is necessary to make the area of the sub-mount larger than the area of the LED chip, resulting in a larger size by that portion.
In contrast, chip 52 of the present embodiment requires the mounting area only for the portion of the LED chip. Therefore, it is possible to make an apparatus smaller.
As described above, according to the present embodiment, it is possible to take sufficient advantage of the high heat diffusion property of graphite in the plan direction. Therefore, desired cooling properties will become attainable in an electronic device.
Here, the configuration of the present embodiment is preferably configured by insulating the P pole and the N pole to function as the wiring extracting portion on the plane of the heating structure except for the plane where the LED chip contacts second metal layer 7. For example, in addition to the case where the P and N poles are present on the upper plane, the P and N poles can be formed on the side plane.
In addition, the present embodiment is exemplified by bringing the LED chip comprising a gold plating layer formed on the lower plane into junction with second metal layer 7 by means of solder layer 4c. However, in the case where no gold plating pattern is formed, a junction can be realized by using an adhesive.
For the present embodiment, an electronic device comprises a graphite layer and a second metal layer to realize high heat conductivity. A method for manufacturing the electronic device comprising, in particular, a connector will be described. Here, in the following description, electronic device 1 illustrated in the first embodiment will be used as an example.
In a case in which the idea is to establish an electrical connection between another apparatus and electronic device 1, using an electric-wire to link wiring layer 31 of electric device 1 to the other apparatus can be considered. In that case, the electric wire will be soldered to wiring layer 31. However, as described above, electronic device 1 is highly heat conductive. Therefore, the heat of the soldering iron will be absorbed by electronic device 1 and there will be a failure in producing an adequate alloy layer, resulting in mechanically incomplete soldering. That is, a method of carrying out soldering onto wiring layer 31 will become substantially difficult.
Therefore, as illustrated in
Therefore, in the case of mounting a connector onto an electronic device of the present invention comprising the graphite layer and the second metal layer, the connector is preferably mounted by the following method.
At first, first solder layer 4a is formed on sub-mount 3. In addition, third solder layer 4e is formed on wiring layer 31 beforehand. Thus, after first solder layer 4a and third solder layer 4e are formed in advance, LED chip 2 is placed on first solder layer 4a and connector 34 is placed on third solder layer 4e. Subsequently, first solder layer 4a and third solder layer 4e are heated simultaneously. Thereby, LED chip 2 is soldered onto sub-mount 3 using first solder layer 4a. Concurrently, connector 34 is soldered onto wiring layer 31 using third solder layer 4e. Thus, simultaneous soldering LED chip 2 and connector 34 can prevent LED chip 2 that have been disposed in advance, from being displaced due to soldering to connector 34.
In addition, the following method can be adopted.
At first, connector 34 is soldered to wiring layer 31 in advance using third solder layer 4e to intervene. Next, LED chip 2 is placed on first solder layer 4a. In that state, heat is applied from the side of the rear plane (the plane where graphite layer 5 is not formed) of first metal layer 6. Then, heat is transferred to first solder layer 4a via graphite layer 5, second metal layer 7, second solder layer 4b and sub-mount 3 to melt first solder layer 4a so that LED chip 2 and sub-mount 3 are brought into junction. The heat that is used to heat first metal layer 6 from the rear plane side will be naturally transferred to third solder layer 4e as well. However, insulating layer 32 whose function is to provide significant thermal resistance is present between first metal layer 6 and third solder layer 4e. Therefore the time required for third solder layer 4e to begin to melt will become longer than the time required for first solder layer 4a to begin to melt and a time difference will occur between the times. That is, when using that time difference, the rear plane of first metal layer 6 is heated to melt first solder layer 4a and heating is stopped before third solder layer 4e starts to melt. Thereby, without melting third solder layer 4e which brings connector 34 into junction, LED chip 2 can be mounted.
In addition, the metal layer in each of the above described embodiments can be either a thin plate or a plating layer. In particular, in the case of a plating layer, the nickel layer can be formed beforehand so that a gold plating layer is formed thereon.
While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-154904 | Jun 2006 | JP | national |
| 2006-169163 | Jun 2006 | JP | national |
| 2006-260343 | Sep 2006 | JP | national |
