Patent Application
20150348487
This relates generally to electronic devices and, more particularly, to electronic devices with displays.
Electronic devices often include displays. For example, cellular telephones, computers, and televisions have displays.
Displays such as liquid crystal displays have arrays of display pixels. Display driver circuitry is used to display images on a display by loading image data into an array of display pixels. The display driver circuitry includes column drivers for supplying data to columns of the display pixels and includes gate driver circuitry for addressing rows of the display pixels. When displaying a frame of data on the display, the gate driver circuitry successively asserts a gate signal in each row of the array to load data into the display pixels.
There are challenges involved in preventing damage to a display when powering down the display. In displays that contain somewhat leaky thin-film transistors, display pixels naturally discharge when the display is powered down. In other displays, however, such as displays based on oxide semiconductor thin-film transistors, the amount of transistor leakage that is exhibited by thin-film transistors in the display pixels is reduced. If care is not taken, this may lead to undesired persistent pixel voltages after powering down the display. For example, display pixel signals of several volts or more may remain on the display pixels once the display is no longer being refreshed during normal operation. Sustained display pixel voltages such as these may cause image retention or permanent damage to the display. In some cases, the most recently displayed image on a display may become effectively burned into the display during power-down and may be subsequently visible for many hours of subsequent operation once the display has been powered-up and used again.
It would therefore be desirable to be able to provide improved ways to power down display pixels in a display.
A display may have an array of display pixels. Display driver circuitry may be used to load data into the display pixels. The display driver circuitry may include column driver circuitry for supplying data signals to columns of the display pixels. The display driver circuitry may also include gate driver circuitry for supplying gate signals that are used in sequentially addressing rows of the display pixels.
The display may include a regulator that produces a power supply voltage for the display driver circuitry. A monitor circuit may measure the power supply voltage. During a power-down event, the power supply voltage will drop. The monitor circuit may assert a mode selection signal in response to detection of a drop in the power supply voltage below a predetermined threshold.
The display driver circuitry may contain mode selection circuitry that is controlled by the mode selection signal. During normal operation, the mode selection signal is deasserted and the display driver circuitry loads image data for the display in to the display pixels. During power-down operations, when the mode selection signal is asserted, the mode selection circuitry and other circuitry in the display driver circuitry may load safe data into the display pixels to avoid damaging the display while the display is powered off.
Electronic devices may be provided with displays. Display driver circuitry such as column driver circuitry and gate driver circuitry may be used in displaying images on an array of display pixels in a display. During an intentional power-down event or when powering down a display due to an unexpected power supply disruption, permanent damage to the display may be avoided by ensuring that each display pixel is driven to a safe voltage. For example, in a display in which display pixels are driven between 7.5 volts and 15 volts (during frames of one polarity) and between 0 and 7.5 volts (during frames of an alternate polarity) on one electrode, and driven at a constant 7.5 volts on the other pixel electrode, the power-down operations are performed so that the voltage across the pixel between the two electrodes is maintained at or near 0 volts during the power down, rather than allowing the unmodified data values for the display pixels to be driven during the power down. The data values during power down on one electrode might otherwise cause relatively high voltages such as 7.5 volts relative to the second electrode to occur across the pixel during power down that could potentially then damage the display if left in place during and following the power down. Display driver circuitry may instead therefore be used to drive safe data (i.e., signals at a desired safe voltage that keeps the pixel voltage itself low) into the display pixels when powering down the display.
Illustrative electronic devices of the types that may be provided with displays having display driver circuitry that can load safe data during power-down operations are shown in
Electronic device 10 of
In the example of
Display 14 may be a liquid crystal display, an organic light-emitting diode display, a plasma display, an electrophoretic display, an electrowetting display, a display using other types of display technology, or a display that includes display structures formed using more than one of these display technologies. A cross-sectional side view of an illustrative configuration for display 14 of device 10 (e.g., a liquid crystal display for the devices of
Display layers 46 may be mounted in chassis structures such as a plastic chassis structure and/or a metal chassis structure to form a display module for mounting in housing 12 or display layers 46 may be mounted directly in housing 12 (e.g., by stacking display layers 46 into a recessed portion in housing 12).
Display layers 46 may include a liquid crystal layer such a liquid crystal layer 52. Liquid crystal layer 52 may be sandwiched between display layers such as display layers 58 and 56. Layers 56 and 58 may be interposed between lower (innermost) polarizer layer 60 and upper (outermost) polarizer layer 54.
Layers 58 and 56 may be formed from transparent substrate layers such as clear layers of glass or plastic. Layers 56 and 58 may be layers such as a thin-film transistor layer and/or a color filter layer. Conductive traces, color filter elements, transistors, and other circuits and structures may be formed on the substrates of layers 58 and 56 (e.g., to form a thin-film transistor layer and/or a color filter layer). Touch sensor electrodes may also be incorporated into layers such as layers 58 and 56 and/or touch sensor electrodes may be formed on other substrates.
With one illustrative configuration, layer 58 may be a thin-film transistor layer that includes an array of thin-film transistors and associated electrodes (display pixel electrodes) for applying electric fields to liquid crystal layer 52 and thereby displaying images on display 14. Layer 56 may be a color filter layer that includes an array of color filter elements for providing display 14 with the ability to display color images. If desired, layer 58 may be a color filter layer and layer 56 may be a thin-film transistor layer.
During operation of display 14 in device 10, control circuitry (e.g., one or more integrated circuits on a printed circuit) may be used to generate information to be displayed on display 14 (e.g., display data). The information to be displayed may be conveyed to display driver circuitry 62 using signal path 64. Display driver circuitry 62 (which may sometimes be referred to as a display driver or timing controller and display driver circuitry) may include one or more integrated circuits such as column driver integrated circuits for driving data signals onto corresponding data lines in display 14, gate driver circuitry for supplying gate signals to gate lines in display 14, and a timing controller (TCON) integrated circuit that supplies image data to the column drivers and gate driver controls signals to the gate driver circuitry.
Backlight structures 42 may include a light guide plate such as light guide plate 78. Light guide plate 78 may be formed from a transparent material such as clear glass or plastic. During operation of backlight structures 42, a light source such as light source 72 may generate light 74. Light source 72 may be, for example, an array of light-emitting diodes.
Light 74 from light source 72 may be coupled into edge surface 76 of light guide plate 78 and may be distributed in dimensions X and Y throughout light guide plate 78 due to the principal of total internal reflection. Light guide plate 78 may include light-scattering features such as pits or bumps. The light-scattering features may be located on an upper surface and/or on an opposing lower surface of light guide plate 78.
Light 74 that scatters upwards in direction Z from light guide plate 78 may serve as backlight 44 for display 14. Light 74 that scatters downwards may be reflected back in the upwards direction by reflector 80. Reflector 80 may be formed from a reflective material such as a layer of white plastic or other shiny materials.
To enhance backlight performance for backlight structures 42, backlight structures 42 may include optical films 70. Optical films 70 may include diffuser layers for helping to homogenize backlight 44 and thereby reduce hotspots, compensation films for enhancing off-axis viewing, and brightness enhancement films (also sometimes referred to as turning films) for collimating backlight 44. Optical films 70 may overlap the other structures in backlight unit 42 such as light guide plate 78 and reflector 80. For example, if light guide plate 78 has a rectangular footprint in the X-Y plane of
Display 14 may have an array of display pixels (e.g., a rectangular array having rows and columns) for displaying images to a viewer. Vertical signal lines called data lines may be used to carry display data to respective columns of display pixels. Horizontal signal lines called gate lines may be used to carry gate line signals (sometimes referred to as gate control signals or gate signals) to respective rows of display pixels.
A circuit diagram of an illustrative display pixel is shown in
Transistor 102 of display pixel 100 is used to control the loading of data signal D into storage capacitor Cst. When the gate signal on line G is asserted, transistor 102 is turned on and data line D supplies a desired value of voltage Vp to capacitor Cst. This voltage is applied to electrode 104 and serves to establish a desired electric field across liquid crystal layer 52.
The presence of persistent direct current (DC) voltages Vp on capacitor Cst (and therefore across liquid crystal layer 52) have the potential to permanently damage display 14 (e.g., by creating permanent images on the display corresponding to the last-loaded data frame). Transistor 102 may be a thin-film transistor formed from a semiconductor such as silicon (e.g., polysilicon) or a semiconducting oxide such as indium gallium zinc oxide. In some situations (e.g., polysilicon transistors), there can be non-negligible amounts of leakage current through transistor 102 when display 14 is powered down. This leakage current can effectively discharge any residual voltage Vp-Vcom across the pixel or capacitor Cst, thereby preventing damage to display 14 on power down events. In other situations (e.g., semiconducting oxide transistors), the leakage current through transistor 102 may be relatively low. In this type of scenario, it can be beneficial to actively drive safe data (e.g., data at a known safe voltage that will not damage display 14) into the display pixel array. For example, with a Vcom of 7.5 volts, a safe voltage of 7.5 volts can be actively loaded into each capacitor Cst in response to detection of an intentional or accidental power-down event so that the pixel voltage is zero, or alternatively Vcom can be set to zero and a safe voltage of zero loaded into each capacitor.
In intentional power-down events, there may be a substantial amount of time available to load safe data into the display pixels of display 14. In accidental power-down events, which may arise, for example, if line power or battery power to device 10 is unexpectedly interrupted, less time may be available. The type of power-down process that is used for device 10 may be configured to accommodate expected available power-down times. Rapid power-down protection schemes (e.g., schemes that accommodate power down events of a few ms or less or other rapid power down events) may be implemented by loading safe data into multiple rows of the display pixels in parallel. The most rapid types of power-down schemes may load numerous rows of display pixels with safe data at the same time. Less rapid types of power-down schemes (which may be used, for example, to avoid overly-large current surges in the display driver circuitry) may involve the loading of fewer rows of display pixels at a time (e.g., loading only two rows or one row with safe data at a time).
Each gate driver integrated circuit 116 may be used in supplying gate signals to a set of corresponding gate lines. There may be two or more, three or more, four or more, eight or more, or other suitable number of gate driver integrated circuits on each edge of display 14. Configurations in which gate driver circuitry is implemented using only gate driver integrated circuits 116 on the left or right edge of display 14 and/or arrangements in which gate driver circuitry is formed using thin-film transistors may also be used, if desired.
Timing controller circuit 108 may receive image data to be displayed on display 14 using path 110, which may be coupled to control circuitry on a main logic board or other circuitry in device 10. The image data may be processed by timing controller circuit 108 and supplied to column driver circuitry 112 so that column driver circuitry 112 can drive corresponding data signals onto data lines D. Timing controller circuit 108 may also supply gate driver control signals to gate driver circuitry 116. For example, timing controller circuit 108 may use a path such as path 122 to supply a gate start pulse signal GSP to circuits 116 and may use a path such as path 124 to supply control signals such as gate shift clock signal GSC and gate output enable signal GOE to circuits 116. Other sets of gate driver control signals may be used if desired (e.g., a control scheme involving multiple clocks may be used, etc.).
Gate driver circuits 116 may contain shift register circuitry formed from a chain of coupled register circuits 120. Mode selection circuits 118 may be used to place the gate driver circuitry of display 14 in one of two states. During normal operation, mode selection circuits 118 are placed in a normal state to apply gate control signals to shift register circuitry 120 in a way that loads a frame of image data sequentially into each row of display pixels 100 in display 14. During power-down operation, mode selection circuits 118 are placed in a power-down state that allows safe data to be loaded into multiple rows of display pixels 100 in parallel, thereby speeding up the process of safe data loading. This helps ensure that display pixels 100 can be satisfactorily loaded with safe data while sufficient power remains to operate the display driver circuitry.
During normal operations, the loading of each frame of image data may be initiated by assertion of signal GSP at the beginning of the frame. Signal GSC may be a square wave clock signal. During the loading of a frame of data, the gate signal on each gate line G in display 14 is asserted in sequence at the clock rate established by signal GSC. GSP paths between the last register circuit 120 in the shift register of each display driver integrated circuit 116 and the first register circuit 120 in the shift register of the next display driver integrated circuit 116 ensure that the asserted gate signal can propagate through each of the rows of the display in sequence (i.e., so that the gate signal in each of the rows of display 14 will be asserted one at a time in order, starting with the first row of the display and ending with the last row of the display). During normal operation, gate output enable signals GOE are used to protect the thin-film transistors 102 in display 14 from being driven during clock transitions.
During power-down operations, mode selection circuitry 118 is placed in a power-down state. In the power-down state, safe data is loaded into display pixels 100 in a desired pattern, balancing loading time versus current draw. As an example, multiple rows of display pixels (e.g., two or more rows, four or more rows, eight or more rows, etc.) may be loaded with safe data in parallel.
Control circuitry such as a voltage monitor circuit may be used to generate a control signal (which may, for example, be called mode selection signal ALL_C) that is used to control mode selection circuitry 118 upon power-down.
In intentional power-down scenarios, TCON 108 deasserts an enable signal EN to disable regulator 134 (
An illustrative mode selection circuit 118 (i.e., a mode selection circuit that may be provided in each of the gate driver integrated circuits 116) is shown in
As shown in
The gate output signal GOE that is supplied to each mode select circuit 118 is output as corresponding internal gate output enable signal INT_GOE, which is applied to the shift register circuitry.
The state of mode selection signal ALL_C from monitor 130 determines the behavior of multiplexing circuitry 160. During normal operation, signal ALL_C is deasserted (e.g., ALL_C is high), so input signal GSP is provided to the output of mode selection circuit 118 as INT_GSP. This signal may propagate downward through the shift registers of display 14 to control which row of display pixels 100 is currently receiving an asserted gate line signal (while all other rows are receiving deasserted gate line signals). During normal operation, the gate output enable signal (i.e., INT_GOE) is supplied to the shift register circuitry 120 to help protect the thin-film transistors in the display pixels from being driven during transitions of clock GSC.
During power-down operations, signal ALL_C is asserted (e.g., ALL_C is taken low). In this situation, signal GSP is held high at Vcc and signal GOE is held low.
Timing diagrams that illustrate the operation of the display driver circuitry of display 14 during normal operation and during power-down operations are shown in
In the graphs of
During normal operation, signal GSP is asserted (e.g., taken high) at the start of the loading of each new frame of image data into the array of display pixels in display 14. Clock GSC and gate output enable signals GOE are used by shift register circuitry 120 to create a sequence of gate signals on the gate lines. As shown in
During a power-down event, power supply voltage Vcc drops below its normal level. At time t2, monitor 130 detects that Vcc has dropped below a predetermined threshold. In response, monitor 130 asserts ALL_C (i.e., ALL_C is taken low, as shown in
Safe data can be loaded into one or more rows of display pixels at a time, but preferably fewer than all of the rows of data are loaded at once. By ensuring that only a subset of the rows of display 14 are loaded during any given clock cycle, excessively large current values will not be drawn by the display driver circuitry during power-down events.
There may be gate driver circuits 116 on both ends of each gate line. In this type of double-ended arrangement, there is a possibility of undesirable contention between the gate drivers on opposing ends of a gate line during power down operations. This situation can be avoided by ensuring that both the left-hand gate driver integrated circuits and the right-hand gate driver integrated circuits of display 14 are driven by a common clock signal GSC during power down (i.e., contention can be avoided by driving the left and right gate driver circuits synchronously during power down operations).
Illustrative pattern A of
Illustrative pattern B of
Pattern C of
If desired, each display driver integrated circuit may be configured to load safe data into the display two rows at a time (i.e., multiple rows may be loaded in parallel using a common gate driver integrated circuit). As shown by illustrative power-down row pattern D of
The foregoing is merely illustrative and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented individually or in any combination.
This application claims the benefit of provisional patent application No. 62/006,667 filed Jun. 2, 2014, which is hereby incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62006667 | Jun 2014 | US |
