Patent Application
20250165685
This application claims benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0161436, filed on Nov. 20, 2023, and Korean Patent Application No. 10-2024-0033324, filed on Mar. 8, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.
The present disclosure relates generally to optimization of semiconductor characteristics, and more particularly, to an electronic device and an operating method thereof, which optimize semiconductor characteristics based on a Plackett-Burman design and genetic algorithm.
With the advent of high-speed systems and the diversification of applications such as, but not limited to, mobile device applications, server applications, autonomous driving, or the like, semiconductor characteristics-related issues may continue to arise, and thus, a need to secure signal integrity may be increasing.
In a development stage, operation stability of signals may be performed. However, it may be difficult to accomplish optimization at a relatively high level within a limited time period due to an increase in evaluation cases. Therefore, the importance of experimental planning for evaluation time and selection of a test case may be increasing, and as such, it may be necessary to efficiently secure semiconductor characteristic optimization conditions by introducing an evaluation condition optimization algorithm.
One or more example embodiments of the present disclosure provide an electronic device and an operating method thereof, which optimize semiconductor characteristics based on a Plackett-Burman design (PBD) and a genetic algorithm.
According to an aspect of the present disclosure, an electronic device includes a Plackett-Burman design (PBD) execution circuit, a genetic algorithm (GA) execution circuit, and a control circuit. The PBD execution circuit is configured to generate an initial design of experiment (DOE) set including a plurality of initial cases regarding semiconductor characteristics of a memory device included in an external device. The GA execution circuit is configured to convert a previous generation DOE set to a next generation DOE set based on a genetic algorithm. The control circuit is configured to transmit the initial DOE set to the external device, receive, from the external device, an initial characteristic evaluation performed based on the initial DOE set, generate a starting DOE set based on the initial characteristic evaluation, and control a genetic algorithm to be performed with an experimental result of the starting DOE set as an input. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values influencing the semiconductor characteristics.
According to an aspect of the present disclosure, an operating method of an electronic device includes generating an initial DOE set including a plurality of initial cases regarding semiconductor characteristics of a memory device of an external device, transmitting, to the external device, the initial DOE set, receiving, from the external device, an initial characteristic evaluation performed based on the initial DOE set, generating a starting DOE set based on the initial characteristic evaluation, and generating an output DOE set by performing a genetic algorithm with an experimental result of the starting DOE set as an input. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values influencing the semiconductor characteristics.
According to an aspect of the present disclosure, a system includes a first electronic device and a second electronic device. The first electronic device is configured to generate an initial DOE set including a plurality of initial cases regarding semiconductor characteristics of a memory device of a second electronic device, transmit, to the second electronic device, the initial DOE set, receive, from the second electronic device, an initial characteristic evaluation corresponding to the initial DOE set, generate a starting DOE set based on the initial characteristic evaluation, and perform a genetic algorithm with an experimental result of the starting DOE set as an input. The second electronic device is configured to receive, from the first electronic device, the initial DOE set including the plurality of initial cases, perform semiconductor characteristic evaluation by setting the memory device based on respective setting values of the plurality of initial cases, and transmit, to the first electronic device, the initial characteristic evaluation corresponding to a result of the performed semiconductor characteristic evaluation. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values influencing the semiconductor characteristics. The first electronic device is further configured to perform linear analysis for each of the plurality of setting values based on the initial characteristic evaluation, determine the plurality of setting values based on a result of the linear analysis, generate an optimal case including the plurality of determined setting values, and generate the starting DOE set by merging the plurality of initial cases, the optimal case, and a base case in which the plurality of setting values are set to off.
Additional aspects may be set forth in part in the description which follows and, in part, may be apparent from the description, and/or may be learned by practice of the presented embodiments.
The above and other aspects, features, and advantages of certain embodiments of the present disclosure may be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of embodiments of the present disclosure defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are considered to be exemplary only. Therefore, those of ordinary skill in the art may recognize that various changes and modifications of the embodiments described herein may be made without departing from the scope and spirit of the disclosure. In addition, descriptions of well-known functions and structures are omitted for clarity and conciseness.
With regard to the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It is to be understood that a singular form of a noun corresponding to an item may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, each of such phrases as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C,” may include any one of, or all possible combinations of the items enumerated together in a corresponding one of the phrases. As used herein, such terms as “1st” and “2nd,” or “first” and “second” may be used to simply distinguish a corresponding component from another, and does not limit the components in other aspect (e.g., importance or order). It is to be understood that if an element (e.g., a first element) is referred to, with or without the term “operatively” or “communicatively”, as “coupled with,” “coupled to,” “connected with,” or “connected to” another element (e.g., a second element), it means that the element may be coupled with the other element directly (e.g., wired), wirelessly, or via a third element.
The terms “first,” “second,” third” may be used to describe various elements but the elements are not limited by the terms and a “first element” may be referred to as a “second element”. Alternatively or additionally, the terms “first”, “second”, “third”, and the like may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms “first”, “second”, “third”, and the like may not necessarily involve an order or a numerical meaning of any form.
Reference throughout the present disclosure to “one embodiment,” “an embodiment,” “an example embodiment,” or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases “in one embodiment”, “in an embodiment,” “in an example embodiment,” and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment. The embodiments described herein are example embodiments, and thus, the disclosure is not limited thereto and may be realized in various other forms.
It is to be understood that the specific order or hierarchy of blocks in the processes/flowcharts disclosed are an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes/flowcharts may be rearranged. Further, some blocks may be combined or omitted. The accompanying claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The embodiments herein may be described and illustrated in terms of blocks, as shown in the drawings, which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, or by names such as device, logic, circuit, controller, counter, comparator, generator, converter, or the like, may be physically implemented by analog and/or digital circuits including one or more of a logic gate, an integrated circuit, a microprocessor, a microcontroller, a memory circuit, a passive electronic component, an active electronic component, an optical component, and the like.
In the present disclosure, the articles “a” and “an” are intended to include one or more items, and may be used interchangeably with “one or more.” Where only one item is intended, the term “one” or similar language is used. For example, the term “a processor” may refer to either a single processor or multiple processors. When a processor is described as carrying out an operation and the processor is referred to perform an additional operation, the multiple operations may be executed by either a single processor or any one or a combination of multiple processors.
Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.
Referring to
The first electronic device 110, according to an embodiment, may optimize semiconductor characteristics of the second electronic device 120. The first electronic device 110 may be referred to using various terms such as, but not limited to, a test device, an optimization device, or the like. For example, the first electronic device 110 may provide a design of experiment (DOE) set to the second electronic device 120. The DOE set may be and/or may include data for evaluating semiconductor characteristics of a memory (e.g., at least one of a volatile memory or a nonvolatile memory) included in the second electronic device 120. For example, the DOE set may include a plurality of cases. Each of the plurality of cases may include a plurality of test mode register setting (TMRS) values for evaluating semiconductor characteristics of a memory included in the second electronic device 120. The TMRS value may include factors that may influence the semiconductor characteristics (e.g., input/output (I/O) margin in the case of a dynamic random-access memory (DRAM), eye size of an eye diagram, or the like) of the memory of the second electronic device 120 depending on whether the TMRS value is set to ON (e.g., POSITIVE, “+”, high, “1”, or the like) or the TMRS value is set to OFF (e.g., NEGATIVE, “−”, low, “0”, or the like).
The second electronic device 120, according to an embodiment, may evaluate semiconductor characteristics and provide a characteristic evaluation result to the first electronic device 110. The second electronic device 120 may receive, from the first electronic device 110, the DOE set and may provide, to the first electronic device 110, a characteristic evaluation result for each of the plurality of cases included in the DOE set. For example, the DOE set may include eight (8) cases, and each of the eight (8) cases may include a combination of seven (7) TMRS values. The second electronic device 120 may set a memory of the second electronic device 120 according to a TMRS value corresponding to each of eight (8) cases and evaluate semiconductor characteristics. For example, the second electronic device 120 may set a memory according to a combination of TMRS values of each of the eight (8) cases and evaluate an I/O margin and/or an eye size of an eye diagram. For example, when the DOE set includes eight (8) cases, the second electronic device 120 may perform evaluation of semiconductor characteristics eight (8) times and provide the first electronic device 110 with the eight (8) results of the characteristic evaluations.
The first electronic device 110, according to an embodiment, may perform a genetic algorithm and/or identify an optimal case based on the characteristic evaluation result received from the second electronic device 120. For example, when the characteristic evaluation result satisfies the termination condition (e.g., the I/O margin exceeds the threshold margin and/or the child size exceeds the threshold size) of the genetic algorithm, generation repetition based on the genetic algorithm may be stopped, and, one case with a preferred (e.g., highest) evaluation result from among the DOE sets provided to the second electronic device 120 may be identified as an optimal case and provided to the second electronic device 120. The second electronic device 120 may provide optimal performance by receiving the optimal case and setting a memory device according to a combination of TMRS values included in the optimal case. As another example, when the characteristic evaluation result does not satisfy the termination condition of the genetic algorithm, the first electronic device 110 may generate and provide, to the second electronic device 120, a new DOE set (e.g., a child generation) by performing generation repetition of the DOE set (e.g., a parent generation). The first electronic device 110 and the second electronic device 120 are further described with reference to
Referring to
The control circuit 210 may control the overall operation of the first electronic device 110. For example, the control circuit 210 may generate an initial PBD DOE set by providing a control signal to the PBD execution circuit 220. The initial PBD DOE set may be a DOE set for identifying initial characteristics of a memory included in the second electronic device 120. As another example, the control circuit 210 may perform generation repetition of the DOE set by providing a control signal to the GA execution circuit 230.
According to an embodiment, the control circuit 210 may determine whether to continue to perform generation repetition of the DOE set based on the characteristic evaluation result received from the second electronic device 120. For example, the control circuit 210 may determine whether the characteristic evaluation result received from the second electronic device 120 exceeds the threshold value and satisfies the termination condition of the genetic algorithm. When the termination condition of the genetic algorithm is satisfied, the control circuit 210 may provide a control signal to the GA execution circuit 230 to stop generation repetition based on the genetic algorithm, and may determine, as an optimal case, a case having a preferred (e.g., highest) characteristic evaluation result among the finally generated DOE set and provide the case to the second electronic device 120. When the termination condition of the genetic algorithm is not satisfied, the control circuit 210 may provide a control signal to the GA execution circuit 230 to instruct the GA execution circuit 230 to continue performing generation repetition based on the genetic algorithm. The control circuit 210 may provide the second electronic device 120 with the next generation DOE set generated from the GA execution circuit 230.
The PBD execution circuit 220 may generate an initial PBD DOE set based on the PBD. The PBD may refer to a design method that may examine factors in which various independent factors may influence results of an experiment. Based on the PBD, factors influencing memory characteristics (e.g., I/O margin, eye size in eye diagrams, or the like) may be explored while minimizing the number of experiments by selecting multiple factors to evenly divide the entire experimental space. The initial PBD DOE set may be used to search for an initial setting of the memory in the second electronic device 120. The second electronic device 120 may respond to the first electronic device 110 with a characteristic evaluation result based on the initial PBD DOE set, and the first electronic device 110 may determine a starting DOE set for starting a genetic algorithm based on the characteristic evaluation result corresponding to the initial PBD DOE set. An example of determining an optimal case is further described with reference to
The GA execution circuit 230 may perform a genetic algorithm based on the DOE set. That is, the GA execution circuit 230 may use the DOE set already provided to the second electronic device 120 as a previous generation to generate a new DOE set of the next generation based on at least one of various selection operators (e.g., roulette wheel selection, ranking selection, tournament selection, elite preserving selection, or the like), various crossover operators (e.g., single point crossover, two point crossover, uniform crossover, arithmetic crossover, or the like), and/or various mutation operators (e.g., scramble mutation, inversion mutation, insertion mutation, or the like). An example of the generation repetition based on the genetic algorithm of the GA execution circuit 230 is described later with reference to
Referring to
The processing circuit 215 may control the overall operation of the second electronic device 120. The processing circuit 215 may correspond to a central processing unit (CPU). For example, the processing circuit 215 may perform booting by loading a boot loader into a DRAM in response to a power-on of the second electronic device 120. As another example, the processing circuit 215 may change a setting value of the memory device 225.
According to an embodiment, the processing circuit 215 may obtain a characteristic evaluation result of the memory device 225 by receiving the DOE set from the first electronic device 110 and changing the setting value of the memory device 225 based on the DOE set. For example, when the DOE set includes eight (8) cases, the processing circuit 215 may change the setting value of the memory device 225 eight (8) times, and evaluate the semiconductor characteristics (e.g., I/O margin, eye size of an eye diagram, or the like) of the memory device 225 each time the setting value is changed. The processing circuit 215 may provide a characteristic evaluation result of the memory device 225 to the first electronic device 110.
The memory device 225 may include at least one of a non-volatile memory or a volatile memory. Examples of nonvolatile memory may include, but not be limited to, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), NAND flash memory, vertical NAND (V-NAND or 3D NAND) flash memory, NOR flash memory, resistive random-access memory (RRAM or ReRAM), phase-change random-access memory (PRAM), magnetoresistive random-access memory (MRAM), ferroelectric random-access memory (FRAM), or the like. Examples of volatile memory may include, but not be limited to, random-access memory (RAM), static RAM (SRAM), DRAM, or the like.
Referring to
Referring to
As another example, the third case Case3 may evaluate semiconductor characteristics of the memory device 225 when the first TMRS factor TMRS1, the third TMRS factor TMRS3, and the fourth TMRS factor TMRS4 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the second TMRS factor TMRS2, the fifth TMRS factor TMRS5, the sixth TMRS factor TMRS6, and the seventh TMRS factor TMRS7) are set to OFF (or NEGATIVE).
As another example, the fourth case Case4 may evaluate semiconductor characteristics of the memory device 225 when the first TMRS factor TMRS1, the fifth TRMS factor TMRS5, the sixth TRMS factor TMRS6, are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the second TRMS factor TMRS2, the third TRMS factor TMRS3, the fourth TRMS factor TMRS4, and the seventh TRMS factor TMRS7) are set to OFF (or NEGATIVE).
As another example, the fifth case Case5 may evaluate semiconductor characteristics of the memory device 225 when the second TRMS factor TMRS2, the third TRMS factor TMRS3, and the fifth TRMS factor TMRS5 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the first TRMS factor TMRS1, the fourth TRMS factor TMRS4, the sixth TRMS factor TMRS6, and the seventh TRMS factor TMRS7) are set to OFF (or NEGATIVE).
As another example, the sixth case Case6 may evaluate semiconductor characteristics of the memory device 225 when the second TRMS factor TMRS2, the fourth TRMS factor TMRS4, and the sixth TRMS factor TMRS6 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the first TRMS factor TMRS1, the third TRMS factor TMRS3, the fifth TRMS factor TMRS5, and the seventh TRMS factor TMRS7) are set to OFF (or NEGATIVE).
As another example, the seventh case Case7 may evaluate semiconductor characteristics of the memory device 225 when the third TRMS factor TMRS3, the sixth TRMS factor TMRS6, and the seventh TRMS factor TMRS7 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the first TRMS factor TMRS1, the second TRMS factor TMRS2, the fourth TRMS factor TMRS4, and the fifth TRMS factor TMRS5) are set to OFF (or NEGATIVE).
As another example, the eighth case Case8 may evaluate semiconductor characteristics of the memory device 225 when the fourth TRMS factor TMRS4, the fifth TRMS factor TMRS5, and the seventh TRMS factor TMRS7 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the first TRMS factor TMRS1, the second TRMS factor TMRS2, the third TRMS factor TMRS3, and the sixth TRMS factor TMRS6) are set to OFF (or NEGATIVE).
Although table 400 describes an example of an initial PBD DOE set with eight (8) cases and seven (7) TMRS factors, the present disclosure is not limited in this regard. For example, the initial PBD DOE set may include additional cases (e.g., more than eight (8)), may include less cases (e.g., less than eight (8)), may include additional TMRS factors (e.g., more than seven (7)), may include less TMRS factors (e.g., less than seven (7)), or any combination thereof. Alternatively or additionally, the initial PBD DOE set may include the same and/or different combinations of TMRS factors in the cases.
The first electronic device 110 may generate an initial PBD DOE set of the table 400 of
In operation S320, the first electronic device 110 may receive initial characteristic evaluation of the initial PBD DOE set. The second electronic device 120 may receive the initial PBD DOE set from the first electronic device 110 and perform semiconductor characteristic evaluation on the memory device 225. For example, the second electronic device 120 may perform semiconductor characteristic evaluation for each of the first to eighth cases Case1 to Case8 of the initial PBD DOE set. That is, the second electronic device 120 may measure the I/O margin and/or the eye size of the eye diagram by changing the setting of the memory device 225 according to the first to seventh TMRS factors TMRS1 to TMRS7 mapped to the first case Case1, applying an input signal to the memory device 225 for which the setting change has been completed, and receiving an output signal. The second electronic device 120 may transmit, to the first electronic device 110, the characteristic evaluation result measured for the first case Case1. For the remaining second to eighth cases Case2 to Case8, the second electronic device 120 may repeatedly evaluate the semiconductor characteristics of the memory device 225 and transmit the measured characteristic evaluation results to the first electronic device 110. The results of the semiconductor characteristic evaluation of the memory device 225 set according to the initial PBD DOE set may correspond to the initial characteristic evaluation.
In operation S330, the first electronic device 110 may generate the starting DOE set using the correlation identified based on the initial characteristic evaluation. The starting DOE set may refer to a set provided as an input to the GA execution circuit 230. That is, the starting DOE set may correspond to the first generation DOE set (or the first parent DOE) in which the genetic algorithm starts.
In order to determine the starting DOE set, the first electronic device 110 may identify a correlation based on the initial characteristic evaluation. For example, referring to
The first electronic device 110 may obtain a starting DOE set to be used as an input of a genetic algorithm by adding the optimal case and the basic case to the existing initial PBD DOE set. The basic case may refer to a case in which the first to seventh TMRS factors TMRS1 to TMRS7 are OFF (or NEGATIVE). The adding of the basic case to the generating of the starting DOE may increase the likelihood of reaching a global optima without falling into the local optima in performing the genetic algorithm. Referring to
In operation S340, the first electronic device 110 may perform a genetic algorithm using a starting DOE set as an input. For example, the first electronic device 110 may provide the generated starting DOE set as an input to the GA execution circuit 230. The GA execution circuit 230 may generate a next generation DOE set by performing a genetic algorithm using the starting DOE set as the previous generation.
Referring to
According to an embodiment, the first electronic device 110 may cross over cases having high scores in the starting DOE set. The first electronic device 110 may cross over the TMRS factors of the first parent case Parent1 and the third parent case Parent3 in the starting DOE set. In the case of
According to an embodiment, the first electronic device 110 may cross over cases having low scores in the starting DOE set. The first electronic device 110 may cross over the TMRS factors of the second parent case Parent2 and the fourth parent case Parent4 in the starting DOE set. Referring to
According to an embodiment, the first electronic device 110 may cross over adjacent cases in the starting DOE set. Referring to
According to an embodiment, the first electronic device 110 may cross over and mutate any cases in the starting DOE set. Referring to
However, the embodiment in which the first electronic device 110 performs a genetic algorithm is not limited thereto, and a new DOE set of the next generation may be generated based on at least one of various selection operators (e.g., roulette wheel selection, ranking selection, tournament selection, elite preserving selection, or the like), various crossover operators (e.g., single point crossover, two point crossover, uniform crossover, arithmetic crossover, or the like), and various mutation operators (e.g., scramble mutation, inversion mutation, insertion mutation, or the like). The first electronic device 110 may transmit the new DOE set of the next generation to the second electronic device 120 to evaluate semiconductor characteristics, and obtain a characteristic evaluation result for the new DOE set of the next generation. When the characteristic evaluation result for the new DOE set of the next generation does not satisfy the termination condition of the genetic algorithm, it may be repeated to generate the new DOE set of the next generation by performing the genetic algorithm for generation repetition again.
In operation S350, when the termination condition of the genetic algorithm is satisfied, the first electronic device 110 may transmit an optimal case among the termination DOE sets. The first electronic device 110 may transmit the new DOE set of the next generation to the second electronic device 120 to evaluate semiconductor characteristics, and obtain a characteristic evaluation result for the new DOE set of the next generation. When the characteristic evaluation result for the new DOE set of the next generation satisfies the termination condition of the genetic algorithm, the genetic algorithm for generation repetition may be terminated without further performing the genetic algorithm. The termination condition may be based on, for example, whether a case exceeding a threshold score exists, or whether a characteristic evaluation result exceeding a threshold exists. However, the above termination condition is not limited thereto, and it may be determined that the termination condition is satisfied if the generation repetition is performed in excess of the threshold number of times even if the above-described threshold score or termination condition exceeding the threshold value is not achieved to prevent excessive delay in a booting process.
Hereinafter, for convenience of description, description is made based on a case in which the memory device 225 is a DRAM. However, as described above, the memory device 225 is not limited to DRAM and may be various volatile memories or nonvolatile memories including NAND flash memories.
Referring to
In operation 815, the first electronic device 110 may generate an initial PBD DOE. The PBD execution circuit 220 may generate the DOE based on TMRS factors (e.g., 31 TMRS factors) influencing upon the performance evaluation of the DRAM. For example, the initial PBD DOE may include 32 cases. Referring to
In operation 820, the first electronic device 110 may provide the initial PBD DOE to the second electronic device 120 of
In operation 825, the processing circuit 215 may provide the memory device 225 with a plurality of case setting values. The processing circuit 215 may sequentially change the setting value of the memory device 225 according to the combination of TMRS factors of the 32 cases, and evaluate the I/O margin value of the case set in operation 830. For example, the processing circuit 215 may evaluate the I/O margin by setting the memory device 225 according to the TMRS factor combination of the first case of the 32 cases provided from the first electronic device 110 and applying an input signal to the memory device 225. Thereafter, the processing circuit 215 may sequentially evaluate the individual characteristics up to the I/O margin according to the TMRS factor combination of the 32nd case.
In operation 835, the first electronic device 110 may receive a plurality of I/O margin evaluation values. Although
In operation 840, the first electronic device 110 may determine a linear coefficient based on the plurality of I/O margin evaluation values. For example, the first electronic device 110 may determine whether the I/O margin evaluation value improves when the first TMRS factor from among 31 TMRS factors is ON or OFF. For example, the first electronic device 110 may determine the linear coefficient to be either ON, OFF, or NULL (e.g., may indicate that there is no correlation) by summing the evaluation values of 32 cases corresponding to the first TMRS factor. The first electronic device 110 may determine 31 linear coefficients by performing the same process on each of the 31 TMRS factors.
In operation 845, the first electronic device 110 may generate an optimal case according to a linear coefficient. The optimal case may refer to a case in which each of the 31 TMRS factors is set to match the linear coefficient determined in operation 840.
In operation 850, the first electronic device 110 may provide information on the optimal case to the second electronic device 120. For example, the first electronic device 110 may provide the processing circuit 215 with an optimal case in which each of the 31 TMRS factors is set to match a linear coefficient.
In operation 855, the processing circuit 215 may provide optimal case setting values to the memory device 225. The processing circuit 215 may change the setting value of the memory device 225 according to a combination of 31 TMRS factors indicated by the optimal case, and may evaluate an I/O margin value of the memory device 225 in operation 860. For example, the processing circuit 215 may set the memory device 225 according to the TMRS factor combination of the optimal case provided from the first electronic device 110 and apply an input signal to the memory device 225 to evaluate the I/O margin.
In operation 865, the first electronic device 110 may receive an I/O margin evaluation value. The received I/O margin evaluation value may be an I/O margin evaluation value corresponding to the optimal case generated in operation 845.
In operation 870, the first electronic device 110 may generate a starting DOE set. The first electronic device 110 may generate a starting DOE set by additionally merging the optimal case and the basic case with the initial PBD DOE. The basic case may correspond to a case in which all TMRS factors are OFF. Accordingly, the starting DOE set may include 34 cases. However, the above-described embodiments are not limited thereto, and a starting DOE set may be generated by additionally merging cases in which all TRMS factors are ON.
In operation 875, the first electronic device 110 may generate the next generation DOE set based on the genetic algorithm. The first electronic device 110 may randomly select at least two cases from among the 34 parent cases, and generate a single child case based on various selection operators, crossover operators, and mutation operators for the selected cases. The first electronic device 110 may generate a next generation DOE set according to the genetic algorithm by randomly generating 34 child cases.
In operation 880, the first electronic device 110 may perform I/O margin evaluation whenever generating a generation-specific DOE set. For example, when the next generation DOE set was generated based on the starting DOE set in operation 875, the second generation DOE set may have been generated. The first electronic device 110 may obtain an I/O margin evaluation value for each case by providing 34 cases of the second generation DOE set to the second electronic device 120.
In operation 885, the first electronic device 110 may determine whether the I/O margin evaluation satisfies a termination condition. For example, in operation 880, the first electronic device 110 may have obtained I/O margin evaluation values for the second generation DOE set. The first electronic device 110 may determine whether the termination condition of the genetic algorithm is satisfied based on the I/O margin evaluation values for the second generation DOE set. For example, the first electronic device 110 may determine whether there is a case exceeding a threshold value among the 34 I/O margin evaluation values corresponding to the 34 cases of the second generation DOE set. When there is a case exceeding the threshold value among 34 I/O margin evaluation values for the second generation DOE set, the first electronic device 110 may determine that the termination condition is satisfied and proceed to operation 890. If no case exceeds the threshold value from among the 34 I/O margin evaluation values corresponding to the 34 cases of the second generation DOE set, it may be determined that the termination condition is not satisfied and may return to operation 875. In such a case, the first electronic device 110 may generate the third generation DOE set by re-performing the genetic algorithm for the input of the second generation DOE set. In operation 880, the first electronic device 110 may provide the third generation DOE set to the second electronic device 120 of
In operation 890, the first electronic device 110 may determine a final case of a termination DOE set. The termination DOE set may refer to as a DOE set of a generation that satisfies the termination condition of the genetic algorithm. The first electronic device 110 may determine, as a final case, a case having the highest score or a case having the highest I/O evaluation margin value among 34 cases included in the termination DOE set.
In operation 895, the first electronic device 110 may provide the second electronic device 120 of
Referring to
The processing circuit 910 may include a PBD execution circuit 912 and a GA execution circuit 914. That is, the electronic device 130 of
In an embodiment, the processing circuit 910 may not include the PBD execution circuit 912. In such an embodiment, instead of generating an initial PBD DOE set by the PBD execution circuit 912, the electronic device 130 may pre-store the initial PBD DOE set in a ROM area accessible at boot time, and load the initial PBD DOE set to identify the initial characteristics of the memory device 920.
Referring to
The HBM 1020 may include a plurality of stacked memory dies, and through a plurality of channels, data may be written in parallel to the plurality of memory dies and/or data may be read in parallel from the plurality of memory dies. The HBM 1020 may include a process in memory (PIM) circuit 1022. The PIM circuit 1022 may perform arithmetic processing by a kernel loaded by the CPU of the processing circuit 215. For example, the PIM circuit 1022 may generate an initial PBD DOE set based on the PBD. The PIM circuit 1022 may include an internal block and/or circuit capable of performing a genetic algorithm that performs generation repetition by stochastically changing each element. For example, the PIM circuit 1022 may perform a genetic algorithm based on a DOE set. The PIM circuit 1022 may generate a new DOE set of the next generation using the initial PBD DOE set as the previous generation.
Referring to
According to an embodiment, the default may represent an I/O margin evaluation value when all TMRS factors influencing upon the I/O margin of the memory device are OFF. As shown in the first graph 1110, the I/O margin evaluation value may increase as generations are repeated using a genetic algorithm between TMRS factors influencing upon the I/O margin of the memory device. However, in the case of the first graph 1110, the TMRS factors were not selected so that the entire experimental space was evenly divided because all TMRS factors were OFF in the basic case, which is the input of the genetic algorithm. For example, after repeating the generation repetition “a” times, according to the genetic algorithm, the I/O margin evaluation value may not be significantly improved. That is, the input of the genetic algorithm may not evenly divide the entire experimental space and, accordingly, may have reached a local optima.
According to the second graph 1120, the I/O margin evaluation value may increase as generations are repeated using a genetic algorithm between TMRS factors influencing the I/O margin of the memory device. However, compared with the first graph 1110, it is possible to observe a relatively rapid increase in the I/O margin evaluation value from the initial time point of generation repetition. The rapid increase may be a result of performing linear analysis based on the initial PBD DOE, according to
Referring to
While the present disclosure has been particularly shown and described with reference to embodiments thereof, it is to be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0161436 | Nov 2023 | KR | national |
| 10-2024-0033324 | Mar 2024 | KR | national |
