Patent Application
20220392399
The disclosure relates to a device, and more particularly to an electronic device with an element protection function.
With the advancement of technology, electronic devices are gradually designed to be light, thin, and compact. However, element reliability may thus face increasingly huge challenges, especially those safety problems related to elements of electronic devices such as damage caused by continuous high current and high temperature that people have to face.
The disclosure is directed to an electronic device that may provide an element protection function through a protection circuit coupled with a pixel circuit.
According to some embodiments of the disclosure, the electronic device of the disclosure includes a pixel circuit and a protection circuit. The pixel circuit includes a driving transistor. The protection circuit includes a first connection transistor, a first switching transistor, and a logic circuit. The first connection transistor is coupled to the driving transistor. The first switching transistor is coupled to the first connection transistor. The logic circuit is coupled to the first switching transistor.
According to some embodiments of the disclosure, the electronic device of the disclosure may detect an operation signal (e.g., a scan signal and/or a reset signal) of the pixel circuit through the protection circuit. When the operation signal of the pixel circuit is abnormal, the protection circuit may close the driving transistor of the pixel circuit of abnormal pixels and may thus provide the element protection function.
Embodiments accompanied with drawings are described in detail below to make the aforementioned features and advantages of the disclosure comprehensible.
References of the exemplary embodiments of the disclosure are to be made in detail. Examples of the exemplary embodiments are illustrated in the drawings. If applicable, the same reference numerals in the drawings and the descriptions indicate the same or similar parts.
The disclosure may be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in order to facilitate understanding and for concision of the drawings, only a part of an electronic device is shown in multiple drawings in the disclosure, and certain elements in the drawings are not drawn to actual scale. In addition, the number and size of each element in the drawings are only exemplary and are not used to limit the scope of the disclosure.
Certain words will be used to refer to specific devices throughout the specification and the appended claims of the disclosure. People skilled in the art should understand that electronic device manufacturers may refer to same components under different names. The disclosure does not intend to distinguish between components having same functions but different names. In the following specification and claims, the words “having” and “including” are open-ended words and thus should be interpreted as “including but not limited to.”
In some embodiments of the disclosure, terms concerning attachments and connections such as “connected,” “interconnected,” and the like, unless defined otherwise, mean two structures directly contact each other, or mean the two structures do not directly contact each other and other structures are disposed therebetween. The terms concerning attachments and connections may also include a relationship in which the two structures are both movable or fixed. In addition, the terms “electrically connected to” and “coupled to” include any direct and indirect electrical connection means.
Ordinal numbers in this specification and the claims such as “first” and “second” are used to modify a device, and do not imply or represent that the (or these) component(s) has (or have) any ordinal number, and do not indicate any order between an element and another element, or an order in a manufacturing method. These ordinal numbers are merely used to clearly distinguish an element having a name with another element having the same name. Different terms may be used in the claims and the specification, so that a first member in the specification may be a second member in the claims. It should be understood that the following embodiments may replace, reorganize, and mix the technical features in several different embodiments to complete other embodiments without departing from the spirit of the disclosure.
It should be understood that the following embodiments may replace, reorganize, and mix the features in several different embodiments to complete other embodiments without departing from the spirit of the disclosure. As long as the features of the embodiments do not violate the spirit of the disclosure or conflict each other, they may be mixed and matched as desired.
In the following embodiments of the disclosure, an electronic device may include a display device, an antenna device, a sensing device, or a splicing device, but the disclosure is not limited thereto. The electronic device may be a bendable electronic device or a flexible electronic device. The electronic device includes a diode element, which may or may not emit light. The diode element may include, for example, a PN diode or a PIN diode, but the disclosure is not limited thereto. The electronic device may include, for example, liquid crystal (LC), a light emitting diode, a quantum dot (QD), fluorescence, phosphor, other suitable materials, or a combination of the above materials, but the disclosure is not limited thereto. The light emitting diode may include, for example, an organic light emitting diode or an inorganic light emitting diode. The light emitting diode may include, for example, an active-matrix organic light emitting diode (AMOLED), an organic light emitting diode (OLED), a mini light emitting diode (mini LED), a micro light emitting diode (micro LED), a quantum dot light emitting diode, or the like, but the disclosure is not limited thereto. The antenna device may be, for example but not limited to, a liquid crystal antenna. The splicing device may be, for example but not limited to, a display splicing device or an antenna splicing device. It should be noted that the electronic device may be any combination of the foregoing, but the disclosure is not limited thereto.
In the following embodiments, the first end, the second end, and the control end of a transistor may refer to, for example, a source, a gate, and a drain of a thin-film transistor (TFT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or other transistors.
In this embodiment, the driving transistor 111, the pixel switching transistor 112, the scan transistor 113, and the reset transistor 114 may respectively be P-type thin-film transistors or P-type MOSFETs, but the disclosure is not limited thereto. In addition, in some embodiments, the pixel circuit 110 may further include other transistors and not be limited to the 3T1C pixel circuit architecture shown in
In this embodiment, the pixel circuit 110 may be respectively operated in a reset mode and a driving mode (which may also be referred to as a display mode or a light emitting mode) during a reset period and a driving period according to the driving data, the control signal EM, the scan signal Sn, and the reset signal RST. In this embodiment, the protection circuit 120 may receive the control signal EM, the scan signal Sn, and the reset signal RST to detect at least one of the scan signal Sn and the reset signal RST. When signal (voltage) abnormality of at least one of the scan signal Sn and the reset signal RST occurs, the protection circuit 120 may provide a shutdown voltage to the control end of the driving transistor 111 through the circuit node N1 to turn off the driving transistor 111, which may effectively protect the diode element 115. In addition, in some embodiments, the protection circuit 120 may further be coupled to other pixel circuits of the electronic device 100.
In this embodiment, the protection circuit 220 includes a logic circuit 221, a switching transistor 222, and connection transistors 223_1 to 223_3. The connection transistors 223_1 to 223_3 may be respectively coupled to driving transistors in the pixel circuits 210_1 to 210_3 (e.g., the driving transistor 111 in
In this embodiment, the switching transistor 222 and the connection transistors 223_1 to 223_3 may respectively be P-type thin-film transistors or P-type MOSFETs, but the disclosure is not limited thereto. In this embodiment, when signal (e.g., a voltage signal or the like) abnormality (e.g., a false trigger or the like) of at least one of the scan signal and the reset signal occurs, the logic circuit 221 may provide a shutdown voltage to the control end of the driving transistors in the pixel circuits 210_1 to 210_3 through the circuit nodes (the circuit node N1 as shown in
In this embodiment, the protection circuit 320 includes a logic circuit 321, switching transistors 322, 324, connection transistors 323_1 to 323_3, and impedance circuits 325, 326. The connection transistors 323_1 to 323_3 may be respectively coupled to driving transistors in the pixel circuits 310_1 to 310_3 (e.g., the driving transistor 111 in
In this embodiment, the impedance circuit 325 may include transistors 325_1 and 325_2. The first end of the transistor 325_1 is coupled to the circuit node N31. The second end of the transistor 325_1 is coupled to the control end of the transistor 325_1 and the first end of the transistor 325_2. The second end of the transistor 325_2 is coupled to the control end of the transistor 325_2 and a ground voltage GND. However, in some embodiments, the impedance circuit 325 may also be other types of impedance circuits and not be limited to those shown in
In this embodiment, the impedance circuit 326 may include a transistor 326_1. The first end of the transistor 326_1 may receive a reference voltage V1, and the reference voltage V1 is a high potential voltage and may be, for example, the protection voltage Vp. The second end of the transistor 326_1 is coupled to the control end of the transistor 326_1 and the circuit node N32. However, in some embodiments, the impedance circuit 326 may also be other types of impedance circuits and not be limited to those shown in
In this embodiment, the logic circuit 321 includes a circuit connection transistor 321_1, a switching circuit 321_2, a circuit switching transistor 321_3, and an impedance circuit 321_4. The circuit connection transistor 321_1 is coupled between the switching transistor 324 and the reference voltage V1. The first end of the circuit connection transistor 321_1 may receive the reference voltage V1. The second end of the circuit connection transistor 321_1 is coupled to the first end of the switching transistor 324. The switching circuit 321_2 is coupled to the control end of the circuit connection transistor 321_1. The circuit switching transistor 321_3 is coupled to the reference voltage V1. The first end of the circuit switching transistor 321_3 may receive the reference voltage V1. The control end of the circuit switching transistor 321_3 may receive the control signal EM. The second end of the circuit switching transistor 321_3 is coupled to the switching circuit 321_2. The switching circuit 321_2 includes a scan transistor 321_21 and a reset transistor 321_22. The first end of the scan transistor 321_21 and the reset transistor 321_22 is coupled to the second end of the circuit switching transistor 321_3. The control end of the scan transistor 321_21 may receive the scan signal Sn. The control end of the reset transistor 321_22 may receive the reset signal RST. The second end of the scan transistor 321_21 and the reset transistor 321_22 is coupled to the impedance circuit 321_4. The impedance circuit 321_4 may include a transistor 321_41. The first end of the transistor 321_41 is coupled to the control end of the transistor 321_41, and is electrically connected with the control end of the circuit connection transistor 321_1 and the second end of the scan transistor 321_21 and the reset transistor 321_22. The second end of the transistor 321_41 is coupled to the ground voltage GND. However, in some embodiments, the impedance circuit 321_4 may also be other types of impedance circuits and not be limited to those shown in
In this embodiment, the circuit connection transistor 321_1, the connection transistors 323_1 to 323_3, the scan transistor 321_21, the reset transistor 321_22, the circuit switching transistor 321_3, the switching transistors 322, 324, and the transistors 321_41, 325_1, 325_2, 326_1 may respectively be P-type thin-film transistors or P-type MOSFETs, but the disclosure is not limited thereto.
Please refer to
During a reset period PR from time t1 to time t2, the reset signal RST switches from a high potential voltage to a low potential voltage to turn on the respective reset transistors of the pixel circuits 310_1 to 310_3 and respectively reset the storage capacitors of the pixel circuits 310_1 to 310_3. During a period PS from time t3 to time t4, the scan signal Sn switches from a high potential voltage to a low potential voltage to turn on the respective scan transistors of the pixel circuits 310_1 to 310_3 and respectively write the driving data into the storage capacitors of the pixel circuits 310_1 to 310_3. As shown in the operation states 1 to 3 of Table 1 below, the circuit node N31 maintains a low potential voltage, and the circuit node N32 maintains a high potential voltage to turn off the connection transistors 323_1 to 323_3.
During the driving period P2 between time t5 and time t6, the control signal EM is a low potential voltage to turn on the circuit switching transistor 321_3, the switching transistor 322, the switching transistor 324, and the respective pixel switching transistors of the pixel circuits 310_1 to 310_3. The reset signal RST and the scan signal Sn are respectively high potential voltages to turn off the respective reset transistors and the scan transistors of the pixel circuits 310_1 to 310_3. As shown in the operation state 4 of Table 1 below, the circuit nodes N31 and N32 are high potential voltage to turn off the connection transistors 323_1 to 323_3. It should be noted that since the scan transistor 321_21 and the reset transistor 321_22 of the switching circuit 321_2 may also receive the reset signal RST and the scan signal Sn, when signal (voltage) abnormality (a false trigger) of at least one of the reset signal RST and the scan signal Sn occurs, for example, when at least one of the reset signal RST and the scan signal Sn switches from a high potential voltage to a low potential voltage during the driving period P2, then at least one of the scan transistor 321_21 and the reset transistor 321_22 is conducted, and the circuit connection transistor 321_1 is thus conducted as well. As shown in the operation states 5 to 7 of Table 1 below, when signal (voltage) abnormality of at least one of the reset signal RST and the scan signal Sn occurs, the circuit nodes N31 and N32 may respectively switch to a low potential voltage to conduct the connection transistors 323_1 to 323_3. In this regard, the circuit connection transistor 321_1 may provide the reference voltage V1 to the control end of the connection transistors 323_1 to 323_3 through the switching transistors 322, 324 and the circuit nodes N31, N32 to conduct the connection transistors 323_1 to 323_3. Next, the connection transistors 323_1 to 323_3 may respectively provide the protection voltage Vp to the respective driving transistors of the pixel circuits 310_1 to 310_3 to turn off the driving transistors. Therefore, the protection circuit 320 may effectively protect the diode elements in the pixel circuits 310_1 to 310_3 of the pixel 310 and may avoid the voltage signal abnormality of at least one of the reset signal RST and the scan signal Sn from causing the damage to the diode elements in the pixel circuits 310_1 to 310_3, which may thus achieve the current overload protection function of the pixel 310.
In addition, in some embodiments, the switching circuit 321_2 may include only one of the scan transistor 321_21 and the reset transistor 321_22, and when signal (voltage) abnormality of one of the scan signal Sn and the reset signal RST occurs, the protection circuit 320 may conduct the connection transistors 323_1 to 323_3 to turn off the respective driving transistors of the pixel circuits 310_1 to 310_3, which may thus achieve the current overload protection function of the pixel 310.
In this embodiment, the protection circuit 520 includes a logic circuit 521, switching transistors 522, 524, connection transistors 523_1 to 523_3, and impedance circuits 525, 526. The connection transistors 523_1 to 523_3 may be respectively coupled to the driving transistors (e.g., the driving transistor 111 in
VDD shown in
In this embodiment, the impedance circuit 525 may include transistors 525_1 and 525_2. The first end of the transistor 525_1 is coupled to the second end of the switching transistor 524. The second end of the transistor 525_1 is coupled to the control end of the transistor 525_1 and the first end of the transistor 525_2. The second end of the transistor 525_2 is coupled to the control end of the transistor 525_2 and the ground voltage GND. However, in some embodiments, the impedance circuit 525 may also be other types of impedance circuits and not be limited to those shown in
In this embodiment, the impedance circuit 526 may include a transistor 526_1. The first end of the transistor 526_1 may receive the reference voltage V1, and the reference voltage V1 is a high potential voltage and may be, for example, the protection voltage Vp. The second end of the transistor 526_1 is coupled to the control end of the transistor 526_1 and the circuit node N52. However, in some embodiments, the impedance circuit 526 may also be other types of impedance circuits and not be limited to those shown in
In this embodiment, the logic circuit 521 includes a circuit connection transistor 521_1, a switching circuit 521_2, a circuit switching transistor 521_3, and an impedance circuit 521_4. The circuit connection transistor 521_1 is coupled between the circuit node N51 and the reference voltage V1. The first end of the circuit connection transistor 521_1 may receive the reference voltage V1. The second end of the circuit connection transistor 521_1 is coupled to the first end of the switching transistor 524. The switching circuit 521_2 is coupled to the control end of the circuit connection transistor 521_1. The circuit switching transistor 521_3 is coupled to the reference voltage V1. The first end of the circuit switching transistor 521_3 may receive the reference voltage V1. The control end of the circuit switching transistor 521_3 may receive the control signal EM. The second end of the circuit switching transistor 521_3 is coupled to the switching circuit 521_2. The switching circuit 521_2 includes a scan transistor 521_21 and a reset transistor 521_22. The first end of the scan transistor 521_21 and the reset transistor 521_22 is coupled to the second end of the circuit switching transistor 521_3. The control end of the scan transistor 521_21 may receive the scan signal Sn. The control end of the reset transistor 521_22 may receive the reset signal RST. The second end of the scan transistor 521_21 and the reset transistor 521_22 is coupled to the impedance circuit 521_4. The impedance circuit 521_4 may include a transistor 521_41. The first end of the transistor 521_41 is coupled to the control end of the transistor 521_41, and is electrically connected with the control end of the circuit connection transistor 521_1 and the second end of the scan transistor 521_21 and the reset transistor 521_22. The second end of the transistor 521_41 is coupled to the ground voltage GND. However, in some embodiments, the impedance circuit 521_4 may also be other types of impedance circuits and not be limited to those shown in
In this embodiment, the circuit connection transistor 521_1, the connection transistors 523_1 to 523_3, the scan transistor 521_21, the reset transistor 521_22, the circuit switching transistor 521_3, the switching transistors 522, 524, and the transistors 521_41, 525_1, 525_2, 526_1 may respectively be P-type thin-film transistors or P-type MOSFETs, but the disclosure is not limited thereto.
With reference to
During the reset period PR from time t1 to time t2, the reset signal RST switches from a high potential voltage to a low potential voltage to turn on the respective reset transistors of the pixel circuits 510_1 to 510_3 and respectively reset the storage capacitors of the pixel circuits 510_1 to 510_3. During the period PS from time t3 to time t4, the scan signal Sn switches from a high potential voltage to a low potential voltage to turn on the respective scan transistors of the pixel circuits 510_1 to 510_3 and respectively write the driving data into the storage capacitors of the pixel circuits 510_1 to 510_3. As shown in the operation states 1 to 3 of Table 2 below, the circuit nodes N51 and N52 maintain a high potential voltage to turn off the connection transistors 523_1 to 523_3.
During the driving period P2 between time t5 and time t6, the control signal EM is a low potential voltage to turn on the circuit switching transistor 521_3, the switching transistor 522, the switching transistor 524, and the respective pixel switching transistors of the pixel circuits 510_1 to 510_3. The reset signal RST and the scan signal Sn are respectively high potential voltages to turn off the respective reset transistors and the scan transistors of the pixel circuits 510_1 to 510_3. As shown in the operation state 4 of Table 2 below, the circuit nodes N51 and N52 are high potential voltage, so as to turn off the connection transistors 523_1 to 523_3. It should be noted that since the scan transistor 521_21 and the reset transistor 521_22 of the switching circuit 521_2 may also receive the reset signal RST and the scan signal Sn, when signal (voltage) abnormality (a false trigger) of at least one of the reset signal RST and the scan signal Sn occurs, for example, when at least one of the reset signal RST and the scan signal Sn switches from a high potential voltage to a low potential voltage during the driving period P2, then at least one of the scan transistor 521_21 and the reset transistor 521_22 is conducted, and the circuit connection transistor 521_1 is thus conducted as well. As shown in the operation states 5 to 7 of Table 2 below, when signal (voltage) abnormality of at least one of the reset signal RST and the scan signal Sn occurs, the circuit nodes N51 and N52 may respectively switch to a low potential voltage to conduct the connection transistors 523_1 to 523_3. In this regard, the circuit connection transistor 521_1 may provide the reference voltage V1 to the control end of the connection transistors 523_1 to 523_3 through the switching transistors 522, 524 and the circuit nodes N51, N52 to conduct the connection transistors 523_1 to 523_3. Next, the connection transistors 523_1 to 523_3 may respectively provide the protection voltage Vp to the respective driving transistors of the pixel circuits 510_1 to 510_3 to turn off the driving transistors. Therefore, the protection circuit 520 may effectively protect the diode elements in the pixel circuits 510_1 to 510_3 of the pixel 510 and may avoid the voltage signal abnormality of at least one of the reset signal RST and the scan signal Sn from causing the damage to the diode elements in the pixel circuits 510_1 to 510_3, which may thus achieve the current overload protection function of the pixel 510.
In addition, in some embodiments, the switching circuit 521_2 may include only one of the scan transistor 521_21 and the reset transistor 521_22, and when signal (voltage) abnormality of one of the scan signal Sn and the reset signal RST occurs, the protection circuit 520 may conduct the connection transistors 523_1 to 523_3 to turn off the respective driving transistors of the pixel circuits 510_1 to 510_3, which may thus achieve the current overload protection function of the pixel 510.
In this embodiment, the protection circuit 620 includes a logic circuit 621, a switching transistor 622, connection transistors 623_1 to 623_3, and impedance circuits 625, 626. The connection transistors 623_1 to 623_3 may be respectively coupled to the driving transistors (e.g., the driving transistor 111 in
In this embodiment, the impedance circuit 625 may include transistors 625_1 and 625_2. The first end of the transistor 625_1 is coupled to the circuit node N61. The second end of the transistor 625_1 is coupled to the control end of the transistor 625_1 and the first end of the transistor 625_2. The second end of the transistor 625_2 is coupled to the control end of the transistor 625_2 and the ground voltage GND. However, in some embodiments, the impedance circuit 625 may also be other types of impedance circuits and not be limited to those shown in
In this embodiment, the impedance circuit 626 may include a transistor 626_1. The first end of the transistor 626_1 may receive the reference voltage V1, and the reference voltage V1 is a high potential voltage and may be, for example, the protection voltage Vp. The second end of the transistor 626_1 is coupled to the control end of the transistor 626_1 and the circuit node N62. However, in some embodiments, the impedance circuit 626 may also be other types of impedance circuits and not be limited to those shown in
In this embodiment, the logic circuit 621 includes a circuit connection transistor 621_1, a switching circuit 621_2, a circuit switching transistor 621_3, and an impedance circuit 621_4. The circuit connection transistor 621_1 is coupled between the circuit node N61 and the reference voltage V1. The first end of the circuit connection transistor 621_1 may receive the reference voltage V1. The second end of the circuit connection transistor 621_1 is coupled to the first end of the switching transistor 622. The switching circuit 621_2 is coupled to the control end of the circuit connection transistor 621_1. The circuit switching transistor 621_3 is coupled to the reference voltage V1. The first end of the circuit switching transistor 621_3 may receive the reference voltage V1. The control end of the circuit switching transistor 621_3 may receive the control signal EM. The second end of the circuit switching transistor 621_3 is coupled to the switching circuit 621_2. The switching circuit 621_2 includes a scan transistor 621_21 and a reset transistor 621_22. The first end of the scan transistor 621_21 and the reset transistor 621_22 is coupled to the second end of the circuit switching transistor 621_3. The control end of the scan transistor 621_21 may receive the scan signal Sn. The control end of the reset transistor 621_22 may receive the reset signal RST. The second end of the scan transistor 621_21 and the reset transistor 621_22 is coupled to the impedance circuit 621_4. The impedance circuit 621_4 may include a transistor 621_41. The first end of the transistor 621_41 is coupled to the control end of the transistor 621_41, and is electrically connected with the control end of the circuit connection transistor 621_1 and the second end of the scan transistor 621_21 and the reset transistor 621_22. The second end of the transistor 621_41 is coupled to the ground voltage GND. However, in some embodiments, the impedance circuit 621_4 may also be other types of impedance circuits and not be limited to those shown in
In this embodiment, the circuit connection transistor 621_1, the connection transistors 623_1 to 623_3, the scan transistor 621_21, the reset transistor 621_22, the circuit switching transistor 621_3, the switching transistor 622, and the transistors 621_41, 625_1, 625_2, 626_1 may respectively be P-type thin-film transistors or P-type MOSFETs, but the disclosure is not limited thereto.
With reference to
During the reset period PR from time t1 to time t2, the reset signal RST switches from a high potential voltage to a low potential voltage to turn on the respective reset transistors of the pixel circuits 610_1 to 610_3 and respectively reset the storage capacitors of the pixel circuits 610_1 to 610_3. During the period PS from time t3 to time t4, the scan signal Sn switches from a high potential voltage to a low potential voltage to turn on the respective scan transistors of the pixel circuits 610_1 to 610_3 and respectively write the driving data into the storage capacitors of the pixel circuits 610_1 to 610_3. As shown in the operation states 2 to 3 of Table 1 below, the circuit node N61 maintains a low potential voltage, and the circuit node N62 maintains a high potential voltage to turn off the connection transistors 623_1 to 623_3.
During the driving period P2 between time t5 and time t6, the control signal EM is a low potential voltage to turn on the circuit switching transistor 621_3, the switching transistor 622, and the respective pixel switching transistors of the pixel circuits 610_1 to 610_3. The reset signal RST and the scan signal Sn are respectively high potential voltages to turn off the respective reset transistors and the scan transistors of the pixel circuits 610_1 to 610_3. As shown in the operation state 4 of Table 3 below, the circuit nodes N61 and N62 are high potential voltage, so as to turn off the connection transistors 623_1 to 6233. It should be noted that since the scan transistor 621_21 and the reset transistor 621_22 of the switching circuit 621_2 may also receive the reset signal RST and the scan signal Sn, when signal (voltage) abnormality (a false trigger) of at least one of the reset signal RST and the scan signal Sn occurs, for example, when at least one of the reset signal RST and the scan signal Sn switches from a high potential voltage to a low potential voltage during the driving period P2, then at least one of the scan transistor 621_21 and the reset transistor 621_22 is conducted, and the circuit connection transistor 621_1 is thus conducted as well. As shown in the operation states 5 to 7 of Table 3 below, when signal (voltage) abnormality of at least one of the reset signal RST and the scan signal Sn occurs, the circuit nodes N61 and N62 may respectively switch to a low potential voltage to conduct the connection transistors 623_1 to 623_3. In this regard, the circuit connection transistor 621_1 may provide the reference voltage V1 to the control end of the connection transistors 623_1 to 623_3 through the switching transistor 622 and the circuit nodes N61, N62 to conduct the connection transistors 623_1 to 623_3. Next, the connection transistors 623_1 to 623_3 may respectively provide the protection voltage Vp to the respective driving transistors of the pixel circuits 610_1 to 610_3 to turn off the driving transistors. Therefore, the protection circuit 620 may effectively protect the diode elements in the pixel circuits 610_1 to 610_3 of the pixel 610 and may avoid the voltage signal abnormality of at least one of the reset signal RST and the scan signal Sn from causing the damage to the diode elements in the pixel circuits 610_1 to 610_3, which may thus achieve the current overload protection function of the pixel 610.
In addition, in some embodiments, the switching circuit 621_2 may include only one of the scan transistor 621_21 and the reset transistor 621_22, and when signal (voltage) abnormality of one of the scan signal Sn and the reset signal RST occurs, the protection circuit 620 may conduct the connection transistors 623_1 to 623_3 to turn off the respective driving transistors of the pixel circuits 610_1 to 610_3, which may thus achieve the current overload protection function of the pixel 610.
To sum up, the electronic device of the disclosure may self-detect one of the scan signal and the reset signal of the pixel through the protection circuit coupled to the pixel. When abnormality or a false trigger of one of the scan signal and the reset signal of the pixel occurs, the protection circuit may turn off the abnormal pixel, which may reduce the problem of diode element damage in the pixel caused by short circuit or high current.
Finally, it should be noted that: the above embodiments are only used to illustrate technical solutions of the disclosure and are not intended to limit the disclosure. Although the disclosure has been described in detail with reference to the above embodiments, people of ordinary skill in the art should understand that they may still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents, and such modifications or replacements of corresponding technical solutions do not substantially deviate from the scope of the technical solutions of the embodiments of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210018344.X | Jan 2022 | CN | national |
This application claims the priority benefits of U.S. provisional application Ser. No. 63/192,574, filed on May 25, 2021, and China application serial no. 202210018344.X, filed on Jan. 7, 2022. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
| Number | Date | Country | |
|---|---|---|---|
| 63192574 | May 2021 | US |
