Claims
- 1. An electronic device comprising:
- input means for entering coordinate information;
- a processing means for processing the coordinate information from said input means;
- detecting means for detecting coordinate information from said input means;
- clock signal generating means for generating a clock signal for operating said processing means, said clock signal generating means generating a first clock signal for operating said processing means and a second clock signal for maintaining low power consumption by said processing means, said second clock signal having a frequency different from that of the first clock signal; and
- control means for entering information from said detecting means at a constant common period based on the first clock signal and the second clock signal from said clock signal generating means, said control means having a frequency division factor greater for said first clock signal as compared with that for said second clock signal.
- 2. An electronic device according to claim 1 wherein said coordinate input means includes indication means for entering the coordinate information.
- 3. An electronic device according to claim 1 wherein said control means includes a counter for altering the frequency of the operating clock.
- 4. An electronic device comprising:
- input means for entering coordinate information;
- processing means for processing the coordinate information from said input means;
- detecting means for detecting the coordinate information from said input means;
- clock signal generating means for generating a clock signal for operating said processing means, said clock signal generating means generating a first clock signal for operating said processing means, and a second clock signal for maintaining low power consumption by said processing means, said second clock signal having a frequency different from that of the first clock signal;
- first control means for entering information from said detecting means at a constant common period based on the first clock signal and the second clock signal from said clock signal generating means, said control means having a frequency division factor greater for said first clock signal as compared with that for said second clock signal; and
- second control means, after elapse of a predetermined time since the clock signal generating means generates the first clock signal, for causing the clock signal generating means to generate the second clock signal.
- 5. An electronic device according to claim 4 wherein said input means includes means for entering coordinate information.
- 6. An electronic device according to claim 4 wherein said input means includes indication means for entering coordinates.
- 7. An electronic device according to claim 4 wherein said second control means has a counter for altering the frequency of the operating clock.
- 8. An electronic device according to claim 4 wherein said input means enters hand-written information.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2-312641 |
Nov 1990 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/790,435, filed Nov. 12, 1991, now abandoned.
US Referenced Citations (4)
Foreign Referenced Citations (4)
Number |
Date |
Country |
0050844 |
May 1982 |
EPX |
0391543 |
Oct 1990 |
EPX |
60-198619 |
Oct 1985 |
JPX |
2024712 |
Jan 1990 |
JPX |
Non-Patent Literature Citations (2)
Entry |
"System Power Savings By Automatic Sleep Mode", IBM Technical Disclosure Bulletin, vol. 29, No. 9, Feb. 1987, pp. 4122-4124. |
"Cursor Controller/Graphics Pad", IBM Technical Disclosure Bulletin, vol. 28, No. 9, Feb. 1986, pp. 4093-4097. |
Continuations (1)
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Number |
Date |
Country |
Parent |
790435 |
Nov 1991 |
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