Patent Application
20080298801
Not applicable.
A test has been developed that is known as the transmitter waveform dispersion penalty (TWDP) test. The TWDP test has been used to test and certify various optical data transmission devices, such as optoelectronic transceivers and calibrated stressed eye generators, for example. In fact, the TWDP test has been used as an industry standard requirement, such as in IEEE 802.3, for certifying certain products.
The TWDP penalty is defined as the difference (in dB) between a reference signal to noise ratio (SNR) and the equivalent SNR at the slicer input of a reference decision feedback equalizer (DFE) receiver for the measured waveform after propagation through a simulated fiber channel. The reference SNR is the SNR of an ideal channel with a matched filter receiver. For the ideal channel, rectangular on-off keyed pulses are transmitted, and the transmitter and fiber are assumed perfect. The received pulse is a rectangular pulse with an amplitude measured in Optical Modulation Amplitude (OMA). The output of the matched filter is sampled once per binary digit (bit) unit interval (without timing error) and presented to the decision element (binary slicer).
The TWDP test involves the use of a computer model having an input as the captured optical transmit waveform. The model for TWDP calculation is illustrated in
Measuring the TWDP involves capturing a transmitter waveform and processing it using software, including the TWDP algorithm, to calculate the penalty of that waveform on a reference equalizer. The model uses one or more fiber models, assumptions about the receiver noise, and a model of a decision feedback equalizer with a large number of taps (to approximate an ideal infinite equalizer) to calculate the excess power needed to achieve the same BER as the BER of a link with an ideal transmitter signal and perfect fiber response. This calculated penalty should, in turn, correspond to the penalty of an ideal decision feedback equalizer (PIE-D) of the resulting received signal through the actual link.
The test pattern used to generate the transmitted sequence by the device under test is a pseudo-random binary sequence (PRBS) data pattern generated via a maximal length 9th order binary polynomial (PRBS9). The PRBS9 test pattern begins with a run of nine ones and has a length of 511 bits as the last 0 bit of the pattern is appended. This PRBS9 test pattern is generated by a device called a pattern generator which can be quite expensive. For example, a compliant pattern generator, such as the Advantest Pulse Pattern Generator Model D3186, can cost as much as $95,000 U.S. dollars or more. Thus, frequent use of a pattern generator may be cost prohibitive in some instances.
The transmitted sequence must be sampled several times per bit period to capture an accurate waveform. Moreover, the waveform is typically repetitively captured using averaging to avoid a pessimistic estimate of the TWDP. For example, an effective sample rate of at least 7 samples per bit period is typically required. However, interpolation is typically necessary for a waveform not captured with at least 16 samples per bit period. As a result, a high sample rate and/or additional post processing are also required. This post processing may also be cumbersome at least due in part to the length of the PRBS9 test pattern.
The PRBS9 test pattern used to generate the transmitted reference sequence must also be aligned with the captured waveform. For example, although the bit period of the captured waveform is highly accurate, compensation for mismatch on the order of a small fraction of a percent between the transmitted sequence and the captured waveform must be performed. This calibration of the transmitted reference sequence and the captured waveform can be quite time consuming at least due in part to the length of the PRBS9 test pattern sequence and the required number of samples per bit period. For example, in one trial an error in timing calibration of 0.024% was determined to be unsatisfactory.
Similar tests are being developed to test optical receivers. For example, a difference waveform distortion penalty (dWDP) has been proposed for testing SFP type transceivers. dWDP uses the same procedure and code as defined by TWDP in clause IEEE 802.3 clause 68.6.6 with consideration of a few comments. For example, dWDP does not use the three emulated reference multi-mode fibers in the TWDP MATLAB code. The three emulated fibers (the last three rows in FiberResp) are replaced with a single identity channel [0 1 0 0], and therefore, only one penalty value is calculated for each measurement (only one pass of the ii loop). Additional distinctions and explanation of the dWDP test is explained in “SFF-8431 Specifications for Enhanced 8.5 and 10 Gigabit Small Form Factor Pluggable Module ‘SFP+’”, Revision 2.0 (26 Apr. 2007), available at ftp://ftp.seagate.com/sff/SFF-8431.PDF, the contents of which are hereby incorporated by reference.
A method of testing an optoelectronic device is disclosed. The method includes receiving an electrical test pattern of between about 8 and about 254 bits. The method further includes converting the electrical test pattern to an optical waveform and sampling the optical waveform. The method further includes calculating a penalty. The penalty calculation is associated with a difference in decibels between a reference SNR and an equivalent SNR for the sampled waveform after propagation through a simulated fiber channel.
A system is disclosed that includes a pattern generator configured to generate an electrical test pattern. The system further includes an optical transmitter within the optoelectronic device. The optical transmitter is configured receive an electrical test pattern and convert the electrical test pattern to an optical waveform. The system further includes a sampling device configured to sample the optical waveform and a data processing device configured to calculate a penalty. The penalty calculation is associated with a difference in decibels between a reference SNR and an equivalent SNR for the sampled waveform after propagation through a simulated fiber channel.
An optoelectronic device is also disclosed. The optoelectronic device includes an optical transmitter, a pattern generator coupled to the optical transmitter, and a housing containing at least the optical transmitter and the pattern generator. The pattern generator is configured to generate a test pattern of between about 8 and 254 binary digits (bits) and transmit the test pattern to the optical transmitter.
These and other aspects of the present invention will become more fully apparent from the following description and appended claims.
To further clarify the above and other aspects of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
As described above, a TP-2 test methodology has been developed for determining compliance with 10GBASE-LRM specifications. In this conventional test, a measured waveform from a device under test (DUT) is captured with a sampling oscilloscope and the data sequence driving the DUT is a PRBS9 or similar test pattern. According to the teachings herein, a test pattern shorter than the PRBS9 test pattern is used to determine whether the DUT is in compliance with a specification.
Using the shortened test pattern for TDWP testing according to the teachings herein may introduce several advantages over the industry standard method. For example, the cost of the pattern generator may be reduced in some instances due to the shorted test pattern. The pattern generator may also be a less complicated device. As such, the pattern generator may be disposed internal to the DUT and included within the final product. As such, a separate external pattern generator would not be required in such embodiments. Moreover, in some embodiments, circuitry already included within a product may be simply reprogrammed so as to generate the test pattern without requiring additional hardware.
In addition, as discussed above, the test pattern used to generate the transmitted sequence must be aligned with the captured waveform. It follows that the alignment of a shorter transmitted sequence with the captured waveform may be accomplished in less time than a longer transmitted sequence. Thus, setup, calibration, and time spent performing post-processing may be drastically reduced, particularly so where the transmitted sequence is a small fraction of the length of the standard PRBS9 sequence.
In some instances, the bit pattern of the shortened test pattern may also be designed as an pre-certification test so as to provide a good indication of whether the DUT would subsequently also satisfy the standard TDWP test using the PRBS9 test pattern. The test pattern may be designed so as to provide a sequence of bits most likely to cause a DUT to fail a TDWP certification test. Thus, the bit pattern can be designed to introduce error in a test pattern including a shorter length of bits. As such, the shortened TDWP test pattern can give a reliable pre-final assembly and test indication of whether the DUT will fail the industry standard test.
Referring to
The TWDP calculation device 215 may include a conventional computer or other data processing device. The TWDP calculation includes processing the waveform generated by the optoelectronic device 200 sampled using software, including the TWDP algorithm, to calculate the penalty of that waveform on a reference equalizer as discussed above. The penalty calculated can characterize an optical transmitter or an optical receiver within the optoelectronic device 200. Three fiber channels can be simulated, each fiber channel corresponding to a defined stressor. A penalty for each of the three simulated fiber channels may be calculated and a maximum penalty of the penalties calculated is identified. The penalty(s) are compared to a penalty threshold to determine whether the optoelectronic device is compliant. The penalty threshold may be determined by an industry standard, such as a 10GBASE-LRM specification.
The pattern generator 205 is configured to generate an electrical test pattern that is less than the 511 bits long. In one embodiment, the test pattern is between about 8 and 254 bits. In another embodiment, the pattern generator is configured to generate an electrical test pattern that is between about 10 and 64 bits. According to another embodiment, the pattern generator is configured to generate an electrical test pattern that is about 32 bits or less. The test pattern maybe transmitted at speeds of between about 8 and about 10 gigabits per second (Gbps), for example. However, the teachings disclosed herein are applicable to testing conducted at speeds higher than 10 Gbps and less than 8 Gbps. Thus, in this embodiment the pattern generator 205 is located external to the optoelectronic device under test 200.
Referring to
For example, the TOSA 305 can include an optical transmitter in the form of a light emitting diode (LED) or a laser diode located on a header for transmitting an optical signal to an optical fiber. A plastic barrel can be used to align and couple the optical signal transmission from the optical transmitter with the end of a fiber optic cable. Similarly, the ROSA 310 can include an optical receiver in the form of a PIN photodiode or avalanche photodiode (“APD”), located on a header. A plastic barrel can be used to align and couple the end of a fiber optic cable for transmission of the optical signal from a fiber optic cable to the optical receiver. Thus, testing of the optical transmitter and/or the optical receiver of the fiber optic transceiver using the shortened test pattern may, in some embodiments, help to determine whether the transceiver will subsequently satisfy a TWDP or dWDP requirement.
Referring to
In another embodiment, the circuitry is configured to provide additional testing functionality for the optoelectronic device 400. For example, the circuitry may have the dual function of generating the test pattern for TWDP or dWDP testing along with the function of generating a different test pattern for another industry standard test, such as any of the tests requiring test patterns disclosed in IEEE 802.3 or other industry standard.
Referring to
The fiber optic transceiver 500 can be any type of fiber optic transceiver. For example, the fiber optic transceiver 500 can be a small form-factor pluggable (SFP), SFP+, a small form-factor (SFF), a 10 gigabit small form factor pluggable (XFP), ZENPAK, XPAK, gigabit Ethernet, GBIC, or other type of fiber optic transceiver.
Referring to
Testing has also revealed that isolated bits adjacent to long runs of the opposite bit value tend to introduce error. Therefore, the test pattern in
In some instances an optoelectronic device maybe more sensitive to a test pattern associated with a large digital sum variation (DSV). Therefore, one manner in which the design of a test pattern may be evaluated is by comparison of a DSV for different test patterns. For example, referring to
The method further includes converting the electrical test pattern to an optical waveform (805). The method further includes sampling the optical waveform (810). The method further includes calculating a penalty (815). The penalty calculation is associated with a difference in decibels between a reference SNR and an equivalent SNR for the sampled waveform after propagation through a simulated fiber channel. For example, the penalty calculation can include the TWDP test algorithm specified in IEEE 802.3-2005, Clause 68. The penalty calculation can include simulating three fiber channels, each fiber channel corresponding to a defined stressor, calculating a penalty for each of the three simulated fiber channels, and identifying a maximum penalty of the penalties calculated.
In one embodiment, the method of
It should be understood that the drawings are diagrammatic and schematic representations of such example embodiments and, accordingly, are not limiting of the scope of the present invention, nor are the drawings necessarily drawn to scale. The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope. Detailed descriptions of apparatus and processing techniques known in the field of the invention to one of ordinary skill in the art have been excluded.
