Electronic function module for generating a current which any rational power of another current

Description

The present invention relates to an electronic function module for generating a current with a predetermined relationship to another current.

More particularly, the invention seeks to provide a function module for implementing the relationship:

y=c

k/j

in which x represents a first current, y represents a second current and k and j are two integers whose ratio defines the exponent of the value x. As a result the function module according to the invention will be able on the basis of a first current x, to generate another current y, which can be any rational power of the first current.

A function module of this type has been described in an article by X. Arreguit, E. A. Vittoz and M. Merz, published in IEEE Journal of Solid State Circuits, Vol. SC-22, No. 3, June 1987, especially intended for incorporation in a data compressor applied to a hearing aid.

FIG. 4

of this article shows an embodiment of such a function module in which compatible bipolar transistors (or compatible planar bipolar transistors in CMOS technology) are used to establish the relationship between the two currents. The exponent of the value of the first current is determined by a resistive component and it is proposed to vary its value to enable a variable exponent value to be obtained. More particularly, a bank of resistors in series is provided and the resistors can be selectively connected in circuit with the aid of MOS selection transistors.

The known function module suffers from the disadvantage of requiring not only compatible bipolar transistors but also resistance components, which are poorly compatible with recent technologies for making exclusively CMOS circuits devoid of any resistance components. Moreover, applications of such a function module are limited, on the one hand because the value of the variable exponent has to lie between 0 and 1 and on the other band because of the various precautions which have to be taken to observe the characteristics of compatible bipolar transistors. The object of the invention is to provide a function module of the type briefly specified above but which does not have the disadvantages of the prior art. In particular the function module according the invention is perfectly adapted to modem technologies for implementing CMOS circuits and does not comprise any components other than MOS transistors.

The invention thus provides an electronic function module comprising a series of sections (C

1

, C

2

, . . . , C

j

, . . . ) enabling the generation of a second current having a relationship to at least one first, current of the type y=x

i

, where x represents the value of the first current, y represents the value of the second current and i the order of the section in said series, characterized in that each section C

j

comprises:

a pseudo-conductance G*j connected between a supply voltage (V*

in

) and a pseudon-grounded (

7

) and generating an output current (I

j

);

a control transistor (T

j

) passing the output current I

j−1

of the preceding section C

j−1

and adapted to control said pseudo-conductance G*

j

in such a manner that said output current I

j

is proportional to the current I

j−1

of the preceding section C

j−1

; and

a current conveyor (T

3

, T

5

, T

6

) for passing said output current I

j

on the one hand to said control transistor of the following section C

j+1

and on the other hand to an output of the section C

j

;

and in that the current passing through the control transistor of the first section C

1

of said series is a fixed current (I

0

), such that the output current I

j

of any section C

j

of the series is proportional to I

0

j

.

The invention also provides a function module comprising a series of sections whose characteristics are as specified above and enabling the generation of a second current which has a relationship to a first current of the type y=x

k/j

, where x represents the value of the first current, y represents the value of the second current and k and j are the orders of the sections C

k

and C

j

respectively, characterized in that it further comprises a close loop control circuit (T

l

) supplying said supply voltage (V*

in

) on the basis of an arbitrarily selected input current (I

in

) and the output current (I

j

) of any section C

j

of said series, such that the currents I

in

and I

l

are kept equal, so that the output current T

k

of a section C

k

is such that I

k

=I

in

k/j

.

By virtue of these characteristics it will be possible to draw a current y from a given section in said network which will be a given rational power of the current output in another section, the power being determined by the ratio between the orders occupied by these sections in the network.

The function module according to the invention thus provides a large choice of current values having the desired power relationship between them, easily obtained by simply making connections.

Furthermore, it is found that the function module can be realized entirely according to CMOS technology, without the need for any resistive components.

The function module according to the invention can also have one or more of the following characteristics:

the closed-loop control circuit is formed by a single MOS transistor which provides a supply voltage for the pseudo-conductances with a value such as to ensure equality between an output current of a selected section and a given input current;

the pseudo-conductances are each formed by an MOS transistor biased so as to operate in a state of weak inversion;

the current conveyors are formed with the aid of current mirrors with two outputs.

Other features and advantages of the invention will appear in the course of the following description, given solely by way of example and with reference to the accompanying drawings, in which;

FIG. 1

is a first diagram showing the principle of operation of the function module according to the invention:

FIG. 2

shows a variant of the diagram according to

FIG. 1

;

FIG. 3

is an example of implementation in CMOS technology of a variable pseudo-conductance;

FIG. 4

represents one section of the circuit of the invention; and

FIG. 5

shows an embodiment of a function module according to the invention.

FIG. 1

shows is a first diagram of the principle of the invention. It comprises a network of conductances G*

1

to G*

N

, connected in parallel between a supply line

2

, carrying the voltage V*

in

, and ground

3

. The reason for the asterisks applied to certain references will be explained with reference to the following figures of the description. The conductance G*

1

is a fixed conductance, while the conductances G*

2

to G*

N

of the network are variable conductances (as indicated by the arrows through them), each variable conductance being so controlled that its value is proportion to the current passing through the preceding conductance. Thus G*

2

is proportional I

1

, G*

3

is proportional to I

2

, . . . , G*

N

is proportional to I

N−1

. Thus for the network of

FIG. 1

we can write:

I

1

=G*

1

.V*

in

G*

2

=(G*

1

.V

in

)/V*

0

where 1/V*

0

represents a constant of proportionality

I

2

=G*

2

.V*

in

=G*

1

.(V*

in

)

2

/V*

0

G*

2

=(G*

2

.V*

in

)/V*

0

=G*

1

.(V*

in

)

2

/V*

0

2

I

3

=G*

3

.V*

in

=G*

1

.(V*

in

)

3

/V*

0

2

etc.,

From the above it can be concluded that I

2

is proportional to I

1

3

, I

3

is proportional to I

1

3

, . . . , I

N

is proportional to I

1

n

. Thus for the network of

FIG. 1

, each branch k is traversed by a currentI

k

which is proportional to the k

th power of I

1

. The input voltage V*

in

can be adjusted so that the current I

1

will be equal to a reference value. The currents I

j

, . . . , I

k

can be drawn from the network by current conveyors. With the proposed use of pseudo-conductances in CMOS technology, as will be seen below, the extraction of the output currents can be effected by means of simple current mirrors.

The diagram of

FIG. 2

shows a variant of

FIG. 1

, according to which the input voltage V*

in

is such that the current in a given branch j (j=3 here) is equal to a fixed input current I

in

. For this purpose a current generator

4

supplying the current I

in

is connected in series with the conductance G*

3

which is traversed by the current I

3

between the supply

2

and ground

3

. The node

6

common to the current generator

4

and the conductance G*

3

is connected to the inverting input (−) of an operational amplifier

5

, whose other input (+) is grounded. The voltage V*

in

at the output of the amplifier

5

is applied to the supply terminal

2

of the network and is thus such as to ensure equality between the current I

3

and I

in

. According to the arrangement of

FIG. 2

it is thus possible to fix the value of the current in any branch of the network and the following relationships obtain:

I

1

is proportional to V*

in

I

2

is proportional to I

1

2

I

3

is proportional to I

1

3

from which it follows that I

1

is proportional to (I

in

)

1/3

.

Thus, by ensuring that the current I

j

is equal to a given input current I

in

, the current I

k

in the branch k is given by:

I

k

is proportional to (I

in

)

k/j

.

Reference is made for the description which follows to an article of E. A. Vittoz and X. Arreguit with the title “Linear networks based on transistors”, appearing in Electronics Letters of 4 February 1993, Vol. 29. No. 3, pp. 297-298. This article describes in particular the principle of pseudo-conductance and defines pseudo-voltages. As in the article, the use in the present description of an asterisk applied to a reference makes it possible to recognize the pseudo-conductances G* and the pseudo-voltages V*.

FIG. 3

shows an example of a variable pseudo-conductance in CMOS type technology. The variable conductance G* is formed by a p-type MOS transistor operating in weak inversion, with its gate connected to the gate of a control transistor T, likewise of p-type and operating in weak inversion, with its drain at a fixed voltage F

F

, its source connected to its gate and whose channel current is I.

A description of the characteristics of MOS transistors operating in weak inversion can be found in the article by E. A. Vittoz and J. Fellrath, entitled “CMOS analog integrated circuits based on weak inversion operation” appearing in Journal of Solid State Circuits, Vol. SC-12, June 1977, pp. 224-231.

If the voltage on the terminal

7

of the transistor G* is sufficiently low relative to its gate voltage, the transistor G* is in the saturated state and the terminal

7

can be considered to be a pseudo-ground (see the article by E. A. Vittoz and X. Arreguit cited above). The transistor G* then behaves as a conductance to ground and we can write:

G*=1/V*

0

,

where V*

0

represents a coefficient with an arbitrary value.

FIG. 4

shows tie complete circuit of one section j of a network or function module according to the invention. The transistor acting as the variable pseudo-conductance G* is seen, connected between the input voltage V*

in

, and the pseudo-ground

7

, also the control transistor T

j

, connected to a fixed voltage V

F

and supplied by a current I

j−1

. This current I

j−1

is drawn from the preceding section by way of a current mirror formed by transistors M

1

and M

2

, both of n-type. The transistor M

2

is connected in series with the transistor T

j

between the fixed voltage V

F

and ground

3

and the transistor M

1

connected as a diode is connected between the terminal

8

and ground with its gate connected to that of M

2

. The current mirror in MOS technology is well known in the literature. If the transistors M

1

and M

2

have identical dimensions (same value of the ratio of the width W to the length L of their channels) and are located very close to one another on the same substrate, they carry the same channel current. It is appropriate to note however that the ratio of the currents may be made other than unity by modifying the dimensional ratio W/L of one of the two mirror transistor relative to the other. The output terminal

7

of the section j forms the input terminal of the following section j+

1

. Equally the input terminal

8

of the section j forms the output terminal of the preceding section j−

1

.

The complete circuit of the network or function module of the invention is shown in FIG.

5

. It is formed by an assembly of sections C

1

, C

2

, . . . , C

j

, . . . The sections are all identical. They comprise, with reference to the section C

j

a p-type transistor which forms the variable pseudo-conductance G*

j

, a control transistor T

j

for this pseudo-conductance and a current mirror formed by a first transistor T

5

connected as a diode and of n-type and two output transistors T

3

and T

6

, also of n-type. The first transistor T

3

allows the current I

j

passing through the pseudo-conductance G*

j

to be applied to the control transistor (analogous to the transistor T

j

) of the following section C

j+1

. In like manner, the control transistor T

j

of the section C

j

receives the current I

j−1

of the preceding section C

j−1

through in output transistor (analogous to the transistor T

6

) of the current mirror of the preceding section C

j−1

. The output transistor T

3

allows the current I

j

of the section C

j

to be extracted if it is to serve in the closed loop control described above. The transistor T

j

is connected in series with the output transistor (analogous to T

6

) of the current mirror of the preceding section C

j−1

, between a fixed positive voltage V+ and a fixed negative voltage (or ground) V−. The transistor forming the variable conductance G*

j

is connected in series with the transistor T

5

between the input voltage V*

in

and ground. This input voltage V*

in

is generated by the transistor T

1

, whose n-type channel is connected between a supply voltage V

alim

and the supply line

1

for V*

in

. The gate

5

of the transistor T

1

receives an input current I

in

as well as the output current I

j

of the selected section. The transistor T

1

operates as a voltage follower; it provides the line

1

with a voltage V*

in

which is such as ensure equality between the input current I

in

and the current I

j

of the selected section. The voltage V

alim

is a fixed supply voltage whose value should be sufficiently above the voltage V+ to ensure correct operation of the network. Connector means (not shown) allow connection of any output current C

j

to the gate

5

of the transistor T

1

. The section C

1

differs from the other sections of the network only in that the current I

0

supplied to the control transistor (analogous to the transistor T

j

of the section C

j

) is generated by a current source

4

connected in series with the said control transistor.

It should be noted that, although CMOS technology is preferred for implementing the function module according to the invention, the man skilled in the art will recognize that It can equally be implemented with the aid of bipolar transistors.

Claims

1. An electronic function module comprising a series of sections (C1, C2, . . . , Cj, . . . ) enabling the generation of a second current having a relationship to at least one first current of the type y=xi, where x represents the value of the first current, y represents the value of the second current and i is the order of the section in said series, characterized in that each section Cj comprises:a pseudo-conductance G*j connected between a supply voltage (V*in) and a pseudo-ground (7) and generating an output current (Ij); a control transistor (Tj) passing the output current Ij−1 of the preceding section Cj−1 and adapted to control said pseudo-conductance G*j in such a manner that said output current Ij is proportional to the current Ij−1, of the preceding section Cj−1; a current conveyor (T3, T5, T6) for passing said output current Ij on the one hand to said control transistor of the following section Cj+1 and on the other hand to an output of the section Cj; and in that the current passing through the control transistor of the first section C1 of said series is a fixed current (I0), such that the output current Ij of any section Cj of the series is proportional to I0j; said series of sections enabling the generation of a second current which has a relationship to a first current of the type y=xk/j, where x represents the value of the first current, y represents the value of the second current and k and j are the orders of the sections Ck and Cj respectively, characterized in that the function module further comprises a closed-loop control circuit (Ti) supplying said supply voltage (V*in) on the basis of an arbitrarily selected input current (Iin) and the output current (Ij) of any section Cj of said series, such that the currents Iin, and I1, are kept equal, so that the output current Ik of a section Ck is such that Ik=Iink/j.
2. An electronic function module comprising a series of sections (C1, C2, . . . , Cj, . . . ) enabling the generation of a second current having a relationship to at least one first current of the type y=xi, where x represents the value of the first current, y represents the value of the second current and i is the order of the section in said series, characterized in that each section Cj comprises:a pseudo-conductance G*j connected between a supply voltage (V*in) and a pseudo-ground (7) and generating an output current (Ij); a control transistor (Tjpassing the output current Ij−1 of the preceding section Cj−1 and adapted to control said pseudo-conductance G*j in such a manner that said output current Ij is proportional to the current Cj−1 of the preceding section Cj−1; a current conveyor (T3, T5, T6) for passing said output current Ij on the one hand to said control transistor of the following section Cj+1 and on the other hand to an output of the section Cj; and in that the current passing through the control transistor of the first section C1 of said series is a fixed current (I0), such that the output current Ij of any section Cj of the series is proportional to I0j; said series of sections enabling the generation of a second current which has a relationship to a first current of the type y=xk/j where x represents the value of the first current, y represents the value of the second current and k and j are the orders of the sections Ck and Cj respectively, characterized in that the function module further comprises a closed-loop control circuit (Ti) supplying said supply voltage (V*in) on the basis of an arbitrarily selected input current (Iin) and the output current (Ij) of any section Cj of said series, such that the currents Iin and I1 are kept equal, so that the output current Ik of a section Ck is such that Ik=Iink/j; wherein said control circuit is formed by a MOS transistor (T1) whose gate is connected to a node (5) receiving said input current (Iin) and from which said any output current (Ij) is drawn and whose channel is connected between a fixed supply voltage (Valim) and the supply node (V*in) of all the pseudo-conductances; said MOS transistor acting as a voltage follower.

Priority Claims (1)

Number	Date	Country	Kind
0399/99	Mar 1999	CH

US Referenced Citations (2)

Number	Name	Date	Kind
5757175	Morishita et al.	May 1998	A
5939933	Wang	Aug 1999	A

Non-Patent Literature Citations (3)

Entry
Arreguit X et al. “Precision compressor gain controller CMOS technology”, Twelth European Solid-State Circuits Conference, Delft, Netherlands, Sep. 16-18, 1986, vol. SC-22, No. 3, pp. 442-445, XP002114419.
Bult K. et al.: “A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation”, IEEE Journal of Solid-State Circuits, vol. SC-22, NR. 3, pp. 357-365 XP000035405, Jun. 1987.
Vittoz, E. A., “Pseudo-Resistive Networks and Their Applications to Analog Collective Computation”, Proceedings MicroNeuro '97, Dresden, pp. 163-173.

Electronic function module for generating a current which any rational power of another current

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

Priority Claims (1)

US Referenced Citations (2)

Non-Patent Literature Citations (3)