Patent Application
20130091322
This application claims the benefit of Taiwan application Serial No. 100136362, filed Oct. 6, 2011, the subject matter of which is incorporated herein by reference.
1. Field of the Invention
The invention relates in general to a flash memory, and more particularly, to a technique for logical/physical address mapping relationship mapping management of a flash memory.
2. Description of the Related Art
Flash memory has the advantaged of having large capacity, low cost and fast access speed, and thus prevails in various consumer electronic products. Apart from storing user data, flash memory is also commonly utilized for storing software data and programs that occupy large amounts of memory space, such as operating systems. The lifespan of flash memory is largely dependable on the frequency of use; frequent writing and erasing of a certain blocks in the flash memory shorten the lifespan of or even damage those blocks, and further jeopardize the use of the overall flash memory.
To evenly prolong the lifespan of the blocks in flash memory, a translation layer is introduced into firmware of the flash memory. The translation layer functions to evenly distribute the utilization frequencies of the blocks in the flash memory. In general, when an application program wishes to read from/write to the flash memory, rather than directly driving the flash memory, a logical address of a desired block is first converted to a physical address via the translation layer in order to correctly find the block. Hence, how to establish and maintain a correct logical/physical address mapping table is closely related to execution efficiency of the above translation layer.
Each of the blocks of the flash memory is usually recorded with its logical/physical address mapping relationship. In other words, the relationships are distributed and stored in different blocks of the flash memory. It should be noted that, the relationships vary. In current techniques, in an initialization procedure each time an electronic system is booted or reset, firmware in the flash memory scans all of the blocks to read the latest logical/physical mapping relationships of the blocks, and rebuilds in an auxiliary memory of the electronic system a logical/physical address mapping table that is to be subsequently used by a translation layer.
However, a major drawback of the current techniques is that, the process of scanning all of the blocks is quite time-consuming. As the capacity of flash memory increases along with the advancement of manufacturing processes, time for rebuilding the mapping table is also significantly increased which can severely affect system performance.
An embodiment of the invention is directed to a novel memory control solution. By establishing a storage region in a flash memory and centralizing storing logical/physical address mapping relationships of all blocks of the flash memory, the memory control solution of the present invention is capable of effectively shortening the time needed for rebuilding an address mapping table in an auxiliary memory of an electronic system, thereby optimizing overall efficiency of the electronic system.
According to an embodiment of the present invention, a memory managing method for an electronic system is provided. The electronic system comprises an auxiliary memory, and is capable of communication with a flash memory comprising a plurality of blocks. Each of the blocks comprises a logical/physical address mapping relationship. The logical/physical address mapping relationships are stored in a storage region in the flash memory. The method comprises steps of: a) determining whether the logical/physical address mapping relationships stored in the storage region are correct; and b) reproducing the logical/physical address mapping relationships from the storage region to the auxiliary memory for reference of the electronic system when the electronic system communicates with the flash memory when a determination result from Step (a) is affirmative.
According to an embodiment of the present invention, a computer-readable storage medium stored with a code readable and executable by an electronic system is provided. The electronic system comprises an auxiliary memory, and is capable of communicating with a flash memory comprising a plurality of blocks. Each of the blocks comprises a logical/physical address mapping relationship. The logical/physical address mapping relationships are stored in a storage region in the flash memory. The code is for managing the flash memory, and comprises: a first sub-code, for determining whether the logical/physical address mapping relationships stored in the storage region are correct; and a second sub-code, for reproducing the logical/physical address mapping relationships from the storage region to the auxiliary memory for reference of the electronic system when the electronic system communicates with the flash memory when a determination result of the first sub-code is affirmative.
According to an embodiment of the present invention, an electronic system comprising an auxiliary memory and a controller is provided. The electronic system is capable of communicating with a flash memory comprising a plurality of blocks. Each of the blocks comprises a logical/physical address mapping relationship. The logical/physical address mapping relationships are stored in a storage region in the flash memory. When the flash memory is coupled to the electronic system, the controller respectively couples to the auxiliary memory and the flash memory. In an initialization procedure of the electronic system, the controller first determines whether the logical/physical address mapping relationships stored in the storage region are correct, and copies the logical/physical address mapping relationships from the storage region to the auxiliary memory for reference of the electronic system when the electronic system communicates with the flash memory.
The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
According to an embodiment of the present invention, a memory managing method for an electronic system is provided. The memory managing method of the present invention is capable of optimizing efficiency of the electronic system in building an address mapping table for a flash memory. For example, the electronic system is a digital camera, a mobile communication system, a portable computer, a desktop computer or external storage devices adopting a flash memory. The concept of the present invention is applicable to both a NAND flash memory and a NOR flash memory. In practice, the flash memory may be directly built in the electronic system, or may be a memory card or a portable disk connected to the electronic system via various connection devices.
The flash memory comprises a plurality of blocks, each corresponding to a logical/physical mapping relationship. Taking an unsorted block image file system (UBIFS) specification for a Linux system as an example, the logical/physical address mapping relationships of the blocks are recorded in EC/Vid headers of the blocks, respectively. Each of the blocks comprises a plurality of same-sized pages, and the EC/Vid header is located at the first two pages of the blocks. According to an embodiment of the present invention, in the flash memory, a specific storage region is provided for further centralized storing of a copy of the logical/physical address mapping relationships of the blocks. For example, the address mapping relationship information may be stored as a look-up table. To distinguish the specific storage region from other memory regions, the storage region is denoted as a table storage region in the descriptions below.
In practice, the table storage region may be located in one block or distributed in several blocks of the flash memory, and the logical/physical address mapping relationships may be stored in one page or several pages of the one block or the several blocks. A capacity of the table storage region is associated with a number and a content size of the logical/physical address mapping relationships. Taking the UBIFS specification as an example, the size of the EC/Vid header of each block is 128 bytes, and thus a 2048-byte page is capable of storing logical/physical address mapping relationships of 16 blocks. In other words, the capacity of the table storage region must get larger as the number of blocks of the flash memory increases in order to store compact logical/physical address mapping relationships of the blocks of the flash memory.
Tasks of establishing the table storage region and reproducing the logical/physical address mapping relationships from the blocks to the table storage region may be completed with assistance of memory managing firmware of the electronic system when the flash memory is used for the first time after the electronic system is initialized. It should be noted that, the logic/physical address mapping relationships may vary when the memory is in use. Apart from the pages stored with the most updated address mapping relationship information, the table storage region may also comprise other backup storage pages as substitutive pages saved for further address mapping relationship information updates, so as to prevent certain pages from excessive repeated use. For example, the number of pages storing the latest address mapping relationship information may be 10, and the table storage region may comprise 10 or 20 backup storage pages.
The electronic system implementing the memory managing method according to an embodiment of the present invention furthur comprises an auxiliary memory, e.g., a random-access memory (RAM). During an initialization procedure when the electronic system is booted or reset, the logical/physical address mapping relationship information in the blocks of the flash memory is copied to the auxiliary memory, as a reference to the electronic system when the electronic system communicates with the flash memory later.
When a determination result from Step S21 is affirmative, Step S22 is performed to reproduce the logical/physical address mapping relationships from the table storage region 12 to the auxiliary memory as a reference to the electronic system when the electronic system communicates with the flash memory. Conversely, when the determination result from Step S21 is negative, Step S23 is performed to scan the blocks 14 to confirm the logical/physical address mapping relationships of the blocks 14. Next, Step S24 comprises storing the logical/physical address mapping relationships obtained from Step S23 to the auxiliary memory as a reference to the electronic system when the electronic system communicates with the flash memory.
It is seen from the above descriptions that, the address mapping relationship information that is centralized stored in the table storage region 12 may be directly copied to the auxiliary memory of the electronic system when the logical/physical address mapping relationships stored in the table storage region 12 are valid, so as to eliminate the procedure of re-scanning all the blocks 14. Compared to the conventional approach of having to re-scan all the blocks 14 every time, the method of the present invention effectively reduces the time required for rebuilding the address mapping table in the auxiliary memory of the electronic system.
Referring to
Assume that the page validity location bitmap 16A is a binary bitmap, for example, the page validity location bitmap 16A is a binary sequence [10100100100 . . . ], with each of the bits corresponding to a storage page 12A or a backup storage page 12B. In this embodiment, a bit 1 corresponds to a valid page (i.e., the storage page 12A), whereas a bit 0 corresponds to an invalid page (i.e., a backup storage page 12B). The bits in the sequence respectively correspond to each of the storage pages 12A and each of the backup storage pages 12B in the table storage region 12. Assuming that the order of the bits in the sequence corresponds to the order of the pages in the table storage region, locations of the storage pages 12A in the table storage region 12 may be identified from the sequence.
In practice, the page validity location bitmap 16A may be established with assistance of memory managing firmware of the electronic system when the flash memory is used for the first time, and is not limited to a binary bitmap. During an initialization procedure of the electronic system, the firmware of the electronic system may determine which pages in the table storage region 12 need to be read according to the page validity location bitmap 16A. Furthermore, before shutting down the electronic system, the firmware of the electronic system may also be in charge of confirming that all logical/physical address mapping relationships modified by the operating system are updated to the table storage region 12, as well as confirming the stored page validity location bitmap 16A is a latest binary bitmap.
In an embodiment, apart from the above sequence, the page validity location bitmap 16A also stores a flag for marking whether the page validity location bitmap 16A is correct. Every time when the logical/physical address mapping relationship of a specific block is modified, the flag may first be set to 0. The flag is then set to 1 only when it is confirmed that the table storage region 12 and the page validity location bitmap 16A are also correctly updated. Therefore, Step S21 in
The above modification procedure provides an advantage that, the bit 18B is not set to 1 until the page 22B is modified to the correct content. In other words, if an unexpected abnormality of the electronic system has occurred, the content of the page 22B would not be taken as correct content immediately after the system is restored from the abnormality, but the electronic system waits until the writing procedure to the page 22B is completed. In practice, previously stored data in the target page 22A may be erased to make the target page 22A as a backup page. Furthermore, right after the modification on the page validity location bitmap 16A is completed, firmware of the electronic system may also synchronously update the address mapping table in the auxiliary memory of the electronic system according to the modified content.
It can be seen from the above descriptions that the number of bits in a value of 1 in the page validity location bitmap 16A is a constant value when the content of the table storage region 12 is entirely correct. Taking the table storage region 12 comprising 32 pages and the number of the storage pages 12A being 10 as an example, under normal circumstances, the number of bits with a value of 1 in the page validity location bitmap 16A is 10, and the number of bits with a value of 0 is then 22. Supposing an unexpected abnormality takes place in the electronic system, the number of bits with a value of 1 is 9, and the number of bits with a value of 0 is 23.
Furthermore, the number of bits in a value of 1 in the page validity location bitmap 16A may also serve as basis for determining whether the content of the table storage region 12 is entirely correct.
Conversely, when the determination result from Step S31 is negative, Steps S32 to S35 are performed. Step S33 comprises determining logical/physical address mapping relationships of which of the blocks in the flash memory need to be confirmed according to the valid storage pages (i.e., the pages corresponding to the bits with a value of 1 in the page validity location bitmap 16A). It should be noted that the storage pages are recorded with information of the logical/physical address mapping relationships of which blocks are stored. Therefore, according to the contents of the valid storage pages, it may be identified that logical/physical address mapping relationships of which blocks stored in the table storage region 12 are correct, as well as logical/physical address mapping relationships of which blocks 14 are incorrect. Next, Step S34 comprises scanning the blocks 14 that are determined as the table storage region 12 storing incorrect logical/physical address mapping relationships of the blocks 14 from Step S33, so as to confirm the logical/physical address mapping relationships of the blocks 14. Step S35 comprises storing the logical/physical address mapping relationships obtained from Step S34 and the logical/physical address mapping relationships stored in the valid storage pages determined from Step S33 to the auxiliary memory of the electronic system.
In the above embodiment, the firmware of the electronic system need not re-scan all the blocks 14 even when the content in the table storage region 12 is faulty. In other words, the correct part of the content of the table storage region 12 may still be directly copied to the auxiliary memory. On average, the above solution further shortens the time needed for rebuilding the address mapping table in the auxiliary memory of the electronic system.
According to another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium stores code that is readable and executable by an electronic system. For example, the code can be memory managing firmware installed in the electronic system. The electronic comprises an auxiliary memory and is capable of communicating with a flash memory comprising a plurality of blocks. Each of the blocks comprises a logical/physical address mapping relationship. The logical/physical address mapping relationships are stored in a storage region in the flash memory. The code is for managing the flash memory, and comprises: a first sub-code, for determining whether the logical/physical address mapping relationships stored in the storage region are correct; and a second sub-code, for reproducing the logical/physical address mapping relationships from the storage region to the auxiliary memory as a reference to the electronic system when the electronic system communicates with the flash memory, when a determination result of the first sub-code is affirmative.
According to another embodiment of the present invention, the first sub-code may be modified to determining whether the logical/physical address mapping relationships stored in the table storage region are correct according to the flag or the number of bits with a value of 1 in the page validity location bitmap 16A. In addition, the code may further comprise sub-codes for respectively performing Steps S33 to S35 in
According to yet another embodiment of the present invention, an electronic system 60 as shown in
During an initialization procedure of the electronic system 60, the controller 64 first determines whether the logical/physical address mapping relationships stored in the storage region 72 are correct. When a determination result is affirmative, the controller 64 copies the logical/physical address mapping relationships from the storage region 72 to the auxiliary memory 62 as a reference to the electronic system 60 when the electronic system 60 communicates with the flash memory 70. In practice, the controller 63 may be designed as comprising a determining unit for performing Steps 31 and 33, a scanning unit for performing Step S34, and a reproducing unit for performing Step S35. Operation details of the units may be appreciated by the previous description and shall not be further described for brevity.
Furthermore, the controller 64 may also be designed as further comprising a setting unit and a read/write unit. The setting unit is for setting the bits in the page validity location bitmap 16A to 0 or 1. The read/write unit is for writing the modified address mapping relationships and other logical/physical address mapping relationships originally stored in the target page to another page. Similarly, operation details of the two hardware units may be appreciated by the previous description and shall not be further described for brevity.
In conclusion, the present invention provides a novel memory managing solution. By establishing a storage region in a flash memory and centralized storing logical/physical address mapping relationships of all blocks of the flash memory, the memory control solution of the present invention is capable of effectively shortening the time needed for rebuilding an address mapping table in an auxiliary memory of an electronic system, thereby optimizing overall efficiency of the electronic system.
Taking a flash memory comprising 100 blocks in a UBIFS system as an example, the system needs to read 200 pages for rebuilding a logical/physical address mapping table during system initialization before applying the memory managing solution provided by the present invention.
By applying the memory managing solution of the present invention, an average search number of binary bitmaps that are searched for page validity location bitmaps is approximately half of the number of the pages. For example, an average search number for a block comprising 64 pages is 32 pages. Assuming that one page is capable of storing logical/physical address mapping relationships of 16 blocks, only 7 pages are required for adequately storing logical/physical address mapping relationships of 100 blocks. Therefore, the number of pages to be read by the memory firmware reduces from 200 to an average number of 39 pages, and thereby saving around 60% of the originally required time. As the capacity of the pages gets greater or as the number of blocks in the flash memory gets larger, the amount of time saved by applying the memory managing solution of the present invention also gets larger.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 100136362 | Oct 2011 | TW | national |
