Claims
- 1. A circuit for an analyte detection system comprising:a sensor site wherein sensor material is constrained at the sensor site and has regions of a nonconductive organic material and a conductive material, and in the presence of an analyte, the sensor material has a measurable change in an electrical property; and a floating gate device coupled to the sensor site, wherein the floating gate device stores an analog value, representative of the measurable chance in the electrical property from the sensor site, based on an amount of charge on a floating gate of the floating gate device; and the analog value is used by the analog detection system to determine the presence of the analyte.
- 2. The circuit of claim 1 further comprising:a first transistor coupled between a first supply voltage and a first node, wherein a gate of the first transistor is coupled to the floating gate device; and a second transistor coupled between the first node and a second supply voltage, wherein a gate of the second transistor is coupled to a bias voltage.
- 3. The circuit of claim 2 wherein the first transistor is a PMOS device and the second transistor is an NMOS device.
- 4. The circuit of claim 2 further comprising:a capacitor coupled between the first node and the floating gate device.
- 5. The circuit of claim 1 wherein the floating gate device stores an analog value with about 14 bits or greater of accuracy.
- 6. The circuit of claim 1 wherein the floating gate device stores an analog value having 14 bits or less of accuracy.
- 7. The circuit of claim 1 wherein the floating gate device provides nonvolatile storage.
- 8. The circuit of claim 1 wherein the floating gate device operates in the subthreshold regime.
Priority Claims (1)
Number |
Date |
Country |
Kind |
PCT/US/16527 |
Aug 1998 |
WO |
|
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims the benefit of U.S. provisional application Nos. 60/081,182, filed Apr. 9, 1998, and 60/092,707, filed Jul. 14, 1998, and is a continuation of U.S. patent application Ser. No. 09/276,988, filed Mar. 26, 1999 now U.S. Pat. No. 6,495,892.
STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
The research carried out in this application was supported in part by grants from the United States Army (#DAAG55-97-1-0187), DARPA (#DAAK60-97-K-9503), and the National Science Foundation (CHE 9202583). The U.S. government may have rights in any patent issuing from this application.
US Referenced Citations (12)
Foreign Referenced Citations (2)
Number |
Date |
Country |
0774662 |
May 1997 |
EP |
WO 9322678 |
Nov 1993 |
WO |
Non-Patent Literature Citations (2)
Entry |
Diorio et al., “A floating-gate MOS learning array with locally computed weight updates” IEEE Transactions on Electronic Devices (1997) 44(12):2281-2289. |
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Provisional Applications (2)
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Number |
Date |
Country |
|
60/092707 |
Jul 1998 |
US |
|
60/081182 |
Apr 1998 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/276988 |
Mar 1999 |
US |
Child |
09/287522 |
|
US |