Claims
- 1. An electronic circuit for readout of an IR focal plane array having a plurality of IR detector cells, comprising:
- a plurality of inverter amplifiers, said inverter amplifiers comprising integrated circuits fabricated on a neutron transmutation doped (NTD) silicon wafer using a p-well CMOS process to provide threshold uniformity and low power dissipation;
- each of said amplifiers having an input, an output, a driver FET, a bias FET, a cascode FET, and a charge storage capacitor connected to said amplifier output, each of said FETs having a gate, a source, and a drain, said amplifier input connected to the gate of said driver FET, the drain of said driver FET connected to the drain of said cascode FET, the source of said cascode FET connected to the drain of said bias FET, the source of said bias FET connected to a power supply, and the drains of said driver FET and said cascode FET further connected to a means for controlling said amplifier output;
- a plurality of FET switches, each of said FET switches connecting one of said IR detector cells to said input of one of said amplifiers;
- a first shift register connected for providing cell select clock signals to the gates of said cascode FETs and FET switches for accessing said detector cells and clamping idle ones of said detector cells to normal operating bias to eliminate excess detector noise and crosstalk;
- a second shift register for multiplexing said amplifiers to an output bus connected to said amplifier outputs; and
- said output bus having distributed capacitance for providing additional detector-generated charge storage capacity.
- 2. The circuit of claim 1, wherein each of said amplifier inputs comprises an input bus for connecting said amplifier to said FET switches of a group of neighboring detector cells.
- 3. An electronic circuit for readout of an IR focal plane array having a plurality of groups of neighboring IR detector cells, comprising:
- a plurality of CMOS inverter amplifiers corresponding to said plurality of groups of IR detector cells, each of said CMOS amplifiers comprising an integrated circuit fabricated on a neutron transmutation doped (NTD) silicon wafer using a p-well CMOS process to provide threshold uniformity and low power dissipation;
- each of said CMOS amplifiers having an input bus, an output, a driver FET, a bias FET, a cascode FET, and a charge storage capacitor connected to said amplifier output, each of Said FETs having a gate, a source, and a drain, said input bus connected to the gate of said driver FET, the drain of said driver FET connected to the drain of said cascode FET, the source of said cascode FET connected to the drain of said bias FET, the source of said bias FET connected to a power supply, and the drains of said driver FET and said cascode FET further connected to a means for controlling said amplifier output;
- a plurality of FET switches, each of said FET switches connected between one of said IR detector cells and one of said input buses, each of said groups of neighboring IR detector cells thereby connected to said input bus of said corresponding one of said CMOS amplifiers;
- an output bus having distributed capacitance for providing additional detector-generated charge storage capacity;
- each of said cascode FETs and FET switches having a gate connected to received cell select clock signals for accessing specific ones of said IR detector cells and clamping idle ones of said IR detector cells to normal operating bias to eliminate excess detector noise and crosstalk; and
- means for multiplexing said amplifier outputs of said plurality of CMOS amplifier on said output bus.
- 4. The circuit of claim 3, wherein each of said CMOS amplifiers has an integration duty cycle, and wherein said plurality of CMOS amplifiers provide readout capability for the focal plane array without significant loss of said duty cycle.
- 5. An electronic circuit for readout of a group of neighboring IR detector cells of an IR focal plane array, comprising:
- a CMOS inverter amplifier comprising an integrated circuit fabricated on a neutron transmutation doped (NTD) silicon wafer using a p-well CMOS process to provide threshold uniformity and low power dissipation;
- an input bus connecting said group of neighboring IR detector cells to said CMOS amplifier;
- said CMOS amplifier comprising an amplifier output, a driver FET, a cascode FET, a bias FET, and a charge storage capacitor connected to said amplifier output, each of said FETs having a gate, a source, and a drain, said input bus connected to the gate of said driver FET, the drain of said driver FET connected to the drain of said cascode FET, the source of said cascode FET connected to the drain of said bias FET, the source of said bias FET connected to a power supply, and the drains of said driver FET and said cascode FET further connected to a means for controlling said amplifier output;
- a plurality of FET switches, each of said FET switches connected between said input bus and a corresponding one of said IR detector cells;
- an output bus connected to said CMOS amplifier output; and
- said output bus having distributed capacitance for providing additional detector-generated charge storage capacity.
- 6. The electronic circuit of claim 5, wherein said cascode FET and each of said FET switches have gates connected to receive cell select clock signals for accessing specific ones of said IR detector cells and clamping idle ones of said IR detector cells to normal operating bias to eliminate excess detector noise and crosstalk.
- 7. The electronic circuit of claim 6, further comprising:
- a plurality of groups of neighboring IR detector cells, each of said groups of IR detector cells connected to one of a corresponding plurality of said CMOS amplifiers; and
- means for multiplexing said amplifier outputs of said plurality of CMOS amplifiers on said output bus.
- 8. The electronic circuit of claim 7, wherein each of said CMOS amplifiers has an integration duty cycle, and wherein said plurality of CMOS amplifiers provide readout capability for the focal plane array without significant loss of said duty cycle.
Parent Case Info
This application is a continuation of application Ser. No. 825,480, filed Jan. 24, 1992, now abandoned.
US Referenced Citations (8)
Foreign Referenced Citations (1)
Number |
Date |
Country |
WO9104633 |
Apr 1991 |
GBX |
Continuations (1)
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Number |
Date |
Country |
Parent |
825480 |
Jan 1992 |
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