Patent Application
20150111544
1. Technical Field
The disclosure generally relates to electronic devices, and particularly to an electronic device having an indicating function for missed calls.
2. Description of the Related Art
Most electronic devices can communicate with others, such as mobile phones, and are in widespread use. When there is an incoming call and the call is not answered timely (i.e., a missed call), information of the missed call will be displayed on a display screen of the electronic device. For a user to know that there is a missed call or not, he or she must check the display screen. However, for many reasons, for example, the user forgetting to bring along the electronic device, or due to being busy, many important incoming calls may be missed, which is usually inconvenient and possibly disadvantageous for the user.
Therefore, there is room for improvement within the art.
Many aspects of the present embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment.
The electronic device 100 includes a signal triggering module 10, a signal amplifying circuit 30, a driving circuit 50, and an indicating circuit 70, electronically connected in that order. When there is an incoming call and is not answered, the electronic device 100 generates an incoming call signal. When the missed call is Known (e.g., a new incoming call is being answered), the electronic device 100 generates a busy signal. When a button (e.g., a hang up button) of the electronic device 100 is operated, which indicates a missed call, as the electronic device 100 generates a control signal. The signal triggering module 10 receives the incoming call signal, the busy signal, and the control signal, generate a triggering signal according to these signals, and sends the triggering signal to the signal amplifying circuit 30.
In detail, when the incoming call signal is received, the signal triggering module 10 processes the incoming call signal, generates a first triggering signal (e.g., a high level signal, logic 1) according to the incoming call signal, and sends the first triggering signal to the signal amplifying circuit 30. The signal amplifying circuit 30 amplifies current of the first triggering signal from the signal triggering module 10, and transmits the amplified first triggering signal to the driving circuit 50. Under the control of the amplified first triggering signal, the driving circuit 50 starts to work and generates a driving signal. The driving signal is sent to the indicating circuit 70 to control the indicating circuit 70 to work, such as blink or flash, which indicates a missed call.
Once the busy signal or the control signal is received, these indicate a missed call. In this way, the signal triggering module 10 processes the busy signal or the control signal, generates a second triggering signal opposite to the first triggering signal (e.g., a low level signal, logic 0) according to the busy signal or the control signal, and sends the second triggering signal to the signal amplifying circuit 30. The signal amplifying circuit 30 amplifies current of the second triggering signal, and sends the amplified second triggering signal to the driving circuit 50. Under the control of the amplified second triggering signal, the driving circuit 50 stops working and does not generate any signal to the indicating circuit 70, which causes the indicating circuit 70 to stop working
The signal triggering circuit 13 includes a signal triggering chip U2, resistors R3-R4, a capacitor C3, and a control switch S. A type of the signal triggering chip U2 may be SN74LVC2G74DCUR. The signal triggering chip U2 includes a power pin VDD, a grounding pin GND2, a clock pin CLK, a data pin D, a preset pin
In detail, when the signal triggering circuit 10 receives the incoming call signal through the clock pin CLK. Under a control of the clock pin CLK, the first output pin Q outputs the first triggering signal which is the same as the signal from the date pin D. In this exemplary embodiment, because the data pin D is connected to the power supply P3V3 through the resistor R2, the first triggering signal is a high level signal (e.g., logic 1). When a missed call is known, the signal triggering module 10 receives the busy signal or the control signal through the clearing pin CLR . In general, the clearing pin
The signal amplifying circuit 30 is electronically connected between the signal triggering module 10 and the driving circuit 50. The signal amplifying circuit 30 amplifies a current of the triggering signal when the current of the triggering signal output by the signal triggering module 10 is not enough to drive the driving circuit 50 to work.
In detail, the signal amplifying circuit 30 includes a first transistor Q1, a second transistor Q2, and resistors R5-R7. The first transistor Q1 and the second transistor Q2 are both npn transistors. A base of the first transistor Q1 is regarded as an input end of the signal amplifying circuit 30 and is electronically connected to the first output pin Q through the resistor R5. An emitter of the first transistor Q1 is grounded. A collector of the first transistor Q1 is connected to the power supply P3V3 through the resistor R6. A base of the second transistor Q2 is connected to the collector of the first transistor Q1. An emitter of the second transistor Q2 is grounded. A collector of the second transistor Q2 is regarded as an output end of the signal amplifying circuit 30. The collector of the second transistor Q2 is electronically connected to the power supply P3V3 through the resistor R7 and is also electronically connected to the driving circuit 50.
When the input end of the signal amplifying circuit 30 (i.e., the base of the first transistor Q1) receives a high level signal the first transistor Q1 is turned on and the second transistor Q2 is turned off. In this way, the output of the signal amplifying circuit 30 (i.e., the collector of the second transistor Q2) is electronically connected to the power supply P3V3 and outputs a high level signal. An output current of the signal amplifying circuit 30 is amplified to β times an input current of the signal amplifying circuit 30 (parameter β is a common emitter current gain of the first transistor Q1 or of the second transistor Q2).
When the input end of the signal amplifying circuit 30 receives a low level signal, the first transistor Q1 is turned off and the second transistor Q2 is turned on. In this way, the output end of the signal amplifying circuit 30 is grounded by the conducting second transistor Q2 and outputs a low level signal. The signal amplifying circuit 30 only amplifies a current of the triggering signal and does not alter logical value of the triggering signal. That is, when the input of the signal amplifying circuit 30 is logic 1, the output of the signal amplifying circuit 30 is still logic 1. When the input of the signal amplifying circuit 30 is logic 0, the output of the signal amplifying circuit 30 is still logic 0.
The driving circuit 50 includes a drive chip U3, a resistor R8, and a capacitor C4. A type of the driving chip U3 may be SN74LVC1G14DCUKR. The driving chip U3 includes a power pin VBB, a signal input pin A2, a signal output pin Y2, a ground pin GND3, and an idle pin NC2. The power pin VBB is electronically connected to the output of the signal amplifying circuit 30, that is, the power pin VBB is electronically connected to the output of the signal triggering circuit 11 (i.e., the first output pin Q) through the signal amplifying circuit 30. The ground pin GND3 is grounded. The signal input pin A2 is connected to the signal output pin Y2 through the resistor R8, and is grounded through the capacitor C4. The signal output pin Y2 is further electronically connected to the indicating circuit 70.
When the driving circuit 50 receives the amplified first triggering signal, the driving circuit 50 is powered on and starts to work. In this way, the signal input pin A2, the resistor R8, and the capacitor C4 form a pulse generator to output a pulse signal having a frequency of about 1 Hertz to the indicating circuit 70. When the driving circuit 50 receives the second triggering signal, the driving circuit 50 stops working and does not output any signal.
The indicating circuit 70 includes a light emitting diode LED and resistors R9-R11. An anode of the light emitting diode LED is electronically connected to the power supply P3V3 through the resistor R9. A cathode of the light emitting diode LED is electronically connected to power supply P3V3 through the resistor R10, and is electronically connected to the output of the driving circuit 50 (i.e., the signal output pin Y2) by the resistor R11.
When the driving circuit 50 outputs the pulse signal through the signal output pin Y2, the light emitting diode LED flashes to indicate that there is a missed call. When the driving circuit 50 does not output any signal, the cathode of the light emitting diode LED is electronically connected to the power supply P3V3 through the resistor R10. The light emitting diode LED is turned off and does not emit any light.
In use of the electronic device 100, when there is an incoming call and which is missed, the electronic device 100 generates an incoming call signal. The signal processing circuit 11 receives the incoming call signal. The signal processing chip U1 processes the incoming call signal and outputs a inverted incoming call signal to the signal triggering circuit 13 through the signal output pin Y1. The signal triggering circuit 13 receives the inverted incoming call signal through the clock pin CLK and outputs a first triggering signal. The signal amplifying circuit 30 amplifies the current of first triggering signal to drive the driving circuit 50 to work. In this way, the signal input pin A2, the resistor R8, and the capacitor C4 of the driving circuit 50 form a pulse generator to output a pulse signal to the indicating circuit 70. Under the control of the pulse signal from the driving circuit 50, the light emitting diode LED flashes to indicate that there is a missed call.
Once the missed call is known (e.g., a new incoming call is answered or the control switch S is operated), the electronic device 100 generates a busy signal or a control signal. The signal triggering circuit 13 receives the busy signal or the control signal and outputs a second triggering signal opposite to the first triggering signal through the first output pin Q. The second triggering signal is transmitted to the driving circuit 50 through the signal amplifying circuit 30 so as to control the driving circuit 50 to stop working. In this way, the driving circuit 50 does not output any signal. The cathode of the light emitting diode LED is connected to the power supply P3V3 through the resistor R10. The light emitting diode LED is turned off and does not emit any light.
When the clock pin CLK is enabled by a low level signal, the signal processing circuit 11 can be omitted and the clock pin CLK can receive the incoming call signal directly.
When a current of the triggering signal of the signal triggering module 10 is always enough to drive the driving circuit 50 to work, the signal amplifying circuit 30 can be omitted, and the signal triggering module 10 is electronically connected to the driving circuit 50 directly.
In the present specification and claims, the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. Further, the word “comprising” does not exclude the presence of elements or steps other than those listed.
It is to be also understood that even though numerous characteristics and advantages of exemplary embodiments have been set forth in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of arrangement of parts within the principles of this disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013104932782 | Oct 2013 | CN | national |
