Patent Application
20080007816
The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings.
The transistor 21 may be an n-channel field-effect transistor as depicted in the drawing. The transistor 21 has its gate connected to a scan line 30, one of its source and drain (input terminal) connected to a data line 31, and the other of its source and drain (output terminal) connected to an input terminal of the latch circuit 26.
The latch circuit (flip-flop circuit) 26 may be configured as a combination of two n-channel field-effect transistors 22 and 24 and two p-channel field-effect transistors 23 and 25, as depicted in the drawing. More specifically, the transistors 22 and 23 are connected to each other in such a manner that their sources or drains are connected to each other. The other of the source and drain of the transistor 22 is connected to a low-voltage power supply line 33. The other of the source and drain of the transistor 23 is connected to a high-voltage power supply line 32. Similarly, the transistors 24 and 25 are connected to each other in such a manner that their sources or drains are connected to each other. The other of the source and drain of the transistor 24 is connected to the low-voltage power supply line 33. The other of the source and drain of the transistor 25 is connected to a high-voltage power supply line 32. The gates of the transistors 22 and 23 are connected to a connection point N1 at which the sources or drains of the transistors 24 and 25 are connected to each other. The connection point N1 functions as the input terminal of the latch circuit 26. The input terminal N1 is connected to the other of the source and drain (output terminal) of the transistor 21, as depicted in the drawing. The gates of the transistors 24 and 25 are connected to a connection point N2 at which the sources or drains of the transistors 22 and 23 are connected to each other. The connection point N2 functions as the output terminal of the latch circuit 26. The input terminal N2 of the latch circuit 26 is connected to a first electrode 27a of the electrophoretic element 27. When the latch circuit 26 receives a high-potential signal at its input terminal N1, the latch circuit 26 outputs a low potential VSS from its output terminal N2. Meanwhile, when the latch circuit 26 receives a low-potential signal at its input terminal N1, the latch circuit 26 outputs a high potential VEP from its output terminal N2.
The electrophoretic element 27 includes a first electrode 27a, a second electrode 27b, an electrophoretic material 27c (see
Next, constituting blocks will be described with reference to
The scan-line driver (first driver) 10 supplies a control signal to the gate of one of the transistors 21 and thus controls turning ON and OFF of the transistor 21. The scan-line driver 10 includes a shifter register circuit 11 and a level shifter circuit 12. The shifter register circuit 11 includes flip-flops having a plurality of stages (whose number of stages corresponds to the number of scan lines 30) and outputs a control signal Vscan to one of the scan lines 30 at predetermined intervals. The level shifter circuit 12 raises the voltage level of the control signal Vscan output from the shifter register circuit 11. For example, in the present embodiment, the power supply voltage of the scan-line driver 10 is set to 5 V, and the power supply voltage of the level shifter circuit 12 is set to 7 V or higher. With such voltage settings, it is possible to prevent any fall in potential of the control signal to be supplied to the scan lines 30.
The data-line driver (second driver) 13 supplies a data signal for controlling the state of the pixel section 20 to the input terminal of the latch circuit 26. The data-line driver 13 includes a shifter register circuit 14 and a latch circuit 15. The shifter register circuit 14 includes flip-flops having a plurality of stages (whose number of stages corresponds to the number of data lines 31) and outputs a data signal VDATA to one of the data lines 31 at predetermined intervals. The latch circuit 15 retains the data signal VDATA output from the shifter register circuit 14 and outputs the data signal VDATA to the data lines 31. In the present embodiment, the data signal VDATA is transmitted in a dot-sequential manner rather than in a line-sequential manner.
The memory power supply control circuit (first power supply control circuit) 16 controls a power supply potential to be supplied to the latch circuit 26 included in each of the pixel sections 20. Here, the power supply potential to be controlled by the memory power supply control circuit 16 is classified into a high-potential side power supply potential VEP and a low-potential side power supply potential VSS (see
The common electrode control circuit (second power supply control circuit) 17 controls a potential to be supplied to the second electrode (common electrode) 27b of the electrophoretic element 27. In the present embodiment, the potential controlled by the common electrode control circuit 17 (the potential hereinafter will be referred to as “common electrode potential”) is also variably set, and details of which will be described later.
The electrophoretic device 100 of the present invention has such a configuration. Hereinafter, a method (i.e., a driving method) of supplying the driving signal to each of the pixel sections 20 will be described in detail. The driving method of the invention can be embodied by one of the following three methods.
In an image data writing period (first driving period), the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. Here, “reference potential” corresponds to, for example, the ground potential level (0 V) as depicted in the drawing. In synchronization with the supply of the reference potential, the scan-line driver 10 supplies the control signal to the gate of one of the transistors 21 to turn ON the transistor 21, and the data-line driver 13 supplies the data signal to the input terminal N1 of the latch circuit 26. Here, “data signal” corresponds to one of a relatively high-potential signal (for example, 5 V) and a relatively low-potential signal (for example, 0 V). In the present embodiment, the high-potential signal (HIGH signal) corresponds to white display, and the low-potential signal (LOW signal) corresponds to black display. Since this example is concerned with the black display, the low-potential signal is supplied as the data signal. The low-potential signal is retained in the latch circuit 26 until a subsequent data writing operation is performed to the latch circuit 26. Accordingly, the first potential (for example, 5 V as depicted in the drawing) supplied from the memory power supply control circuit 16 is output from the output terminal N2 of the latch circuit 26. In this period, the electrophoretic element 27 is charged in such a manner that the potential V1 of the first electrode 27a is set to the first potential, and the potential VCOM of the second electrode 27b is set to the reference potential. As a result, the potential V1 becomes greater than the potential VCOM. Accordingly, as schematically depicted by the black arrows in the drawing, a potential difference (electric field) of 5 V is generated across the electrodes 27a and 27b in a direction from the first electrode 27a toward the second electrode 27b. Accordingly, the pixel section 20 is controlled by the electric field so as to display a black color.
In a VCOM driving period (second driving period) subsequent to the image data writing period, a driving signal (alternating signal) alternating between the reference potential (for example, 0 V as depicted in the drawing) and a second potential (for example, 15 V as depicted in the drawing) higher than the first potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In this case, as described above, the potential V1 of the first electrode 27a is maintained at the first potential (5 V in this example). Therefore, when the potential of the driving signal becomes higher than the first potential, the potential VCOM of the second electrode 27b becomes higher than the potential V1 of the first electrode 27a in the electrophoretic element 27. Accordingly, as schematically depicted by the white arrows in the drawing, a potential difference (electric field) of 10 V is generated across the electrodes 27a and 27b in a direction from the second electrode 27b toward the first electrode 27a. Accordingly, the pixel section 20 is controlled by the electric field so as to display a white color. Meanwhile, when the potential of the driving signal becomes lower than the first potential, the potential V1 of the first electrode 27a becomes higher than the potential VCOM of the second electrode 27b in the electrophoretic element 27. Accordingly, as schematically depicted by the black arrows in the drawing, a potential difference (electric field) of 5 V is generated across the electrodes 27a and 27b in a direction from the first electrode 27a toward the second electrode 27b. Accordingly, the pixel section 20 is controlled by the electric field so as to display a black color. In this way, by the supply of such an alternating driving signal, the black and white particles contained in the electrophoretic material 27c are mixed with each other and thus placed in such a state that the particles are easily movable. The VCOM driving period (second driving period) functions as a reset period for mixing the particles with each other in preparation of a subsequent displaying operation.
In the foregoing descriptions, a pulse-shaped driving signal (rectangular waveform driving signal) is illustrated as an example. The driving signal may have a square waveform in the present invention (the same statement can be applied to the following driving methods).
In a display period (third display period) subsequent to the VCOM driving period, the reference potential (0 V in this example) is supplied from the common electrode control circuit 17 to the second electrode 27b. In this case, similar to the case of the foregoing periods, since the potential V1 of the first electrode 27a in the electrophoretic element 27 is maintained at the first potential (5 V in this example), the potential V1 of the first electrode 27a becomes higher than the potential VCOM of the second electrode 27b. Accordingly, as schematically depicted by the black arrows in the drawing, a potential difference (electric field) of 5 V is generated across the electrodes 27a and 27b in a direction from the first electrode 27a toward the second electrode 27b. Accordingly, the pixel section 20 is controlled by the electric field so as to display a black color. In the display period (third display period), it is also desirable that the high-potential side power supply potential VEP to be supplied from the memory power supply control circuit 16 to the latch circuit 26 is set to a third potential higher than the first potential so that the third potential (for example, in the range of 7 and 10 V) is output from the output terminal N2 of the latch circuit 26 (the third potential is depicted by the dotted lines in the drawing). With such a configuration, it is possible to further increase the potential difference caused in a direction from the first electrode 27a toward the second electrode 27b and thus further increase a display speed and contrast. When the power supply is cut off thereafter, the potential difference between the first and second electrodes 27a and 27b gradually decreases to 0 V.
Next, a driving method for displaying a white color using one of the pixel sections 20 will be described with reference to
In the image data writing period, the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In synchronization with the supply of the reference potential, the scan-line driver 10 supplies the control signal to the gate of one of the transistors 21 to turn ON the transistor 21, and the data-line driver 13 supplies the data signal to the input terminal N1 of the latch circuit 26. Since the example is concerned with the white display, the high-potential signal is supplied as the data signal. The high-potential signal is retained in the latch circuit 26 until a subsequent data writing operation is performed to the latch circuit 26. Accordingly, the potential VSS supplied from the memory power supply control circuit 16 is output from the output terminal N2 of the latch circuit 26. In this period, the electrophoretic element 27 is charged in such a manner that the potential V1 (=VSS) of the first electrode 27a becomes substantially equal to the potential VCOM of the second electrode 27b. Therefore, there is no potential difference between the first electrode 27a and the second electrode 27b. Accordingly, the displaying state of the pixel section 20 is not changed.
In the VCOM driving period subsequent to the image data writing period, the driving signal alternating between the reference potential and the second potential higher than the first potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In this case, as described above, the potential V1 of the first electrode 27a is maintained at the reference potential. Accordingly, as schematically depicted by the white arrows in the drawing, a potential difference (electric field) of 15 V is generated across the electrodes 27a and 27b in a direction from the second electrode 27b toward the first electrode 27a. Accordingly, the pixel section 20 is controlled by the electric field so as to display a white color. That is, in the VCOM driving period, by the supply of such an alternating driving signal, the black and white particles contained in the electrophoretic material 27c are mixed with each other and thus placed in such a state that the white and black particles are easily movable toward the second electrode 27b and the first electrode 27a, respectively. As a result, the pixel section 20 is controlled to display a white color.
In the display period subsequent to the VCOM driving period, the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In this case, similar to the case of the foregoing periods, since the potential V1 of the first electrode 27a in the electrophoretic element 27 is maintained at the potential VSS equal to the reference potential, there is no potential difference between the first electrode 27a and the second electrode 27b. Incidentally, since the pixel section 20 has been controlled to display a white color in the previous VCOM driving period, the pixel section 20 maintains the white displaying state. Accordingly, the pixel section 20 is controlled to display a white color in the display period. When the power supply is cut off thereafter, the potential difference between the first and second electrodes 27a and 27b gradually decreases to 0 V.
In this way, in the case of using the first driving method, since a data writing operation is performed to the latch circuit 26 when the high-potential side power supply potential VEP of the memory power supply control circuit 16 is at a relatively low potential (5 V in this example), it is not necessary to install a level shifter circuit in the data-line driver 13. Accordingly, it is possible to decrease the overall circuit size.
Since the black and white particles are mixed with each other in the VCOM driving period, latent images are not displayed on the pixel section 20 at the time of controlling the pixel section 20 to display a black color, thereby realizing a high-quality display.
Since in the display period, the high-potential side power supply potential VEP is raised from the first potential to the third potential higher than the first potential, it is possible to further increase a display contrast and a display-speed at the time of displaying a black color.
In the first driving method, if the black and white particles contained in the electrophoretic material 27c are charged in an opposite manner to the case of the above-mentioned case, the pixel section 20 may be controlled in an opposite manner. That is, the pixel section 20 may be controlled to display a white color in accordance with the driving method described in connection with
In an entire-pixel LOW-potential writing period (first driving period), the scan-line driver 10 supplies the control signal to the gate of one of the transistors 21 to turn ON the transistor 21, and the data-line driver 13 supplies the data signal to the input terminal N1 of the latch circuit 26. In the entire-pixel LOW-potential writing period, a high-potential signal is supplied to the input terminal N1 of the latch circuit 26. The high-potential signal is retained in the latch circuit 26 until a subsequent data writing operation is performed to the latch circuit 26. Accordingly, the potential VSS supplied from the memory power supply control circuit 16 is output from the output terminal N2 of the latch circuit 26. In the present embodiment, the potential VSS corresponds to the reference potential as described above. In this period, since the electrophoretic element 27 is charged in such a manner that the potential V1 of the first electrode 27a is set to the potential VSS (=the reference potential), and the potential VCOM of the second electrode 27b is set to the reference potential, there is no potential difference between the first and second electrodes 27a and 27b. Accordingly, the pixel section 20 maintains its previous displaying state. Such a writing operation is performed to the entire pixel sections 20.
In a VCOM driving period (second driving period) subsequent to the entire-pixel LOW-potential writing period, a driving signal alternating between the reference potential and a second potential higher than the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In this case, as described above, the potential V1 of the first electrode 27a is maintained at the reference potential. Accordingly, as schematically depicted by the white arrows in the drawing, a potential difference of 15 V is generated across the electrodes 27a and 27b in a direction from the second electrode 27b toward the first electrode 27a. Accordingly, the pixel section 20 is controlled by the electric field so as to display a white color. That is, in the VCOM driving period, by the supply of such an alternating driving signal, the black and white particles contained in the electrophoretic material 27c are mixed with each other and thus placed in such a state that the white and black particles are easily movable toward the second electrode 27b and the first electrode 27a, respectively. As a result, the pixel section 20 is controlled to display a white color.
In an image data writing period (third driving period) subsequent to the VCOM driving period, the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In synchronization with the supply of the reference potential, the scan-line driver 10 supplies a control signal to the gate of one of the transistors 21 to turn ON the transistor 21, and the data-line driver 13 supplies the data signal to the input terminal N1 of the latch circuit 26. Since this example is concerned with the black display, the low-potential signal is supplied as the data signal. The low-potential signal is retained in the latch circuit 26 until a subsequent data writing operation is performed to the latch circuit 26. Accordingly, the high-potential side power supply potential VEP supplied from the memory power supply control circuit 16 is output from the output terminal N2 of the latch circuit 26. In this example, the high-potential side power supply potential VEP corresponds to the first potential. In this period, the electrophoretic element 27 is charged in such a manner that the potential V1 (=the first potential) of the first electrode 27a becomes higher than the potential VCOM (=the reference potential) of the second electrode 27b. Accordingly, as schematically depicted by the black arrows in the drawing, a potential difference of 5 V is generated across the electrodes 27a and 27b in a direction from the first electrode 27a toward the second electrode 27b. Accordingly, the pixel section 20 is controlled by the electric field so as to display a black color.
In a contrast boost period (fourth driving period) subsequent to the image data writing period, a third potential higher than the first potential is generated as the high-potential side power supply potential VEP to be supplied from the memory power supply control circuit 16 to the latch circuit 26, and the third potential (for example, in the range of 7 and 10 V) is output from the output terminal N2 of the latch circuit 26. With such a configuration, it is possible to further increase the potential difference caused in a direction from the first electrode 27a toward the second electrode 27b and thus further increasing a display speed and contrast. When the power supply is cut off thereafter, the potential difference between the first and second electrodes 27a and 27b gradually decreases to 0 V.
Next, a driving method for displaying a white color using the pixel section 20 will be described with reference to
In the entire-pixel LOW-potential writing period, the scan-line driver 10 supplies the control signal to the gate of one of the transistors 21 to turn ON the transistor 21, and the data-line driver 13 supplies the data signal to the input terminal N1 of the latch circuit 26. Since detailed operations for this period are the same as those of the foregoing black displaying case, descriptions thereof will be omitted.
In the VCOM driving period subsequent to the entire-pixel LOW-potential writing period, a driving signal alternating between the reference potential and a second potential higher than the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. Since detailed operations for this period are the same as those of the foregoing black displaying case, descriptions thereof will be omitted.
In the image data writing period subsequent to the VCOM driving period, the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In synchronization with the supply of the reference potential, the scan-line driver 10 supplies a control signal to the gate of one of the transistors 21 to turn ON the transistor 21, and the data-line driver 13 supplies the data signal to the input terminal N1 of the latch circuit 26. Since this example is concerned with the white display, the high-potential signal is supplied as the data signal. The high-potential signal is retained in the latch circuit 26 until a subsequent data writing operation is performed to the latch circuit 26. Accordingly, the potential VSS (equal to the reference potential in this example) supplied from the memory power supply control circuit 16 is output from the output terminal N2 of the latch circuit 26. In this period, since the electrophoretic element 27 is charged in such a manner that there is no potential difference between the potential V1 of the first electrode 27a and the potential VCOM of the second electrode 27b, the displaying state of the pixel section 20 depends on its controlled state in the previous driving period. As a result, the pixel section 20 is controlled to display a white color.
In the contrast boost period (fourth driving period) subsequent to the image data writing period, the potential VSS (=the reference potential) is output from the output terminal N2 of the latch circuit 26, and the electrophoretic element 27 maintains its charged state in which there is no potential difference between the potential V1 of the first electrode 27a and the potential VCOM of the second electrode 27b. That is, the pixel section 20 is controlled to maintain the white displaying state. When the power supply is cut off thereafter, the potential difference between the first and second electrodes 27a and 27b gradually decreases to 0 V.
In this way, in the case of using the second driving method, since a data writing operation is performed to the latch circuit 26 when the high-potential side power supply potential VEP of the memory power supply control circuit 16 is at a relatively low potential, it is not necessary to install a level shifter circuit in the data-line driver 13. Accordingly, it is possible to decrease the overall circuit size.
Incidentally, in the VCOM driving period, the electrophoretic element is controlled to preferentially display a white color while the black and white particles are mixed with each other. In this way, by controlling to preferentially display a white color and then a black color, it is possible to realize a high-quality display.
Since in the contrast boost period, the high-potential side power supply potential VEP is raised from the first potential to the third potential higher than the first potential, it is possible to further increase a display contrast and a display speed at the time of displaying a black color.
In an image data writing period (first driving period), the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In synchronization with the supply of the reference potential, the scan-line driver 10 supplies the control signal to the gate of one of the transistors 21 to turn ON the transistor 21, and the data-line driver 13 supplies the data signal to the input terminal N1 of the latch circuit 26. Since this example is concerned with the black display, the low-potential signal is supplied as the data signal. The low-potential signal is retained in the latch circuit 26 until a subsequent data writing operation is performed to the latch circuit 26. Accordingly, the first potential (for example, 5 V as depicted in the drawing) supplied as the high-potential side power supply potential VEP from the memory power supply control circuit 16 is output from the output terminal N2 of the latch circuit 26. In this period, the electrophoretic element 27 is charged in such a manner that the potential V1 (=the first potential) of the first electrode 27a becomes higher than the potential VCOM (=the reference potential) of the second electrode 27b. Accordingly, a potential difference of 5 V is generated across the electrodes 27a and 27b in a direction from the first electrode 27a toward the second electrode 27b. Accordingly, the pixel section 20 is controlled by the electric field so as to display a black color.
In a first VCOM driving period (second driving period) subsequent to the image data writing period, a driving signal alternating between the reference potential and a second potential (for example, 15 V as depicted in the drawing) higher than the first potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In synchronization with the supply of the driving signal, a potential equal to the second potential is supplied as the high-potential side power supply potential VEP from the memory power supply control circuit 16 to the output terminal N2 of the latch circuit 26. Therefore, when the potential of the driving signal becomes equal to the second potential, the electrophoretic element 27 is charged in such a manner that the potential V1 of the first electrode 27a becomes equal to the potential VCOM of the second electrode 27b. Accordingly, in this case, no potential difference is generated between the first and second electrodes 27a and 27b. Meanwhile, when the potential of the driving signal becomes equal to the reference potential, the electrophoretic element 27 is charged in such a manner that the potential V1 (=the second potential) of the first electrode 27a becomes higher than the potential VCOM (=the reference potential) of the second electrode 27b. Accordingly, as schematically depicted by the black arrows in the drawing, a potential difference of 15 V is generated across the electrodes 27a and 27b in a direction from the first electrode 27a toward the second electrode 27b. Accordingly, the pixel section 20 is controlled by the electric field so as to display a black color.
In a memory retention period (third display period) subsequent to the first VCOM driving period, the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In synchronization with the supply of the reference potential, a third potential lower than the first potential is generated as the high-potential side power supply potential VEP to be supplied from the memory power supply control circuit 16 to the latch circuit 26, and the third potential (for example, in the range of 2 and 3 V) is output from the output terminal N2 of the latch circuit 26. In this case, the third potential corresponds to the lowest potential at which the data can be retained in the latch circuit 26. The memory retention period can be suitably set depending on the characteristics of the electrophoretic material 27c so as to maintain a display contrast. As an example, the memory retention period may be set in the range of several tens of minutes and several hours.
In a second VCOM driving period (fourth driving period) subsequent to the memory retention period, it is controlled in the same manner as that for the first VCOM driving period (second driving period). The second VCOM driving period is designed to restore the display contrast to the initial state. For this reason, the number of pulses included in the driving signal may be smaller than that for the first VCOM driving period. Thereafter, respective control operations in the third and fourth driving periods are suitably repeated so that the display contrast is maintained constant. When the power supply is cut off thereafter, the potential difference between the first and second electrodes 27a and 27b gradually decreases to 0 V.
In the memory retention period (third driving period), the potential of the first electrode 27a may be the reference potential. In such a driving method, since both the first and second electrodes 27a and 27b are at the reference potential and thus generating no potential difference between the electrodes, the pixel section 20 maintains its black displaying state at the time of the previous VCOM driving period.
Next, a driving method for displaying a white color using the pixel section 20 will be described with reference to
In the image data writing period, the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In synchronization with the supply of the reference potential, the scan-line driver 10 supplies the control signal to the gate of one of the transistors 21 to turn ON the transistor 21, and the data-line driver 13 supplies the data signal to the input terminal N1 of the latch circuit 26. Since this example is concerned with the white display, the high-potential signal is supplied as the data signal. The high-potential signal is retained in the latch circuit 26 until a subsequent data writing operation is performed to the latch circuit 26. Accordingly, the potential VSS (substantially equal to the reference potential in this example) supplied from the memory power supply control circuit 16 is output from the output terminal N2 of the latch circuit 26. In this period, the electrophoretic element 27 is charged in such a manner that the potential V1 (=VSS) of the first electrode 27a becomes substantially equal to the potential VCOM (=the reference potential) of the second electrode 27b. Accordingly, since no potential difference is generated between the electrodes 27a and 27b, the pixel section 20 maintains its previous displaying state.
In the first VCOM driving period subsequent to the image data writing period, a driving signal alternating between the reference potential and a second potential higher than the first potential is supplied from the common electrode control circuit 17 to the second electrode 27b. In synchronization with the supply of the driving signal, the low-potential side power supply potential VSS is supplied from the memory power supply control circuit 16 to the output terminal N2 of the latch circuit 26. Therefore, when the potential of the driving signal becomes equal to the second potential, the electrophoretic element 27 is charged in such a manner that the potential V1 (=VSS) of the first electrode 27a becomes equal to the potential VCOM (=the second potential) of the second electrode 27b. Accordingly, as schematically depicted by the white arrows in the drawing, a potential difference of 15 V is generated across the electrodes 27a and 27b in a direction from the second electrode 27b toward the first electrode 27a. Accordingly, the pixel section 20 is controlled by the electric field so as to display a white color. Meanwhile, when the potential of the driving signal becomes equal to the reference potential, the electrophoretic element 27 is charged in such a manner that the potential V1 of the first electrode 27a becomes substantially equal to the potential VCOM of the second electrode 27b. Accordingly, in this case, no potential difference is generated between the first and second electrodes 27a and 27b. Therefore, the pixel section 20 maintains its white displaying state.
In the memory retention period subsequent to the first VCOM driving period, the reference potential is supplied from the common electrode control circuit 17 to the second electrode 27b. Incidentally, the low-potential side power supply potential VSS supplied from the memory power supply control circuit 16 to the latch circuit 26 is not changed. The memory retention period can be suitably set depending on the characteristics of the electrophoretic material 27c so as to maintain a display contrast. As an example, the memory retention period may be set in the range of several tens of minutes and several hours.
In the second VCOM driving period subsequent to the memory retention period, it is controlled in the same manner as that for the first VCOM driving period. The second VCOM driving period is designed to restore the display contrast to the initial state. For this reason, the number of pulses included in the driving signal may be smaller than that for the first VCOM driving period. Thereafter, respective control operations in the third and fourth driving periods are suitably repeated so that the display contrast is maintained constant. When the power supply is cut off thereafter, the potential difference between the first and second electrodes 27a and 27b gradually decreases to 0 V.
In this way, in the case of using the third driving method, since a data writing operation is performed to the latch circuit 26 when the high-potential side power supply potential VEP of the memory power supply control circuit 16 is at a relatively low potential, it is not necessary to install a level shifter circuit in the data-line driver 13. Accordingly, it is possible to decrease the overall circuit size. Since the high-potential side power supply potential VEP is raised from the first potential to the third potential higher than the first potential after writing the image data, it is possible to reduce current consumption.
Moreover, relatively long memory retention period can be maintained until the second or subsequent VCOM driving period is initiated for retaining and boosting a display contrast. In this regard, it is possible to reduce current consumption.
Next, examples of electronic apparatuses including the foregoing electrophoretic device as a display section will be described.
The invention is not limited to the foregoing embodiment. Various changes can be made to the invention without departing from the scope of the invention. For example, although the foregoing embodiment has been explained with reference to the case where the invention is applied to an electrophoretic device including a plurality of pixel sections arranged in a matrix configuration, the pixel section does not necessarily have such a matrix configuration. The application field of the invention is not limited to such an electrophoretic device for displaying purpose.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-184858 | Jul 2006 | JP | national |
| 2007-075476 | Mar 2007 | JP | national |
