Patent Application
20070052032
1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) device. More particularly, it relates to an ESD device with a silicon controlled rectifier (SCR) structure and being immune from the latch-up phenomenon.
2. Description of the Related Art
Electrostatic discharge (ESD) devices are widely applied in integrated circuits (IC) to prevent them from being damaged by electrostatic discharges. In general, a latch-up effect happens to the ESD device with a silicon controlled rectifier (SCR) structure due to its congenital limitation. Once the SCR structure is triggered, a great amount of current is carried by the SCR structure, but the voltage crossing over two terminals thereof returns to a low sustained voltage. When the SCR structure is latched after being trigged, the SCR structure cannot return to its normal operating state; thus, the function provided by the ESD device will be no longer available.
Therefore, how to improve the latch-up immunity of the ESD device has become a major subject in designing ESD devices. Accordingly, an ESD device with latch-up immunity is greatly desired by the industry.
Accordingly, at least one object of the present invention is to provide latch-up immunity for an ESD device having parasitic SCR structure. To this end the equivalent SCR structure is changed in order to free the ESD device from the latch-up phenomenon whenever it occurs.
To achieve these and other advantages in accordance with the purpose of the invention, as embodied and broadly described herein, the present invention provides an ESD device with latch-up immunity, that comprises a P-type substrate, an N-type well, a first N+ doped region, a first P+ doped region, a second N+ doped region, a second P+ doped region, a third N+ doped region, a third P+ doped region, a first electrode, and a second electrode.
The N-type well is formed in the P-type substrate. The first N+ doped region and the first P+ doped region are formed in the N-type well and isolated from each other by a third field oxide layer. The second N+ doped region is formed between the first P+ doped region and a first field oxide layer. The second N+ doped region is adjacent to the first P+ doped region. The third N+ doped region is formed in the P-type substrate and outside the N-type well; and the third N+ doped region is isolated from the N-type well. The second P+ doped region is formed in the P-type substrate and outside the N-type well; and the second P+ doped region is isolated from the N-type well.
The third P+ doped region is disposed in the P-type substrate and outside the N-type well. The third P+ doped region is isolated from the second N+ doped region by the first field oxide layer. The third P+ doped region is isolated from the third N+ doped region by a fourth field oxide layer; and the third N+ doped region is isolated from the second P+ doped region by a second field oxide layer. In addition, the first electrode is electrically coupled to the second P+ doped region and the third N+ doped region through a first electric conductor, and the second electrode is electrically coupled to the first N+ doped region and the first P+ doped region through a second electric conductor.
In the present invention, the third P+ doped region is disposed in the equivalent SCR structure of the ESD device. The electrostatic discharge occurs when the supply voltage is not applied to the ESD device. The third P+ doped region is in floating status; the ESD device is working as an equivalent SCR structure. A surge occurs when the supply voltage is applied to the ESD device. The third P+ doped region is electrically coupled to a lowest potential through a switch, so that the equivalent SCR structure of the ESD device shifts to an equivalent PN diode structure, and the ESD device is free from the latch-up phenomenon.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
One embodiment below describes how to overcome the disadvantage of the conventional ESD device, and how to achieve the latch-up immunity.
The equivalent SCR structure of the ESD device 100 comprises two equivalent transistors and two internal resistors. The first P+ doped region 202a, the N-type well 106, and the P-type substrate 102 together form an equivalent PNP transistor; and the N-type well 106, the P-type substrate 102, and the third N+ doped region 202b together form an equivalent NPN transistor.
In the present embodiment, the second P+ doped region 104c and the third N+ doped region 202b outside the N-type well 106 are electrically coupled to a first electrode VSS through a first electric conductor. The second P+ doped region 104c is isolated from the third N+ doped region 202b by a second field oxide layer. In the N-type well 106, the first N+ doped region 104a, a plurality of the first P+ doped regions 202a, and a plurality of the second N+ doped regions 104b alternatively sequentially form a sequence of doped regions. The two terminals at the sequence of doped regions are the second N+ doped regions 104b. Moreover, the first N+ doped region 104a and the first P+ doped region 202a are electrically coupled to a second electrode VCC through a second electric conductor, wherein the first P+ doped region 202a is isolated from the first N+ doped region 104a by a third field oxide layer. The second N+ doped region 104b is adjacent to the first P+ doped region 202a. In addition, the aforesaid first and second electric conductors can be made of metal.
In the present embodiment, a plurality of additional third P+ doped regions 104d can be disposed in the equivalent SCR structure of the ESD device 100, wherein the third P+ doped region 104d is formed in the P-type substrate 102 and outside the N-type well 106. One terminal of the third P+ doped region 104d is isolated from the second N+ doped region 104b by a first field oxide layer, and the other terminal of the third P+ doped region 104d is isolated from the third N+ doped region 202b by a fourth field oxide layer.
In the present embodiment, the ESD device 100 further comprises a switch Ms and a resistor RS. A first terminal of the switch MS and a second terminal of the switch Ms are electrically coupled to the third P+ doped region 104d and the first electrode VSS, respectively, wherein a parasitic capacitor CP congenitally exists between a control terminal and the second terminal of the switch Ms. Moreover, two terminals of the resistor RS are electrically coupled to the control terminal of the switch MS and the second electrode VCC, respectively.
In summary, whether the supply voltage is applied or not, the ESD device 100 provided by the present invention can effectively avoid the latch-up phenomenon to improve the performance of the ESD device 100.
Although the invention has been described with reference to a particular embodiment, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed description.
