The invention relates to technology to electrostatic discharge (ESD) protection and to ESD circuit and method to protect an internal circuit from ESD current.
Electrostatic discharge (ESD) may easily damage IC devices such as DRAMs and SRAMs during both manufacture and operation. A person walking on a carpet, for instance, can carry up to several thousand volts of electrostatic charge under high relative humidity (RH) conditions and over 10,000 volts under low RH conditions. If such a person touches an IC package, the electrostatic charge on his/her body is instantly discharged to the IC package, thus causing ESD damage to the internal circuitry of the IC package. A widely used solution to this problem is to provide an on-chip ESD protection circuit around each I/O pad of the IC package.
In the usual mechanism to conduct the ESD current away is implementing an ESD circuit with the internal circuit which is to be protected from the ESD current/voltage. The ESD circuit is at the off state when no ESD event. However, when the ESD event occurs, the ESD circuit would be turn on to create a short trigger path, so that the ESD current/voltage would be conducted away without entering the internal circuit.
However, the ESD current/voltage may still a possibility in leaking to the internal circuit. How to improve the blocking capability from the ESD event for the internal circuit is still an issue in consideration for designing the ESD circuit.
The invention provides ESD circuit and method to protect an internal circuit from ESD event. The ESD event may be efficiently blocked to the internal circuit to be protected.
In an embodiment, the invention provides an ESD circuit, which is used to protect an internal circuit. The ESD circuit includes: an ESD clamp, having a first terminal connected to a power and a second terminal connected to a ground voltage; and a first switch, connected between an ESD terminal of the ESD clamp and the internal circuit. A gate of the first switch is controlled by a state signal in the ESD clamp to turn off the first switch when an ESD event occurs on the first terminal of the ESD clamp and turn on the first switch when the ESD event does not occur.
In an embodiment, as to the ESD circuit, the first terminal and the ESD terminal are a same node.
In an embodiment, as to the ESD circuit, the ESD clamp comprises a resistor and a capacitor, connected in series between the first terminal and the second terminal. An inverter is connected between the first terminal and the second terminal, wherein the inverter has an input terminal connected to a connection node between the resistor and the capacitor. A second switch is connected between the first terminal and the second terminal, wherein the second switch is controlled by an output of the inverter. The gate of the first switch is connected to one of the input terminal and the output terminal of the inverter to receive the state signal. The first switch and the second switch are opposite in conduction state.
In an embodiment, as to the ESD circuit, the first switch is a P-type MOS (PMOS) transistor and the gate of the first switch is connected to the output terminal of the inverter.
In an embodiment, as to the ESD circuit, a bulk electrode of the PMOS transistor is connected to the first terminal of the ESD clamp.
In an embodiment, as to the ESD circuit, the first switch is an N-type MOS (NMOS) transistor and the gate of the first switch is connected to the input terminal of the inverter.
In an embodiment, as to the ESD circuit, a bulk electrode of the NMOS transistor is connected to the second terminal of the ESD clamp.
In an embodiment, as to the ESD circuit, the first terminal and the ESD terminal are different nodes, wherein the first terminal receives the power for operation of the ESD clamp and the ESD terminal receives an ESD signal when the ESD signal is induced.
In an embodiment, as to the ESD circuit, the ESD clamp comprises a resistor and a capacitor, connected in series between the first terminal and the second terminal. An inverter is connected between the first terminal and the second terminal, wherein the inverter has an input terminal connected to a connection node between the resistor and the capacitor. A second switch is connected between the first terminal and the second terminal, wherein the second switch is controlled by an output of the inverter. A diode string is connected between the first terminal and the second terminal, wherein a portion of the diode string is between the first terminal and the ESD terminal. The gate of the first switch is connected to one of the input terminal and the output terminal of the inverter to receive the state signal. The first switch and the second switch are opposite in conduction state.
In an embodiment, as to the ESD circuit, the first switch is a P-type MOS (PMOS) transistor and the gate of the first switch is connected to the output terminal of the inverter.
In an embodiment, as to the ESD circuit, a bulk electrode of the PMOS transistor is connected to the first terminal of the ESD clamp.
In an embodiment, as to the ESD circuit, the first switch is an N-type MOS (NMOS) transistor and the gate of the first switch is connected to the input terminal of the inverter.
In an embodiment, as to the ESD circuit, a bulk electrode of the NMOS transistor is connected to the second terminal of the ESD clamp.
In an embodiment, the invention also provides a method to protect an internal circuit from electrostatic discharge (ESD) current. The method comprises providing an ESD clamp, having a first terminal connected to a power and a second terminal connected to a ground voltage. In addition, a first switch is provided in connection between an ESD terminal of the ESD clamp and the internal circuit. A gate of the first switch is controlled by a state signal in the ESD clamp to turn off the first switch when an ESD event occurs on the first terminal of the ESD clamp and turn on the first switch when the ESD event does not occur.
In an embodiment, as to the method, the first terminal and the ESD terminal are configured to be a same node.
In an embodiment, as to the method, the ESD clamp as provided comprises a resistor and a capacitor, connected in series between the first terminal and the second terminal. In addition, an inverter is connected between the first terminal and the second terminal, wherein the inverter has an input terminal connected to a connection node between the resistor and the capacitor. A second switch is connected between the first terminal and the second terminal. The second switch is controlled by an output of the inverter. The gate of the first switch is connected to one of the input terminal and the output terminal of the inverter to receive the state signal. The first switch and the second switch are opposite in conduction state.
In an embodiment, as to the method, the first switch is a P-type MOS (PMOS) transistor and the gate of the first switch is connected to the output terminal of the inverter.
In an embodiment, as to the method, the first switch is an N-type MOS (NMOS) transistor and the gate of the first switch is connected to the input terminal of the inverter.
In an embodiment, as to the method, the first terminal and the ESD terminal configured to be different nodes, wherein the first terminal receives a power for operation of the ESD clamp and the ESD terminal receives an ESD signal when the ESD signal is induced.
In an embodiment, as to the method, the ESD clamp as provided comprises a resistor and a capacitor, connected in series between the first terminal and the second terminal. In addition, an inverter is connected between the first terminal and the second terminal, wherein the inverter has an input terminal connected to a connection node between the resistor and the capacitor. A second switch is connected between the first terminal and the second terminal, wherein the second switch is controlled by an output of the inverter. a diode string is connected between the first terminal and the second terminal, wherein a portion of the diode string is between the first terminal and the ESD terminal. The gate of the first switch is connected to one of the input terminal and the output terminal of the inverter to receive the state signal. The first switch and the second switch are opposite in conduction state.
In order to make the aforementioned and other objectives and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The invention is directed to the ESD protection technology, in which the ESD circuit is proposed to efficiently protect the internal circuit from the ESD event with improved blocking capability.
Several embodiments are provided for describing the invention but the invention is not just limited to the embodiments. In addition, a combination between the embodiments may be made for another embodiment.
Referring to
The design of the ESD circuit would determine the ESD protection capability. To improve the ESD protection capability, the invention has firstly looked into the protection mechanism of the ESD circuit and then provide an improved design of the ESD circuit.
In a usual way, the internal circuit 60 is also connected to the terminal N1 of the ESD clamp 50. The ESD current 56 would trigger the ESD clamp 50 as a conducting state, so that the ESD clamp 50 as conducted provides a path like a short trigger path to the ground 54. The ESD current 56 would be quickly drawn to the ground 54 without entering to the internal circuit 60.
However, if the ESD clamp 50 may be not sufficiently turned on in time due to the response time of the ESD clamp 50. The ESD current 56 may still leak to the internal circuit 60, and still causing damage to the internal circuit 60.
After looking into the protection mechanism of the ESD clap 50, the invention has proposed an ESD circuit to have more capability to protect the internal circuit from the ESD event.
Referring to
With the effect of the switch 70, the ESD current 56 may be more efficiently blocked to the internal circuit 60, in which the double protection of the ESD circuit is set up.
The ESD clamp 50 in an embodiment may include a circuit structure, and the state signal NS may be provided from an ESD terminal of the ESD clamp 50 to obtain the status of the ESD event.
The ESD clamp 50 includes a trigger path 50A, an inverter path 50B, and a switch path 50C, which paths are parallel connection between the terminal N1 and the terminal N2. The trigger path 50A includes a resistor R and a capacitor C in series connection between the terminal N1 and the terminal N2. Here, the ESD terminal N3, where the ESD event may occur, is the same as the terminal N1, which may provide the usual power in operation. The inverter path 50B in an example includes an inverter as formed by two transistors as usually taken. The switch path 50C in an example is another transistor switch, which is an N-type metal-oxide-semiconductor (NMOS) transistor. The bulk electrode of the connected to the ground 54 at the terminal N2. The switch 70 in an embodiment may be PMOS transistor, of which the bulk electrode is connected to the terminal N1.
The inverter of the inverter path 50B has an input terminal connected to the connection node between the resistor R and the capacitor C in the trigger path 50A. The inverter of the inverter path 50B also has an output terminal to control the gate of the NMOS transistor of the switch path 50C. The switch 70 is connected between the terminal N1 and the internal circuit 60.
In an embodiment, the ESD current 56 would accidently enter the ESD terminal N3, which is the same as the terminal N1. The protection mechanism is following. The ESD event may refer to the ESD current (voltage) 56 in an example. The ESD event usually is an AC signal with high frequency. Due to the RC effect in the trigger path 50A, the capacitor C is operating as a short element to the ground 54. As a result, the input terminal of the inverter of the inverter path 50B has a low state as indicated by “0”, corresponding to the ground 54. The inverter path 50B inverts the low state of “0” to the high state of “1” at the output terminal. The states signal NS is at the output terminal of the inverter path 50B, then the states signal NS has the high state of “1”, which turns on the switch path 50C, operated as a short circuit to the ground 54.
Further, the states signal NS with the high state of “1” also controls the switch 70 to be turned off. In an example, the switch 70 as the PMOS transistor is different conductive type from the NMOS transistor of the switch path 50C. The states signal NS with the high state of “1” would turn off the switch 70 to additionally block the ESD current 56 to the internal circuit 60. As a result, the internal circuit 60 has more ESD protection effect from the ESD current 56.
With the similar mechanism, the switch 70 may be implemented by the NMOS transistor. Then, the state signal NS would be taken from the input terminal of the inverter.
In a further example, the ESD event may not occur at the terminal N1.
Referring to
The switch 70 is a PMOS transistor as an example similar to the switch 70 in
Likewise, the switch 70 based on the ESD circuit in
Referring to
In the foregoing description, the ESD circuit include the switch 70 which is control by the state signal NS, as obtained from the ESD clamp 50. Depending on the conductive type of the switch 70 in PMOS or NMOS, the input terminal or the output terminal of the inverter path 50B may provide the state signal NS. The ESD terminal N3 may be the same as the power terminal N1 or a signal terminal to the internal circuit 60.
Further as to a method to protect an internal circuit from electrostatic discharge current. The method in an embodiment may include providing an ESD clamp 50, having a first terminal N1 connected to a power and a second terminal N2 connected to a ground voltage, GND. In addition, a first switch 70 is provided in connection between an ESD terminal N3 of the ESD clamp 50 and the internal circuit 60. A gate of the first switch 70 is controlled by a state signal NS in the ESD clamp 50 to turn off the first switch 70 when an ESD current 56 occurs on the first terminal N1 of the ESD clamp 50 and turn on the first switch 70 when the ESD current 56 does not occur.
Although the invention is described with reference to the above embodiments, the embodiments are not intended to limit the invention. A person of ordinary skill in the art may make variations and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the invention should be subject to the appended claims.