Patent Application
20150084702
Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to electrostatic discharge (ESD) circuitry and associated techniques.
Present electrostatic discharge (ESD) circuitry may experience a high in-rush current when a power supply has a fast rise time and, in some cases, may experience oscillation from gain feedback during normal operation of a chip. Techniques and configurations to provide stable ESD protection with reduced in-rush current for a fast-rising supply may be desirable.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.
a schematically illustrates an alternative configuration of ESD circuitry, according to various embodiments.
b schematically illustrates an alternative configuration of ESD circuitry, according to various embodiments.
Embodiments of the present disclosure describe electrostatic discharge (ESD) circuitry and associated techniques and configurations. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The term “coupled” may refer to a direct connection, an indirect connection, or an indirect communication.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.
In some embodiments, the ESD clamps 102 may be formed on an active side of the die 100 using semiconductor fabrication techniques such as, for example, complementary metal-oxide-semiconductor (CMOS) technology or other suitable technology. The ESD clamps 102 may be disposed adjacent to or between power connections 104 and ground connections 106 of the die 100. For example, in some embodiments, one or more of the power connections may be coupled with the supply voltage (VDD or VSS) node in the ESD circuitry 200 of
The power connections 104 and ground connections 106 may include, for example, interconnect structures or contacts such as, for example, bumps, pillars, traces, vias, pads or other suitable structures and may be configured to respectively provide a supply voltage and ground for operation of the die (e.g., processing, sending/receiving input/output signals, storing information, executing code, etc.). As used herein, “ground” may represent any suitable voltage including non-zero voltage.
In the depicted embodiment, the power connections 104, ground connections 106 and ESD clamps 102 are disposed in a peripheral region of the die 100 and the other circuitry 110 is disposed in a central region of the die 100. In other embodiments, the power connections 104, ground connections 106, ESD clamps 102 and/or other circuitry 110 may be arranged in other suitable configurations than depicted.
According to various embodiments, the ESD circuitry 200 may include a first node, n1, coupled with VDD and GND, a first transistor, M1, coupled with the first node n1 and VDD, a second transistor, M2, coupled with the first node n1 and GND, a second node, n2, coupled with the first transistor M1 and the second transistor M2, a third transistor, M3, coupled with the second node n2 and a third node, n3, coupled with the third transistor M3. In some embodiments, the ESD circuitry 200 may further include a fourth transistor, M4, coupled with the third node n3, a fifth transistor, M5, coupled with the third node n3, a sixth transistor M6 coupled with the third node n3, a seventh transistor M7 coupled with the third node n3 and a latch node configured to couple the fourth transistor M4 with the third node n3, as can be seen.
In some embodiments, the first node n1 may be coupled with an inverter including the first transistor, M1, and the second transistor, M2, as can be seen. The first node n1 may be coupled with a gate of the first transistor M1 and the second transistor M2, a source of the first transistor M1 may be coupled with VDD, a source of the second transistor M2 may be coupled with GND, and a drain of the first transistor M1 may be coupled with a drain of the second transistor M2, as can be seen. The second node n2 may be coupled with a drain of the first transistor M1 and a drain of the second transistor M2.
In some embodiments, the third transistor M3 may serve as a source follower. The second node n2 may be coupled with a gate of the third transistor M3. A drain of the third transistor M3 may be coupled with VDD. The third node n3 may be coupled with a source of the third transistor M3 and a drain of the fourth transistor M4. A source of the fourth transistor M4 may be coupled with GND. In some embodiments, the third node n3 may be coupled with a gate of the fifth transistor M5, a gate of the sixth transistor M6 and a gate of the seventh transistor M7. The latch node may be coupled with a drain of the sixth transistor, a drain of the seventh transistor and a gate of the fourth transistor.
According to various embodiments, one or more resistors and/or capacitors may be coupled to one or more of the first node n1 and the third node n3. A resistance or capacitance of the nodes n1 and/or n3 may be based, at least in part, on the one or more resistors or capacitors. For example, a resistance of the first node n1 may be determined based on one or more resistors (hereinafter “R1”) coupled with the first node n1 and a capacitance of the first node n1 may be determined based on one or more capacitors (hereinafter “C1”) coupled with the first node n1. Resistance and capacitance of the third node n3 may be determined based on one or more resistors (hereinafter “R2”) and one or more capacitors (hereinafter “C2”) coupled with the third node n3. In some embodiments, capacitance of the third node n3 may be primarily based on a gate capacitance of the fifth transistor M5 and capacitors such as C2 may not be needed in the ESD circuitry 200.
According to various embodiments, R1 and C1 may be tuned or configured to provide a first time period (e.g., constant, τ1) to charge the first node n1. R2 and C2 may be tuned configured to provide a second time period (e.g., constant, T2) to discharge the third node n3. In some embodiments, the first time period (e.g., τ1) may be less than the second time period (e.g., τ2) to provide ESD circuitry 200 of a transient ESD clamp having improved stability and reduced in-rush current relative to other transient ESD clamps. For example, a shorter first time period (e.g., τ1) may limit in-rush current to the ESD circuitry 200 and a longer second time period (e.g., τ2) may allow complete discharge of an external ESD capacitance (e.g., 100 picoFarads for human body model) through the ESD circuitry 200. The ESD circuitry 200 may have the stability of a 1-inverter clamp and maintain ESD protection level while reducing in-rush current by a factor of about 105 for a 1 microsecond (μs) rise time supply.
In some embodiments, the first time period may begin when VDD is turned on to provide a supply voltage and end when C1 has charged to a point where the second node n2 is low enough to turn off the third transistor M3. The second time period may begin when the third transistor M3 is set to an off-state and may end when the fourth transistor M4 is set to an on-state (normal power-up). The first time period and second time period may be configured using other suitable techniques in other embodiments.
In some embodiments, the second time period may be about an order of magnitude longer than the first time period. For example, in some embodiments, the second time period may be at least seven times greater than the first time period. In some embodiments, the first time period may have a value from 30 nanoseconds (ns) to 300 ns and the second time period may have a value from 300 ns to 3000 ns. In one embodiment, the first time period may be about 40 ns and the second time period may be about 800 ns. In another embodiment, the first time period may be 100 ns and the second time period may be about 1000 ns. In one embodiment, the first time period may be 180 ns and the second time period may be 1230 ns. In one embodiment, the first time period has a value less than 1 microsecond and the second time period is greater than the first time period. The first time period and the second time period may have a wide variety of other suitable values in other embodiments.
According to some embodiments, R1 and C1 may create a shorter first time period, which may only allow the voltage of the second node n2 to go high when VDD (e.g., 5 volt (V)) has a fast rise time (e.g., less than 1 μs). When the voltage of second node n2 goes high, the third transistor M3 may turn on and pull a voltage of the third node n3 up such that the fifth transistor M5 can sink the ESD current (e.g., ˜1.33 amperes (A) in some embodiments). The first time period may cause the voltage of the second node n2 to quickly go low, turning off the third transistor M3. The longer second time period created by R2 and C2 (and/or gate capacitance of fifth transistor M5) may discharge a voltage of the third node n3 at a slower rate. Using the first time period and second time period in this manner may limit in-rush current while allowing complete discharge of an external ESD capacitor (e.g., 100 picoFarads for human body model) through the ESD circuitry 200. A gate capacitance of the fifth transistor M5 may be greater than a gate capacitance of other transistors in the ESD circuitry 200 in order to advantageously tune the longer second time period to discharge the third node n3. Using the gate capacitance of the fifth transistor to primarily provide capacitance for tuning the second time period may save area on the die (e.g., die 100 of
In a first embodiment of the ESD circuitry 200, the first transistor M1 may have a width of 40 microns and a channel length of 0.6 microns, the second transistor M2 may have a width of 10 microns and a channel length of 0.6 microns, the third transistor M3 may have a width of 40 microns and a channel length of 0.6 microns, the fourth transistor M4 may have a width of 10 microns and a channel length of 0.6 microns, the fifth transistor M5 may have a width of 2000 microns and a channel length of 0.6 microns, the sixth transistor M6 may have a width of 2 microns and a channel length of 0.6 microns and the seventh transistor M7 may have a width of 10 microns and a channel length of 0.6 microns. In the first embodiment, R1 may have an effective resistance of 400,000 ohms and R2 may have an effective resistance of 200,000 ohms.
In other embodiments, the transistors (e.g., M1, M2, etc.) and/or resistors (e.g., R1, R2) may have other suitable values. The other suitable values may include different nominal values than described above, but may have a same relative value (e.g., greater or less than) when compared with other transistors or resistors of the ESD circuitry 200. For example, in some embodiments, the width of the first transistor may be greater than the width of the second transistor, which may increase a switching point of the inverter formed by transistors M1 and M2. The fifth transistor M5 may have a width that is substantially larger than the width of the other transistors in the ESD circuitry 200. The sixth transistor M6 may have a width that is less than a width of the seventh transistor M7, which may decrease a switching point of the inverter formed by transistors M6 and M7.
In a second embodiment of the ESD circuitry 200, the first transistor M1 may have a width of 40 microns and a channel length of 0.7 microns, the second transistor M2 may have a width of 10 microns and a channel length of 0.7 microns, the third transistor M3 may have a width of 20 microns and a channel length of 0.7 microns, the fourth transistor M4 may have a width of 10 microns and a channel length of 0.7 microns, the fifth transistor M5 may have a width of 2880 microns and a channel length of 0.7 microns, the sixth transistor M6 may have a width of 2 microns and a channel length of 0.7 microns and the seventh transistor M7 may have a width of 10 microns and a channel length of 0.6 microns. In the second embodiment, R1 may have an effective resistance of ˜400,000 ohms and R2 may have an effective resistance of ˜200,000 ohms. In other embodiments, the transistors (e.g., M1, M2, etc.) and/or resistors (e.g., R1, R2) may have other suitable values.
The eighth transistor M8 may include a source coupled with VDD, a drain coupled with the first node n1 and a gate coupled with GND, as can be seen. In some embodiments, the eighth transistor M8 may be a P-type field effect transistor (PFET). Replacing R1 of the ESD circuitry 200 with the eighth transistor M8 may reduce die area in the ESD circuitry 300 relative to the ESD circuitry 200.
The ninth transistor M9 may include a source coupled with GND, a drain coupled with the third node n3 and a gate coupled with the third node n3, as can be seen. In some embodiments, the ninth transistor M9 may be a zero threshold voltage transistor. Replacing R2 of the ESD circuitry 300 with the ninth transistor M9 may reduce die area in the ESD circuitry 400 relative to the ESD circuitry 300.
The tenth transistor M10 may include a source coupled with GND, a drain coupled with GND and a gate coupled with the first node n1, as can be seen. The eleventh transistor M11 may include a source coupled with GND, a drain coupled with GND and a gate coupled with the third node n3, as can be seen. A gate capacitance of the tenth transistor M10 and eleventh transistor M11 may be configured, tuned or selected to provide a first time period (e.g., τ1) of the first node n1 and a second time period (e.g., τ2) of the third node n3 as described in connection with ESD circuitry 200 of
In an embodiment corresponding with the first embodiment described in connection with the ESD circuitry 200 of
The triple-well transistor TWL may include a source coupled with the third node n3, a drain coupled with VDD and a gate coupled with the second node n2, as can be seen. Further, a body of the triple-well transistor TWL may be coupled with the third node n3, as can be seen. In some embodiments, the triple-well transistor TWL may be an isolated transistor, e.g., a body of the transistor is isolated from the bulk silicon. In some embodiments, the triple-well transistor TWL may be isolated from the bulk by means of a silicon-on-insulator (SOI) process. In some embodiments, the triple-well transistor may be an SOI transistor. In some embodiments, the triple-well transistor TWL may be an N-type FET (NFET). In some embodiments, replacing the third transistor M3 of
The bipolar transistor Q1 may include an emitter coupled with the third node n3, a collector coupled with VDD and a base coupled with the second node n2, as can be seen. In some embodiments, the bipolar transistor Q1 may be formed according to a BiCMOS process. In some embodiments, replacing the third transistor M3 of
a schematically illustrates an alternative configuration of ESD circuitry 800a, according to various embodiments. The ESD circuitry 800a may represent a reconfiguration of the ESD circuitry 200 of
b schematically illustrates an alternative configuration of ESD circuitry 800b, according to various embodiments. The ESD circuitry 800b may represent a simplified configuration of the ESD circuitry 200 of
As can be seen, the current peaks at 250 μA or less. The supply voltage (e.g., VDD of ESD circuitry 200) may reach a peak voltage of about 5.5V and may quickly discharge without oscillating as may occur with ESD circuitry including multiple inverters. A first peak in time may correspond with the first time period (e.g., τ1) and the second peak in time may correspond with the second time period (e.g., τ2). The current drops to ˜0 μA at ˜1 μs when the latch node goes high, pulling node n3 to GND.
Referring to
At 1102, the method 1100 may include coupling a first node (e.g., first node n1 of
At 1112, the method 1100 may include coupling a third node (e.g., third node n3 of
At 1122, the method 1100 may include coupling a latch node (e.g., latch node of
Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
Embodiments of ESD circuitry described herein, and apparatuses (e.g., die 100 of
The power amplifier module 1202 may receive an RF input signal, RFin, from the transceiver 1204. The power amplifier module 1202 may amplify the RF input signal, RFin, to provide the RF output signal, RFout. The RF input signal, RFin, and the RF output signal, RFout, may both be part of a transmit chain, respectively noted by Tx−RFin and Tx−RFout in
The amplified RF output signal, RFout, may be provided to an antenna switch module (ASM) 1206, which effectuates an over-the-air (OTA) transmission of the RF output signal, RFout, via an antenna structure 1208. The ASM 1206 may also receive RF signals via the antenna structure 1208 and couple the received RF signals, Rx, to the transceiver 1204 along a receive chain.
In various embodiments, the antenna structure 1208 may include one or more directional and/or omnidirectional antennas, including, e.g., a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a microstrip antenna or any other type of antenna suitable for OTA transmission/reception of RF signals.
The system 1200 may be any system including power amplification. Circuitry of the die 100 may provide an effective switch device for power-switch applications including power conditioning applications such as, for example, Alternating Current (AC)-Direct Current (DC) converters, DC-DC converters, DC-AC converters, and the like. In various embodiments, the system 1200 may be particularly useful for power amplification at high radio frequency power and frequency. For example, the system 1200 may be suitable for any one or more of terrestrial and satellite communications, radar systems, and possibly in various industrial and medical applications. More specifically, in various embodiments, the system 1200 may be a selected one of a radar device, a satellite communication device, a mobile handset, a cellular telephone base station, a broadcast radio, or a television amplifier system.
Although certain embodiments have been illustrated and described herein for purposes of description, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims and the equivalents thereof.
