Patent Application
20160190800
Embodiments of the disclosure relate to semiconductor integrated circuits to protect such circuits from electrostatic discharge (ESD).
Semiconductor integrated circuits utilizing high impedance transistor technologies such as metal oxide semiconductor (MOS) technologies are known to be vulnerable to ESD. ESD “events” may include the so-called “human body model” (HBM) type of event. See e.g., JEDEC Standard JS-001-2012, JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST—HUMAN BODY MODEL (HBM)—COMPONENT LEVEL (2012) for additional information about HBM. A person may accumulate static electrical charge on the surface of his or her body, generally through the rubbing together of dissimilar articles of clothing, shoes rubbing against carpet, clothing rubbing against a car seat when entering or exiting a vehicle, etc., particularly at times of low relative humidity. An HBM ESD event occurs when the person subsequently touches a conductor, including perhaps an electronic circuit and discharges the accumulated charge to and through circuit components. Such components may be subject to damage by a resulting discharge pulse of 1000 volts or more with a discharge time of several hundred nanoseconds.
The ESD protection circuits include a trigger circuit having a resistor and a capacitor to sense an ESD strike. Such ESD RC trigger circuit (or ESD clamp) turns on falsely during fast power rise. This induces self-damage, or damage elsewhere in the circuitry. The system on chips (SoCs) with fast power rise have to either add board components, which add costs, or limit power rise to solve this problem. One way to solve this problem is to use RC (resistor capacitor) trigger with desensitized RC. This clamp desensitizes RC trigger to improve clamp response, but clamp still leaks current. Existing ESD clamps employ RC transient triggers, which work on the ESD rise edge. Problem occurs with fast rising power and when the clamp produces leakage current.
Various aspects of the disclosure provides electrostatic discharge (ESD)-triggered protection apparatus having an ESD trigger circuit including a set of diodes coupled to a resistor. The set of diodes is configured to be forward biased in response to a threshold level of the ESD pulse. An ESD discharge device is coupled to the ESD trigger circuit. Further, a pre-driver circuit coupled between the ESD trigger circuit and the ESD discharge device.
Other aspects and example embodiments are provided in the Drawings and the Detailed Description that follows.
The ESD protection apparatus 100 also includes an ESD discharge device 120 communicatively coupled to the ESD trigger circuit 110. The ESD discharge device 120 operates in response to the switching pulse to transfer a current generated by the ESD pulse 115 to a ground rail 125. The protection apparatus 100 also includes a pre-driver circuit 105 having an inverting buffer 128 and a set of inverters 130 communicatively coupled between the ESD trigger circuit 110 and the ESD discharge device 120. The pre-driver circuit 105 propagates the switching pulse from the ESD trigger circuit 110 to the ESD discharge device 120.
Referring now to
The pre-driver circuit 105 is coupled to the ESD discharge device 120. The ESD discharge device 120 includes a power MO SFET transistor 120 having a conduction channel with a width sufficient to transfer the current generated by the ESD pulse 115 to ground rail. Although reference is made in this disclosure to the power MOSFET transistor 230 as the ESD discharge device 120, it is noted that other implementations of the ESD discharge device 120 are contemplated herein.
As such, the ESD trigger circuit 110 is designed to initiate a switching cascade through the protection apparatus 200 in order to cause the ESD discharge device 120 to begin dissipating energy associated with the ESD pulse 115. The ESD trigger circuit 110 is implemented as a voltage level based trigger, meaning, the set of diodes 205 are configured to be forward biased in response to a threshold level of the ESD pulse 115. During fast power rise, an RC based ESD trigger gives a false trigger. Since, the ESD trigger circuit 110 is implemented with the set of diodes, the diodes are forward biased only at a threshold level of the ESD pulse 115, and thus avoiding the false triggering problem associated with RC based ESD trigger circuits. The occurrence of an ESD event resulting in an ESD pulse 115 causes a large initial voltage drop across trigger circuit resistor 210. The voltage drop across trigger circuit resistor 210 forward biases PMOS transistor 220, resulting in a positive pulse at the output. This positive pulse is then propagated through the inverters 130 to forward bias the ESD discharge device (power MOSFET transistor 225). The power MOSFET transistor 225 opens a low resistance, high current capacity channel through which to discharge the energy produced by the ESD pulse 115.
Referring now to
Referring now to
It is noted that the ESD protection apparatus according to various embodiments can be employed in a variety of electronic devices such as microprocessors, application specific integrated circuits (ASICs), microcontrollers, and systems on chip (SoC). Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.
The forgoing description sets forth numerous specific details to convey a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. Well-known features are sometimes not described in detail in order to avoid obscuring the invention. Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of invention not be limited by this Detailed Description, but only by the following Claims.
