Patent Application
20230378165
The present invention relates generally to the electrical, electronic and computer arts, and, more particularly, to electrostatic discharge protection devices and fabrication methods.
Electrostatic discharge (ESD) is often recognized as one of the biggest threats to sensitive electronic devices, such as mobile phones, etc. An ESD event generally involves charge transfer between a device and an external body due to electrostatic potential difference. During an ESD event, large currents can pass through the pins of an integrated circuit (IC) for very short durations of time causing electrical and thermal overstress and resulting internal damage. Such internal damage can wholly or partly impair the functionality of the device or its operational lifetime. ESD sensitivity testing is in wide use for quantifying susceptibility of devices to damage in various environments. Such tests emulate ESD events in a controlled fashion by subjecting the device under test to transient electrical overstress for various discharge pathways. Hence, building ESD protection into electronic devices and establishing its efficacy through sensitivity testing has become a routine part of the product development process.
For ESD protection of IC devices, various protection elements are added to augment core circuitry in the device. A widely used method of ESD protection employs a power clamp coupled between positive and negative voltage supply nodes in combination with individual protection elements to provide bidirectional current discharge paths between each of the pins and one or more of the voltage supply nodes. A discharge path in effect diverts large discharge currents away from vulnerable internal circuitry. For this to be effective, the discharge path must be fast acting and be of sufficiently low impedance so that the terminal voltage is limited to a tolerable level during the ESD event.
Power clamps can generally be classified as static or transient according to their manner of operation. A static clamp limits voltage rise by conducting when the terminal voltage exceeds a predetermined level. Such clamps are often set to a threshold level higher than the specified absolute maximum power supply voltage with the addition of an adequate margin to avoid false activation during normal operation. Thus, terminal voltage can reach well in excess of the maximum rated supply voltage during an ESD event, which often limits the utility of static clamps. Further, as in the case of diode-based static clamps, resistive voltage drops from large discharge currents will cause the terminal voltage to reach even higher levels than the threshold, thereby exacerbating the problem.
Alternatively, a transient clamp dynamically turns on during a voltage surge arising from discharge events. A resistor-capacitor (RC) trigger circuit is typically employed for detecting fast transients and in turn switching on a large-sized transistor that bypasses discharge currents. This method is effective in limiting the voltage rise during ESD events to a few volts and is widely adopted in complementary metal-oxide-semiconductor (CMOS) circuits.
In a radio frequency (RF) power amplifier (PA) application, the positive voltage supply (VDD) terminal is vulnerable during RF fast switching/swings against voltage spikes, such as spikes generated from parasitic inductor and/or capacitors. Therefore, ESD devices are often used to protect the terminal to prevent device failure. Unfortunately, however, the use of conventional ESD devices typically increases overall leakage current in the device. Such increased leakage current, particularly from the positive voltage supply terminal, contributes to the total power dissipation in the RF PA, which results in performance degradations in the RF PA and ultimately lowers the overall efficiency of the RF PA (a critical performance parameter), which is undesirable.
The present invention, as manifested in one or more embodiments, provides an ESD protection device that advantageously reduces overall leakage current in the device, thereby beneficially enhancing performance (e.g., efficiency), particularly in an RF PA application, among other applications. One or more embodiments of the invention employs an ESD protection device including at least one ground-gate n-type metal-oxide semiconductor (ggNMOS) device having multiple pairs of PN stripes in a source region of the device. This arrangement provides a plurality of distributed parasitic bipolar junction transistors (BJTs) which establish current discharge paths during an ESD event, but exhibit very low leakage current during normal operation of the ESD protection device.
In accordance with an embodiment of the invention, an electrostatic discharge (ESD) protection device includes a deep well having a first conductivity type, a well having the first conductivity type disposed in at least a portion of the deep well, proximate an upper surface of the deep well, and a drain region having a second conductivity type disposed in a portion of the deep well, proximate the upper surface of the deep well, the second conductivity type being opposite in polarity to the first conductivity type. A source structure is disposed in at least a portion of the well, proximate an upper surface of the well and spaced laterally from the drain region. The source structure includes multiple pairs of stripe regions, each of the stripe regions including a doped region of the first conductivity type and a doped region of the second conductivity type disposed laterally adjacent to one another. A gate is disposed over at least a portion of the well, between the drain region and the source structure, the gate being electrically isolated from the well by a dielectric layer disposed between the well and the gate. The doped regions of the first and second conductivity types are electrically coupled together, and the drain region is adapted for connection to an input/output pad to be protected from an ESD event.
In accordance with another embodiment of the invention, a method of fabricating an ESD protection device includes: forming a deep well having a first conductivity type; forming a well having the first conductivity type in at least a portion of the deep well, proximate an upper surface of the deep well; forming a drain region having a second conductivity type in a portion of the deep well, proximate the upper surface of the deep well, the second conductivity type being opposite in polarity to the first conductivity type; forming a source structure in at least a portion of the well, proximate an upper surface of the well and spaced laterally from the drain region, the source structure comprising a plurality of pairs of stripe regions, each of the stripe regions including a doped region of the first conductivity type and a doped region of the second conductivity type disposed laterally adjacent to one another; and forming a gate over at least a portion of the well, between the drain region and the source structure, the gate being electrically isolated from the well by a dielectric layer formed between the well and the gate. The doped regions of the first and second conductivity types in the plurality of pairs of stripe regions are electrically coupled together, and the drain region is adapted for connection to an input/output pad to be protected from an ESD event.
Techniques of the present invention can provide substantial beneficial technical effects. By way of example only and without limitation, an ESD protection device according to one or more embodiments of the invention may provide one or more of the following advantages:
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The patent or patent application file contains at least one drawing executed in color. Copies of this patent application or patent application publication with color drawing(s) will be provided by the U.S. Patent and Trademark Office upon request and payment of the necessary fee.
Non-limiting and non-exhaustive embodiments of the present invention will be described with reference to the following drawings which are presented by way of example only, wherein like reference numerals (when used) indicate corresponding elements throughout the several views unless otherwise specified, and wherein:
It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments.
Principles of the present invention, as manifested in one or more embodiments, will be described herein in the context of an illustrative electrostatic discharge (ESD) protection device, and methods for fabricating an ESD protection device, having multiple pairs of PN stripes. The ESD protection device according to embodiments of the invention is well-suited for power applications, such as, for example, a radio frequency (RF) power amplifier (PA) application, among other beneficial uses. It is to be appreciated, however, that the invention is not limited to the specific device(s) and/or method(s) illustratively shown and described herein. Rather, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the claimed invention. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.
For the purpose of describing and claiming embodiments of the invention, the term MISFET, as may be used herein, is intended to be construed broadly and to encompass any type of metal-insulator semiconductor field-effect transistor. The term MISFET is, for example, intended to encompass semiconductor field-effect transistors that utilize an oxide material as their gate dielectric (i.e., metal-oxide semiconductor field-effect transistors (MOSFETs)), as well as those that do not. In addition, despite a reference to the term “metal” in the acronyms MISFET and MOSFET, the terms MISFET and MOSFET are also intended to encompass semiconductor field-effect transistors wherein the gate is formed from a non-metal material such as, for instance, polysilicon; the terms “MISFET” and “MOSFET” are used interchangeably herein.
Although the overall fabrication method and structures formed thereby are entirely novel, certain individual processing steps required to implement a portion or portions of the method(s) according to one or more embodiments of the invention may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to those having ordinary skill in the relevant arts. Moreover, many of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: P. H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008; and R. K. Willardson et al., Processing and Properties of Compound Semiconductors, Academic Press, 2001, which are incorporated by reference herein in their entireties. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative and one skilled in the art may be familiar with several equally suitable alternatives that would also fall within the scope of the present invention.
It is to be understood that the various layers and/or regions shown in the accompanying figures are not necessarily drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for economy of description. This does not imply, however, that the semiconductor layer(s) not explicitly shown are omitted in the actual device or structure.
The ESD protection device 100 includes a gate 110, which may be formed of polysilicon material, disposed above the upper surface of the p-well 104, between the source and drain regions 106, 108. The gate 110 is electrically isolated from the p-well 104 by a thin dielectric layer 112, which is typically formed of an oxide and therefore referred to as a gate oxide layer. As will be known by those skilled in the art, when the gate 110 is more positive relative to the source region 106, it attracts electrons, inducing an n-type conductive channel in the p-well 104 below the gate oxide layer 112, which allows electrons to flow between the n-doped source and drain regions 106, 108 in the ESD protection device 100.
A heavily-doped p-type region (P+) 114 is formed in the p-well 104, proximate the upper surface of the p-well and adjacent to the source region 106. The p-type region 114 can be formed using an implant process. The p-type region 114, which is electrically coupled with the p-well 104, serves as bulk connection in the ESD protection device 100.
In an ESD protection application, gate (G), source (S) and bulk (B) terminals are all connected to ground (GND), as the ggNMOS name implies. A drain (D) terminal of the device 100 is connected to an input/output (I/O) pad under protection. A parasitic NPN bipolar junction transistor (BJT), Q1, is formed, with the n-type drain region 108 serving as a collector (C) of Q1, the p-type body region in the p-well 104 serving as a base (B) of Q1, and the n-type source region 106 serving as an emitter (E) of Q1. A key element to the operation of the ggNMOS transistor as an ESD protection device is a parasitic base resistance, RB, present between the emitter and base terminals of the parasitic NPN BJT Q1. This parasitic resistance RB is a result of the finite conductivity of the p-well 104.
In terms of a basic operation of the ESD protection device 100, when a positive ESD event is present on the I/O pad (drain terminal), the collector-base junction of the parasitic NPN BJT Q1 becomes reverse biased to the point of avalanche breakdown. At this point, the positive current flowing from the base to ground through the parasitic resistance RB induces a voltage potential across RB, thereby causing a positive voltage difference to appear across the base-emitter junction of transistor Q1. When this voltage difference exceeds a prescribed threshold of transistor Q1 (e.g., about 0.7 volt), the base-emitter junction will become forward-biased, triggering the parasitic NPN BJT Q1. With the parasitic NPN BJT Q1 turned on, a current path will be established between the collector and emitter for discharging ESD current in the device 100. In this manner, the ESD protection device 100, particularly in an RF PA application, protects the drain terminal from parasitic voltage spikes.
As previously stated, however, the use of conventional ESD devices typically increases overall leakage current in the circuit. Such increased leakage current, particularly in a power amplifier context, decreases the overall gain and causes performance degradations in the RF PA, which ultimately lowers the overall efficiency of the amplifier. Moreover, the ESD leakage current is generally process, voltage and/or temperature (PVT) dependent, which introduces another source of undesirable variation.
In order to reduce leakage current within a technology platform resulting from the use of ESD protection devices, one or more embodiments of the invention employ an ESD protection device including at least one NMOS transistor device having multiple pairs of PN stripes.
In this exemplary embodiment, the deep well 202 is of p-type conductivity (e.g., boron dopant) and will thus be referred to as a deep p-well (DPW). A resistivity of the DPW 202 is preferably less than about 1-10 ohms-centimeter (Ω·cm), and a cross-sectional thickness (i.e., depth) of the DPW is about 2 μm, although embodiments of the invention are not limited to any specific resistivity or depth of the DPW. It is to be appreciated that when a grounded-gate p-type metal-oxide semiconductor (ggPMOS) transistor is used as the primary ESD protection device, a deep n-well (DNW) may be employed in place of the DPW 202, as will become apparent to those skilled in the art.
A well 204 is formed in a portion of the DPW 202, proximate an upper surface of the DPW. The well 204 is shallower in depth compared to the DPW 202, such as about 0.5 μm to 1.0 μm, depending on the ESD design parameters. In this illustrative embodiment, the well 204 is preferably a p-type well (e.g., formed by implanting a p-type dopant, such as boron, into a defined portion of the DPW 202, flowed by annealing), and is thus referred to herein as a p-well. A resistivity of the p-well 204 is preferably about 0.05 Ω·cm, although embodiments of the invention are not limited to any specific resistivity.
A highly-doped drain region 206 of n-type conductivity (N+) is formed in the DPW 102 proximate the upper surface of the DPW. The ESD protection device 200 further includes a source structure formed in the p-well 204 proximate an upper surface of the p-well and spaced laterally from the drain region 206. The source structure comprises a plurality of pairs (e.g., three, as in the illustrative ESD protection device 200) of alternating heavily doped n-type (N+) and heavily doped p-type (P+) regions that are laterally adjacent to one another, referred to herein as PN stripes. Each of the doped N+ and P+ regions 208 through 218 forming the pairs of PN stripes are preferably formed by implantation and annealing (to drive in the impurity), in one or more embodiments.
More particularly, the source structure in the illustrative ESD protection device 200 includes a first doped n-type (N+) source region 208, a first doped p-type (P+) body (i.e., bulk) region 210 disposed directly adjacent to the first N+ source region 208, a second doped n-type source region 212 disposed directly adjacent to the first P+ body region 210, a second doped p-type body region 214 disposed directly adjacent to the second N+ source region 212, a third doped n-type source region 216 disposed directly adjacent to the second P+ body region 214, and a third doped p-type body region 218 disposed directly adjacent to the third N+ source region 216. The plurality of alternating N+ source regions 208, 212, 216 and P+ body regions 210, 214, 218 extend from an edge of the gate 220 in a z-direction within the p-well 204. Collectively, the N+ source regions 208, 212 and 216 serve as a distributed source in the NMOS device of the ESD protection device 200. Likewise, the P+ body regions 210, 214 and 218 collectively serve as a distributed body/bulk connection of the NMOS device.
The ESD protection device 200 further includes a gate 220, which may be formed of polysilicon material, disposed above the upper surface of the p-well 204, between the first source region 208 and the drain region 206. The gate 110 is electrically isolated from the p-well 204 by a thin dielectric layer 222, which may be formed of an oxide (e.g., silicon dioxide) and therefore referred to as a gate oxide layer. As will be known by those skilled in the art, when the gate 220 is more positive relative to the source (208, 212, 216) of the NMOS device, it attracts electrons, inducing an n-type conductive channel in the p-well 204 below the gate oxide layer 222, which allows electrons to flow between the n-doped drain region 206 and the n-doped source structure 208, 212, 216 in the ESD protection device 200.
In an ESD protection application, the NMOS device is preferably arranged in a grounded-gate configuration, whereby gate (G), source (S) and body/bulk (B) terminals of the NMOS device are all connected to ground (GND), as the ggNMOS name implies. A drain (D) terminal of the NMOS device in the ESD protection device 200 is connected to an input/output (I/O) pad under protection. With multiple pairs of PN stripes, the NMOS device will form multiple parasitic NPN BJTs, with the n-type drain region 206 serving as a common collector (C) of each parasitic BJT, and the n-type source regions 208, 212, 216 serving as an emitter (E) of the respective parasitic BJTs, as shown in
With reference now to
Each parasitic NPN BJT Q1, Q2, Q3 can work independently to divert ESD current during an ESD pulse event, and paralleling each of the parasitic NPN BJTs will enhance the overall capabilities of ESD protection from various sources such as thermal, leakage, etc. During an ESD event, such as when a positive ESD pulse is present on the drain I/O pad, the PN junction between the body and drain regions is reversed-biased to its breakdown avalanche state. An avalanche current, ICBS1, ICBS2 and ICSS3, will flow from the collector to the base of each NPN BJT, Q1, Q2 and Q3, respectively, and through the base resistor, RB1, RB2 and RB3, to the source, which is grounded.
The avalanche current ICBS1, ICBS2 and ICSS3 flowing through the respective base resistors RB1, RB2 and RB3, respectively, will cause a voltage drop to develop across each of the base resistors. Once this voltage drop across the base resistor exceeds a threshold voltage of the parasitic NPN BJT (e.g., VBE≥0.7 V), snapback will occur in the BJT, wherein the base-emitter junction is in a forward bias state with base current IB; that is, snapback is a mechanism in a BJT in which avalanche breakdown (or impact ionization) generates a sufficient base current to turn on the transistor. At this point, when the parasitic NPN BJT is turned on, a significant collector current, IC, will flow, which is modulated by β·IB, where β is a gain of the parasitic NPN BJT. This collector current IC flowing from the I/O pad (drain) to ground, through the source of the NMOS device, diverts the ESD current and clamps the voltage at the drain terminal, thereby protecting the I/O pad from damage due to the ESD event. This type of ESD protection device is bidirectional; that is, when a negative ESD pulse occurs on the drain I/O pad, the parasitic NPN BJTs are in a forward-bias condition. Thus, the device I/O terminals are again protected from ESD damages.
With reference again to
By way of example only and without limitation,
In
The I-V curves shown in
With reference to
As an unexpected result, the benefit to using multiple pairs of PN stripes is not necessarily linear. For example, using three pairs of PN stripes in this illustrative embodiment provides lower leakage current than using five pairs of PN stripes (which provides only a marginal reduction in leakage current compared to the single pair case), at least under a prescribed set of device parameters. Furthermore, when stripe lengths for the doped N+ source regions and P+ body regions are not equal to one another (i.e., LS≠LP), simulation data shows larger leakage current compared to using equal stripe lengths (i.e., LS=LP), with all other parameters being the same.
By way of example only and without limitation,
In
After snapback occurs, when the parasitic BJT is operating in a forward bias state, there is a slightly more pronounced separation between the various I-V curves, evidencing the impact of PN stripe size on hold voltage. In this example, the hold voltage VHOLD varies in a range of about 8.6-9.3 volts, depending on the PN stripe size. As apparent from
The I-V curves shown in
As apparent from
As an unexpected result in this example scenario, leakage current in the ESD protection device does not appear to vary linearly or monotonically with PN stripe length. For example, using three pairs of PN stripes, although a PN stripe length of 0.9 μm provides the highest leakage current, the next highest leakage current is obtained using a PN stripe length of 1.0 μm, followed by PN stripe lengths of 0.6 μm, 0.4 μm, and 0.8 μm (in order of decreasing leakage current), with 0.8 μm providing the lowest leakage current among the PN stripes sizes used in the simulations. This observation shows that leakage currents are a more complicated function of the two variables; number of pairs of PN stripes and sizes of PN stripes, among other parameters. Using unequal N+ and P+ stripe lengths (LS, LP) would introduce additional complexity into the leakage current optimization function.
For example, the ESD protection device 800 shown in
The color gradations in
By way of example only and without limitation,
The x-axis in each of the graphs represents the collector voltage (in volts), VC, of the parasitic BJT in the ESD protection device, measured at the I/O pad (i.e., NMOS drain terminal), and the y-axis represents the collector current (in A/mm) in the parasitic BJT; the y-axis is linear in
In
After snapback occurs, when the parasitic BJT is operating in a forward bias state, there is a more pronounced separation between the various I-V curves, evidencing the impact of PN stripe size and/or number of pairs of PN stripes on hold voltage. In this example, the hold voltage VHOLD varies in a range of about 7.6 to 8.6 volts, depending on the number of pairs of PN stripes and PN stripe size. As apparent from
The I-V curves shown in
As apparent from
As an unexpected result in this example scenario, leakage current in the ESD protection device does not seem to vary linearly or monotonically with the number of pairs of PN stripes, given a fixed total length of PN stripes of 4.8 μm. For example, as stated above, using three pairs of PN stripes provides the lowest leakage current, but the next lowest leakage current is achieved using a single pair of PN stripes, with the highest leakage current exhibited using five pairs of PN stripes among the PN stripes sizes used in the simulations. Again, this observation shows that leakage current optimization is a more complicated function involving more than just two variables; number of pairs of PN stripes and sizes of PN stripes.
Another factor that can impact leakage current in the ESD protection device is the distance, d, between the edge of the drain region (e.g., drain region 206 shown in
The curves shown in
The impact of gate to drain distance d on hold voltage in the ESD protection device after snapback occurs is evident and appears to exhibit a fairly linear relationship. With reference to
In
Although not explicitly shown in the figures, simulation scenarios varying gate length LG while keeping the other parameters constant (e.g., using three pairs of PN stripes of equal lengths LS=LP=0.8 μm, and drain region edge to gate edge distance d held constant at 0.1 μm for all noted simulations) demonstrate that gate length has far less impact on triggering voltage of the ESD protection device than drain region edge to gate edge distance d. Thus, the drain region edge to gate edge distance d is a more effective parameter to modulate the triggering voltage than gate length LG, which makes high triggering voltage ESD protection devices much easier to fabricate than scaling the gate length alone.
In step 1204, a deep p-well implant (e.g., boron) is formed in at least a portion of the n-type substrate, proximate an upper surface of the substrate, followed by annealing to form a deep p-well (DPW). The deep p-well implant is used to form a p-layer above the n-type substrate for isolation purposes, and is preferably formed having a junction depth of about 2 μm, although it is to be appreciated that embodiments of the invention are not limited to any specific junction depth.
A dielectric layer is formed on an upper surface of the substrate in step 1206, such as by using an oxidation process. This dielectric layer, which is preferably an oxide (e.g., silicon dioxide), is subsequently patterned (e.g., using photolithography or the like) and etched to form a gate oxide layer on a portion of an upper surface of the DPW. A gate is then formed on an upper surface of the gate oxide layer, such as by using deposition, photolithography and etching, in step 1208; photolithography and etching are used to define the gate as desired. The gate is preferably formed of polysilicon material, although a gate formed of other materials (e.g., metal) is similarly contemplated by embodiments of the invention.
In step 1210, a p-type well (p-well) region is formed in the DPW, proximate the upper surface of the DPW, using a p-type implant, followed by annealing to drive in the implant. Optionally, if using an ESD device utilizes an NDD region, step 1210 may include an n-type implant followed by annealing to drive in the implant. Although the NDD region is not explicitly shown in the two-dimensional cross-section of the exemplary ESD protection device 200 illustrated in
In step 1214, p-type and n-type implants are used to form the P+ body regions and N+ source regions in the p-well region used in forming multiple pairs of PN stripes in a source side of the ESD protection device. The number of pairs of PN stripes and the lengths of the P+ and N+ regions in the PN stripes are beneficially configured to meet prescribed leakage current, triggering voltage, hold voltage, etc. criteria for the ESD protection device, as previously described. In one or more embodiments, the N+ source and drain regions are formed using an arsenic implant with implant dose of about 5×1015 atoms/cm2 at an energy level of about 40 kiloelectron volts (keV), and the P+ body regions are formed using a boron implant with implant dose of about 3×1015 atoms/cm2 at an energy level of about 15 keV. An anneal is then performed in step 1214 following the P+ and N+ implants to drive the implants a desired depth into the p-well region. Contact and metal connections are formed in step 1216 as part of back-end-of line (BEOL) processing.
At least a portion of the techniques of the present invention may be implemented in an integrated circuit. In forming integrated circuits, identical die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die includes a device described herein, and may include other structures and/or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Any of the exemplary structures or circuits illustrated in the accompanying figures, or portions thereof, may be part of an integrated circuit. Integrated circuits so manufactured are considered part of this invention.
Those skilled in the art will appreciate that the exemplary structures discussed above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, in packaged form, or incorporated as parts of intermediate products or end products that benefit from having power MOSFET devices therein formed in accordance with one or more embodiments of the invention, such as, for example, radio frequency (RF) power amplifiers, power management ICs, etc.
An integrated circuit in accordance with aspects of the present disclosure can be employed in essentially any high-frequency, high-power application and/or electronic system, such as, but not limited to, RF power amplifiers, power management ICs, etc. Suitable systems for implementing embodiments of the invention may include, but are not limited to, DC-DC converters, transmitters, communications systems, etc. Systems incorporating such integrated circuits are considered part of this invention. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
The illustrations of embodiments of the invention described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the devices, structures and techniques described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. The drawings are also merely representational and may not be drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Embodiments of the invention are referred to herein, individually and/or collectively, by the term “embodiment” merely for convenience and without intending to limit the scope of this application to any single embodiment or inventive concept if more than one is, in fact, shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that an arrangement achieving the same purpose can be substituted for the specific embodiment(s) shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those of skill in the art given the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
Relational terms such as, for example, “above,” “below,” “upper” and “lower,” may be used herein to indicate a position of elements or structures relative to one another, rather than absolute positioning. Thus, it will become apparent that an upper surface of a given structure, when the structure is flipped upside down, will become a lower surface of the structure, and vice versa.
The corresponding structures, materials, acts, and equivalents of all means or step-plus-function elements in the appended claims are intended to include any structure, material, or act for performing the function in combination with other elements as specifically claimed. The description of the various embodiments has been presented merely for purposes of illustration and description, but is not intended to be exhaustive or limited to only the specific forms disclosed. Many modifications and variations will become apparent to those of ordinary skill in the art given the without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.
The abstract is provided to comply with 37 C.F.R. § 1.72(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, inventive subject matter lies in less than all features of a single embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.
Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of embodiments of the invention. Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the invention are not limited to those precise embodiments, and that various other changes and modifications can be made therein by one skilled in the art without departing from the scope or spirit of the appended claims.
