ELECTROSTATIC DISCHARGE PROTECTION DEVICES WITH HIGH CURRENT CAPABILITY

Abstract

Electrostatic discharge (ESD) protection devices with high current capability are described. The ESD protection device may include a pair of bidirectional diodes (first and second bidirectional diodes) connected in series. Each of the bidirectional diodes includes a low capacitance (LC) diode and a bypass diode connected in parallel. During ESD events, current flows through the LC diode of the first bidirectional diode and the bypass diode of the second bidirectional diode. Particular arrangements of the LC diodes and the bypass diodes are devised to facilitate uniform distribution of the current throughout an area occupied by the ESD protection device.

Description

TECHNICAL FIELD

The present disclosure generally relates to the field of semiconductor devices, and more particularly to electrostatic discharge protection devices with high current capability.

BACKGROUND

Integrated circuits (ICs) can be subject to electrostatic discharge (ESD) events, which typically occur when the ICs are brought in contact with or close to another object. ESD protection devices may be coupled with ICs to provide current paths during ESD events to protect the ICs. It would be desirable for the ESD protection devices to be able to safely dissipate high current without incurring damage. During normal operations of the ICs, the ESD protection devices are inactive so as not to interfere with the normal operations. Although the ESD protection devices are inactive (e.g., a diode under a reverse bias condition), their presence tends to increase parasitic capacitance for the ICs. It would be desirable for the ESD protection devices to have low capacitance.

SUMMARY

The present disclosure describes ESD protection devices with high current capability. Moreover, the ESD protection devices include diodes with low capacitance. This summary is not an extensive overview of the disclosure, and is neither intended to identify key or critical elements of the disclosure, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the disclosure in a simplified form as a prelude to a more detailed description that is presented later.

In some embodiments, a semiconductor device includes an n-type substrate; an n-type layer on the substrate; a p-type layer on the n-type layer, the p-type layer including a surface facing away from the substrate; and a first bidirectional diode including: a first low capacitance (LC) diode having (1) a first p-type buried region extended from the p-type layer toward the substrate and terminated within the n-type layer and (2) a first n-type region extended from the surface toward the substrate and terminated above the first p-type buried region.

In some embodiments, a semiconductor device includes an n-type substrate; an n-type layer on the substrate; a p-type layer on the n-type layer, the p-type layer including a surface facing away from the substrate; and a first area including a first side and a second side opposite to the first side, where the first area includes (1) a first pn junction at a first depth from the surface, the first pn junction formed across the p-type layer and a first n-type region extended from the surface to the first depth and (2) a second pn junction at a second depth from the surface greater than the first depth, the second pn-junction formed across the n-type layer and a first p-type buried region extended from the p-type layer toward the substrate.

In some embodiments, a semiconductor device includes an n-type substrate; an n-type layer on the substrate; a p-type layer on the n-type layer, the p-type layer including a first dopant concentration and a surface facing away from the substrate; a first diode area having a first side and a second side opposite to the first side; a second diode area proximate to the first side; a third diode area having a third side and a fourth side opposite to the third side, the third diode region located proximate to the second side having the fourth side facing the second side; and a fourth diode area proximate to the third side, where: each of the first and third diode areas includes (1) a p-type buried region having a second dopant concentration greater than the first dopant concentration, the p-type buried region extended from the p-type layer toward the substrate and terminated within the n-type layer, and (2) an n-type region extended from the surface toward the substrate and terminated within the p-type layer above the p-type buried region, and each of the second and fourth diode areas include a p-type region extended from the surface toward the substrate and terminated within the p-type layer, where the p-type region has a third dopant concentration greater than the first dopant concentration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate schematic diagrams of a semiconductor device in plan and cross-sectional views in accordance with embodiments of the present disclosure;

FIG. 2 is an equivalent circuit of a semiconductor device in accordance with embodiments of the present disclosure;

FIGS. 3A and 3B illustrate example layouts of semiconductor devices in accordance with embodiments of the present disclosure;

FIGS. 4A and 4B present experimental and simulation results illustrating electrical characteristics of semiconductor devices in accordance with embodiments of the present disclosure; and

FIGS. 5A and 5B illustrate schematic diagrams of a semiconductor device in plan and cross-sectional views in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure is described with reference to the attached figures. The components in the figures are not drawn to scale. Instead, emphasis is placed on clearly illustrating overall features and the principles of the present disclosure. Numerous specific details and relationships are set forth with reference to example embodiments of the figures to provide an understanding of the disclosure. It is to be understood that the figures and examples are not meant to limit the scope of the present disclosure to such example embodiments, but other embodiments are possible by way of interchanging or modifying at least some of the described or illustrated elements. Moreover, where elements of the present disclosure can be partially or fully implemented using known components, those portions of such components that facilitate an understanding of the present disclosure are described, and detailed descriptions of other portions of such components are omitted so as not to obscure the disclosure.

Various structures disclosed herein can be formed using semiconductor process techniques. Layers including a variety of materials can be formed over a substrate, for example, using deposition techniques (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating), thermal process techniques (e.g., oxidation, nitridation, epitaxy), and/or other suitable techniques. Similarly, some portions of the layers can be selectively removed, for example, using etching techniques (e.g., plasma (or dry) etching, wet etching), chemical mechanical planarization, and/or other suitable techniques, some of which may be combined with photolithography steps.

The semiconductor devices, integrated circuits, or IC components described herein may be formed on a semiconductor substrate (or die) including various semiconductor materials, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, silicon carbide, or the like. In some cases, the substrate refers to a semiconductor wafer. The conductivity (or resistivity) of the substrate (or regions of the substrate) can be controlled by doping techniques using various chemical species (which may also be referred to as dopant atoms) including, but not limited to, boron, indium, arsenic, or phosphorus. Doping may be performed during the initial formation or growth of the substrate (or an epitaxial layer grown on the substrate), by ion-implantation, or other suitable doping techniques.

As used herein, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms in the description and in the claims are not intended to indicate temporal or other prioritization of such elements. Moreover, terms such as “front,” “back,” “top,” “bottom,” “over,” “under,” “vertical,” “horizontal,” “lateral,” “down,” “up,” “upper,” “lower,” or the like, are used to refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than other features. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the technology described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Diodes are used in a variety of ESD protection devices. Typically, silicon-controlled rectifier (SCR) or bipolar avalanche phenomena including one or more pn junctions provide low resistance current-voltage (I-V) characteristics suitable for ESD protection. For example, a bidirectional ESD protection diode configuration includes back-to-back diodes (e.g., a D1-Z1 diode with diodes D1 and Z1 having a common anode) of a unit cell combined with a forward biased diode (e.g., a diode D2) of another unit cell next to the unit cell to provide a current path during ESD events. Such a configuration may facilitate amplifying the avalanche current based on the bipolar transistor gain of the back-to-back D1-Z1 diode (e.g., open base npn transistor).

It is common practice to increase areas of the ESD protection devices to improve their performance—e.g., to increase amount of current (e.g., ESD current) for the protection devices to safely dissipate. Increasing device areas, however, may not lead to increased current handling capability in some instances. For example, localized current crowding phenomena may hinder the entire device area from uniformly participating in conducting the ESD current. Localized current crowding may initiate thermal runaway phenomena that tend to permanently damage the ESD protection devices by melting localized regions of the device area. As such, achieving uniform distribution of the ESD current throughout the device area would be beneficial to improve current handling capability of the ESD protection devices.

The present disclosure describes ESD protection devices including low capacitance (LC) diodes with high current capability. The protection devices may be configured to have a pair of unit cells disposed next to each other, each unit cell including a bidirectional diode. The bidirectional diode includes first and second diodes connected in parallel, and the ESD protection devices are laid out to position the first and second diodes of the pair of unit cells in particular arrangements. Such arrangements are shown to improve performance of the ESD protection devices (e.g., greater ESD current handling capability, higher ESD ratings) without increasing the area occupied by the protection devices. Simulation results indicate relatively uniform distribution of the ESD current across the unit cells, which can be attributed to the improved ESD current handling capability. Moreover, the LC diodes in accordance with the present disclosure include pn junctions suitable for providing ESD protections for devices designed to operate with relatively high operating voltages (e.g., approximately 30V or so).

FIGS. 1A and 1B illustrate schematic diagrams of a semiconductor device 100 in accordance with embodiments of the present disclosure. FIG. 1A is a plan view of the semiconductor device 100, which may be regarded as a composite layout of the semiconductor device 100, and FIG. 1B is a cross-sectional view of the semiconductor device 100 taken across an imaginary line AB as marked in FIG. 1A. These figures are described concurrently in the following discussion.

The semiconductor device 100 includes an n-type substrate 105. In some embodiments, the n-type substrate 105 may have an average dopant density (e.g., phosphorus or arsenic concentration) greater than 1×10¹⁸ cm⁻³. In some embodiments, a dynamic resistance (Ron) of the semiconductor device 100 may depend on the dopant density of the substrate 105—e.g., the greater dopant density, the less Ron. Moreover, spreading the ESD current throughout the semiconductor device 100 may become more efficient with higher dopant concentration of the substrate 105. In some embodiments, the substrate 105 can have an average dopant density exceeding 5×10¹⁹ cm⁻³. The substrate 105 may be, for example, part of a bulk silicon wafer.

The semiconductor device 100 includes an n-type semiconductor layer 110 (e.g., a crystalline silicon layer) disposed on the substrate 105. In some embodiments, the n-type semiconductor layer 110 has an average dopant density (e.g., phosphorus and/or arsenic concentration) less than 1×10¹⁶ cm⁻³. As such, the n-type semiconductor layer 110 may be referred to as a lightly doped n-type semiconductor layer—i.e., having a relatively less dopant concentration when compared to the substrate 105. In some embodiments, the n-type semiconductor layer 110 may be 1 to 5 micrometers (μm) thick. Moreover, the n-type semiconductor layer 110 may be an epitaxial layer formed on the substrate 105.

Additionally, the semiconductor device 100 includes a p-type semiconductor layer 115 disposed over the n-type semiconductor layer 110. The p-type semiconductor layer 115 has a surface 116 facing away from the substrate 105. In some embodiments, the p-type semiconductor layer 115 has an average dopant density (e.g., boron and/or indium concentration) less than 1×10¹⁵ cm⁻³. As such, the p-type semiconductor layer 115 may be referred to as a lightly doped p-type semiconductor layer. In some embodiments, the p-type semiconductor layer 115 may be 3 to 8 μm thick. The p-type semiconductor layer 115 may be an epitaxial layer formed on the n-type semiconductor layer 110. In some embodiments, the p-type dopant density at or near the surface 116 may be increased greater than the average dopant density. For example, p-type dopant atoms may be added after forming the p-type semiconductor layer 115—e.g., by performing a blanket ion-implantation step after the epitaxial growth process forming the p-type semiconductor layer 115. As a result, the p-type semiconductor layer 115 may include a p-type surface region 117 with the p-type dopant density of approximately 1×10¹⁶ cm⁻³ or less. The increased dopant density at or near the surface 116 is expected to reduce likelihood of forming a depletion layer at or near the surface 116, which may result from electric charge present in a dielectric layer (e.g., oxide layer) above the surface 116.

The semiconductor device 100 includes bidirectional diodes 120 (also identified individually as first and second bidirectional diodes 120a/b). Individual bidirectional diode 120 may be referred to as a unit cell of the semiconductor device 100. As depicted in FIGS. 1A/1B, the semiconductor device 100 includes a pair of the unit cells placed next to each other. The bidirectional diode 120 includes a first diode 125 (also identified individually as first diodes 125a/b) that includes a p-type buried region 130 extended from the p-type semiconductor layer 115 toward the substrate 105. The p-type buried region 130 terminates within the n-type semiconductor layer 110. As such, the p-type buried region 130 does not directly contact the substrate 105.

In some embodiments, the p-type buried region 130 can be formed by performing ion-implantation (i.e., implanting p-type dopant atoms, such as boron and/or indium) in the area corresponding to the first diode 125 after forming the n-type semiconductor layer 110—e.g., after growing an n-type epitaxial layer on the substrate 105. After the ion-implantation step, the p-type semiconductor layer 115 can be formed—e.g., growing a p-type epitaxial layer on the n-type semiconductor layer 110 including the implanted dopant atoms. While the p-type semiconductor layer 115 is being formed (e.g., during the epitaxial growth process forming the p-type semiconductor layer 115), the implanted dopant atoms can spread (e.g., through diffusion process) into the n-type semiconductor layer 110 and into the p-type semiconductor layer 115 as shown in FIG. 1B. In some embodiments, the p-type buried region 130 has a dopant concentration (e.g., boron and/or indium concentration) of at least 1×10¹⁷ cm⁻³.

The first diode 125 also includes an n-type region 135 extended from the surface 116 toward the substrate 105 and terminated above the p-type buried region 130. In some embodiments, the n-type region 135 has a dopant concentration (e.g., phosphorus and/or arsenic concentration) of at least 1×10¹⁶ cm⁻³ or greater. In some embodiments, the n-type region 135 has a graded dopant profile including an inner portion and an outer portion. The inner portion may have an average dopant concentration (e.g., phosphorus and/or arsenic concentration) ranging from 1×10¹⁷ cm⁻³ to 3×10¹⁹ cm⁻³. The outer portion may have an average dopant concentration (e.g., phosphorus and/or arsenic concentration) ranging from 1×10¹⁶ cm⁻³ to 1×10¹⁷ cm⁻³. As depicted in FIG. 1B, the n-type region 135 may laterally extend to the isolation structure (e.g., the isolation structures 141b/c or the isolation structures 141c/d). In some embodiments, the n-type region 135 may not laterally extend all the way to the isolation structure—e.g., the n-type region 535 depicted in FIG. 5B.

The n-type region 135 is in contact with the p-type semiconductor layer 115, which forms a first pn junction (e.g., the diode D1H or D1L depicted in FIG. 1B) of the first diode 125. The first pn junction is formed at a first depth (d1 denoted in FIG. 1B) from the surface 116. In some embodiments, the n-type region 135 is separated from the p-type buried region 130 by approximately 2 μm or more.

The first pn junction is expected to form a relatively wide depletion region under a reverse bias condition (e.g., during normal operations of the device under protection (DUP) coupled with the semiconductor device 100) in view of the first pn junction formed across the n-type region 135 (or the outer portion of the n-type region 135 in some embodiments) and the lightly doped p-type semiconductor layer 115. The wide depletion region is expected to provide relatively low capacitance coupled to the DUP, which may be advantageous to maintain the integrity of signals that the DUP manages. Accordingly, the first diode 125 may be referred to as a low capacitance (LC) diode.

As described herein, the p-type buried region 130 has an interface contacting the n-type semiconductor layer 110. The interface between the p-type buried region 130 and the n-type semiconductor layer 110 forms a second pn junction (e.g., the diode Z1H or diode Z1L depicted in FIG. 1B) of the first diode 125. The second pn junction is formed at a second depth (d2 denoted in FIG. 1B) from the surface 116, which is greater than the first depth. As such, a portion of the p-type semiconductor layer 115 located between the first and second pn junctions forms a common anode for the first and second pn junctions—e.g., a common anode for the diode D1H and the diode Z1H, a common anode for the diode D1L and the diode Z1L. In this manner, the diode D1H (or D1L) and the diode Z1H (or Z1L) forms back-to-back D1-Z1 diodes.

The second pn junction can be configured to breakdown under a reverse bias condition (e.g., at a reverse bias breakdown voltage) to conduct current (e.g., avalanche current) during ESD events. The reverse bias breakdown voltage may be related to working voltages of the ESD protection devices, which can be determined to be less than the reverse bias breakdown voltage. The working voltages of the ESD protection devices may be regarded as a parameter to consider in selecting a proper ESD protection device based on operating conditions of the DUP. For example, the signals that the DUP handles may not exceed the working voltage of the ESD protection device. In other words, the ESD protection devices with greater reverse bias breakdown voltages (i.e., greater working voltages) can provide ESD protection for the DUPs handling greater signal voltage ranges.

The second pn junction of the LC diode 125 is configured to have a greater reverse bias breakdown voltage than a pn junction formed across the p-type buried region 130 and the substrate 105—i.e., a pn junction with the p-type buried region 130 in direct contact with the substrate 105. The greater reverse bias breakdown voltage may be attributed to the lower dopant concentration of the n-type semiconductor layer 110 than the substrate 105. Accordingly, the semiconductor device 100 can have a greater working voltage than ESD protection devices with the pn junction formed across the p-type buried region 130 and the substrate 105 to provide ESD protection for DUPs designed to handle greater signal voltage ranges.

The bidirectional diode 120 includes a second diode 145 (also identified individually as second diodes 145a/b) that has a p-type region 150 extended from the surface 116 toward the substrate 105. The p-type region 150 terminates within the p-type semiconductor layer 115. In some embodiments, the p-type region 150 has a dopant concentration (e.g., boron and/or indium concentration) of at least 1×10¹⁷ cm⁻³. The second diode 145 includes a third pn junction (e.g., the diode D2H or D2L depicted in FIG. 1B) of the bidirectional diode 120, which is formed across the p-type semiconductor layer 115 and the n-type semiconductor layer 110. The third pn junction is formed at a third depth (d3 denoted in FIG. 1B) from the surface 116, which is greater than the first depth (dl) and less than the second depth (d2).

Moreover, the bidirectional diode 120 includes an isolation area 140 surrounding the first diode 125 and the second diode 145, respectively. In this regard, the first diode 125 and the second diode 145 are laterally separated by the isolation area 140. The isolation areas for the first bidirectional diode 120a and the second bidirectional diode 120b may be regarded as merged (conjoined) together for the semiconductor device 100. The isolation area 140 includes isolation structure 141. The cross-sectional view of FIG. 1B illustrates portions of the isolation structure 141, which are identified individually as isolation structures 141a through 141e. The isolation structure 141 extend from the surface 116 past an interface between the n-type semiconductor layer 110 and the substrate 105. In this manner, a portion of the isolation area 140 surrounds the first diode 125—e.g., the isolation structures 141b and 141c at both sides of the first diode 125a in the cross-sectional view of FIG. 1B. Similarly, another portion of the isolation area 140 surrounds the second diode 145—e.g., the isolation structures 141a and 141b at both sides of the second diode 145a in the cross-sectional view of FIG. 1B.

In some embodiments, the isolation structure 141 can be formed by trench isolation techniques. For example, the isolation structure 141 may be formed by etching trenches through the p-type semiconductor layer 115 (and the p-type buried region 130 of the first diode 125), the n-type semiconductor layer 110, and into the substrate 105. Depths of the trenches may range from 5 to 15 μm, or even greater (e.g., 20 μm). Accordingly, the isolation area 140 may be referred to as a deep trench isolation (DTI) area. Similarly, the isolation structure 141 may be referred to as a DTI structure or a dielectric isolation structure. In some embodiments, the DTI structure include a dielectric liner formed on the trench surface (e.g., sidewall and bottom of the trench) and poly-silicon formed on the dielectric liner. The poly-silicon may be dielectrically isolated from other structures (or components) outside the DTI structure.

In some embodiments, the isolation structure 141 can be formed after forming the n-type region 135 and/or the p-type region 150 in the p-type semiconductor layer 115. For example, after forming the p-type semiconductor layer 115 (e.g., by forming the p-type epitaxial layer on the n-type semiconductor layer 110), photolithography steps can define the n-type region 135 (or the p-type region 150) followed by ion-implantation steps to introduce n-type dopant atoms for the n-type region 135 (or p-type dopant atoms for the p-type region 150) Subsequently, the isolation structure 141 can be formed as described above.

In other embodiments, the isolation structure 141 can be formed before forming the n-type region 135 and/or the p-type region 150 in the p-type semiconductor layer 115. For example, the isolation structure 141 can be formed as described above after forming the p-type semiconductor layer 115 (e.g., by forming the p-type epitaxial layer on the n-type semiconductor layer 110). Subsequently, photolithography steps can define the n-type region 135 (or the p-type region 150) followed by ion-implantation steps to introduce n-type dopant atoms for the n-type region 135 (or p-type dopant atoms for the p-type region 150) to form the n-type region 135 and the p-type region 150.

The n-type region 135 and the p-type region 150 of the bidirectional diode 120 are connected to a terminal—e.g., a terminal 160 connected to the first bidirectional diode 120a, a terminal 165 connected to the second bidirectional diode 120b. Although the first diode 125 and the second diode 145 are laterally isolated from each other by the isolation structure 141 throughout the p-type semiconductor layer 115 (and the p-type buried region 130 of the first diode 125) and the n-type semiconductor layer 110, the substrate 105 provides a common node for the first diode 125 and the second diode 145, which may be regarded as another terminal for the bidirectional diode 120.

Accordingly, the first diode 125 and the second diode 145 are connected in parallel between two terminals—e.g., the terminal 160 (or 165) and the substrate 105. As such, the second diode 145 may be referred to as a parallel diode (parallel to the first diode 125). Moreover, during ESD events that forward biases the second diode 145, the second diode 145 activates (turns on) to flow the ESD current that bypasses the first diode 125. As such, the second diode 145 may also be referred to as a bypass diode.

The semiconductor device 100 is depicted to include a pair of the bidirectional diodes 120a/b and two terminals, each of which is connected to one of the bidirectional diodes 120a/b, respectively—e.g., a first terminal 160 connected to the first bidirectional diode 120a and a second terminal 165 connected to the second bidirectional diode 120b. The first terminal 160 may be coupled with a node (a high node) of a DUP, and the second terminal 165 may be coupled with another node (a low node (or ground)) of the DUP as indicated in FIG. 1B. Moreover, the first and second bidirectional diodes 120a/b share the substrate 105 such that the first and second bidirectional diodes 120a/b are connected to each other at the substrate 105. An equivalent circuit diagram of the semiconductor device 100 is shown in FIG. 2.

During a first ESD event with a first polarity (e.g., forward biasing the first bypass diode 145a), first current 170 flows between the first bypass diode 145a (connected to the first terminal 160) and the second LC diode 125b (connected to the second terminal 165) through a first portion of the substrate 105 under the first LC diode 125a. The pn junction of the diode Z1L of the second LC diode 125b breaks down to flow the current 170 (e.g., avalanche current) to steer (e.g., dissipate, shunt) the ESD current to the second terminal 165, thereby protecting the DUP coupled to the first and second terminals 160 and 165.

Similarly, during a second ESD event with a second polarity opposite to the first polarity (e.g., forward biasing the second bypass diode 145b), second current 175 flows between the second bypass diode 145b (connected to the second terminal 165) and the first LC diode 125a (connected to the first terminal 160) through a second portion of the substrate 105 under the second LC diode 125b. The pn junction of the diode Z1H of the first LC diode 125a breaks down to flow the current 175 (e.g., avalanche current) to steer the ESD current to the first terminal 160, thereby protecting the DUP coupled to the first and second terminals 160 and 165.

As described in more detail with reference to FIGS. 3A/3B and 4A/4B, components of the semiconductor device 100 (e.g., the first and second LC diodes, the first and second bypass diodes) are particularly arranged (e.g., positioned, laid out) to increase the ESD current handling capability of the semiconductor device 100 for both polarities of the ESD events. The increased ESD current handling capability may be attributed to relatively uniform distribution of the ESD current throughout the device area.

Referring to FIG. 1A, the semiconductor device 100 includes a first area 180 having a first side 181a and a second side 181b opposite to the first side 181a. The first area 180 includes the first LC diode 125a. The semiconductor device 100 includes a second area 185 located proximate to the first side 181a of the first area 180. The second area 185 includes the first bypass diode 145a. The semiconductor device 100 also includes a third area 190 having a third side 191b and a fourth side 191a opposite to the third side 191b, where the third area 190 is located proximate to the first area 180 with the fourth side 191a facing the second side 181b of the first area 180. The third area 190 includes the second LC diode 125b. Moreover, the semiconductor device 100 includes a fourth area 195 located proximate to the third side 191b of the third area 190. The fourth area 195 includes the second bypass diode 145b.

FIG. 1A illustrates directions of the first current 170 and the second current 175 during the first and second ESD events, respectively, as described with reference to FIG. 1B. Namely, the current 170 flows into the first bypass diode 145a (as indicated by the “x” mark) that is connected to the first terminal 160, and exits out of the second LC diode 125b (as indicated by the filled circle mark) that is connected to the second terminal 165 during the first ESD event with the first polarity. Similarly, the current 175 flows into the second bypass diode 145b (connected to the second terminal 165) and exits out of the first LC diode 125a (connected to the first terminal 160) during the second ESD event with the second polarity opposite to the first polarity.

The layout of FIG. 1A (i.e., placement of the first and second LC diodes, the first and second bypass diodes) facilitates the first current 170 and the second current 175 to travel a distance generally the same. In this manner, the ESD current handling capability of the semiconductor device 100 is expected to be generally the same for both polarities of the ESD events—e.g., the ESD current handling capability being symmetrical to both polarities of the ESD events. Moreover, the layout of FIG. 1A tends to maximize the distance that the ESD current travels within the area occupied by the semiconductor device 100, which can be advantageous for uniformly distributing the ESD current throughout the area as described with reference to FIGS. 4A/4B.

FIG. 2 is an equivalent circuit 200 of a semiconductor device (e.g., the semiconductor device 100) in accordance with embodiments of the present disclosure. The circuit 200 includes two bidirectional diodes 205 (also identified individually as first and second bidirectional diodes 205a/b) with a node 210 common to both of the bidirectional diodes 205a/b. The first and second bidirectional diodes 205a/b may be examples of or include aspects of the first and second bidirectional diodes 120a/b described with reference to FIGS. 1A/1B, respectively. For example, individual bidirectional diode 205 includes the LC diode (i.e., the diodes D1 and Z1 connected in a back-to-back configuration) and the bypass diode (i.e., the diode D2) in parallel as described with reference to FIGS. 1A/1B. The node 210 may correspond to the substrate 105, to which both the first and second bidirectional diodes 205a/b are connected.

Moreover, the nodes marked as HIGH and LOW (GND) of the circuit 200 may correspond to the terminals 160 and 165, respectively. FIG. 2 also indicates the first and second current 170 and 175 that flow through the two bidirectional diodes 205a/b (120a/b) during the ESD events. Namely, the first current 170 flows through the diode D2H, Z1L (under the reverse bias breakdown condition), and D1L during the first ESD event. Similarly, the second current 175 flows through the diode D2L, Z1H (under the reverse bias breakdown condition), and D1H during the second ESD event.

FIGS. 3A and 3B illustrate example layouts of semiconductor devices 301 and 302, respectively, in accordance with embodiments of the present disclosure. Both of the semiconductor devices 301 and 302 include first and second bidirectional diodes 305 and 325, which may be examples of or include aspects of the bidirectional diodes 120a/b and 205a/b described with reference to FIGS. 1A/1B and 2. Isolation areas (e.g., the isolation area 140 described with reference to FIGS. 1A/1B) of the bidirectional diodes 305 and 325 are omitted in FIGS. 3A/3B to clearly illustrate the principles of the present disclosure. As described herein, individual bidirectional diode 305 or 325 can be regarded as a unit cell for the semiconductor device 301 (or 302), and the semiconductor device 301 (or 302) may be configured to include a pair of the unit cell. The semiconductor devices 301 and 302 occupy generally the same area.

The first bidirectional diode 305 includes a first LC diode 310 (which may be an example of or include aspects of the LC diode 125 described with reference to FIGS. 1A/1B) and a first bypass diode 315 (which may be an example of or include aspects of the bypass diode 145 described with reference to FIGS. 1A/1B). Similarly, the second bidirectional diode 325 includes a second LC diode 330 (which may be an example of or include aspects of the LC diode 125 described with reference to FIGS. 1A/1B) and a second bypass diode 335 (which may be an example of or include aspects of the bypass diode 145 described with reference to FIGS. 1A/1B). Moreover, the first LC diode 310 and the first bypass diode 315 are connected to a first terminal 320 (HIGH), and the second LC diode 330 and the second bypass diode 335 are connected to a second terminal 340 (LOW/GND) in the manner described with reference to FIGS. 1A/1B. Accordingly, the first and second bidirectional diodes 305 and 325 form the circuit 200 described with reference to FIG. 2.

The semiconductor device 301 of FIG. 3A may be regarded as an ESD protection device designed to have a relatively reduced dynamic resistance (Ron)—e.g., when compared to the semiconductor device 302. Having relatively less Ron may be advantageous to reduce the voltage drop across the semiconductor device 301 (and the voltage drop across a DUP coupled thereto) during ESD events, which may be referred to as a clamping voltage. As described with reference to FIG. 1B, the dynamic resistance of the semiconductor device 301 may be, at least partially, determined by the distance that the ESD current travels and/or the resistivity of the substrate 105, through which the ESD current flows.

The layout of the semiconductor device 301 is devised to reduce the distance that the ESD current travels. For example, the semiconductor device 301 has the first bypass diode 315 placed proximate to the second LC diode 330. Additionally, the second bypass diode 335 is placed proximate to the first LC diode 310. In this manner, the distance for ESD current 350 or 351 to flow during ESD events may be reduced—e.g., when compared to the distance for ESD current 360 or 361 to flow in the semiconductor device 302. Accordingly, the semiconductor device 301 may be expected to exhibit a less dynamic resistance than the semiconductor device 302.

The semiconductor device 302 of FIG. 3B may be regarded as an ESD protection device designed to have a relatively greater current handling capability in both polarities of the ESD events—e.g., when compared to the semiconductor device 301. Moreover, the semiconductor device 302 is configured to increase the current handling capability while maintaining the device area generally same as the semiconductor device 301. The semiconductor device 302 is expected to have relatively uniform distribution of the ESD current throughout the device area during the ESD event, which is expected to contribute to the increased current handling capability.

The semiconductor device 302 has the first bypass diode 315 placed away from the second LC diode 330 with at least a portion of the first LC diode 310 located between the first bypass diode 315 and the second LC diode 330. Similarly, the second bypass diode 335 is placed away from the first LC diode 310 with at least a portion of the second LC diode 330 located between the second bypass diode 335 and the first LC diode 310. In this manner, the distance for ESD current 360 or 361 to flow during ESD events may be increased—e.g., when compared to the distance for the ESD current 350 or 351 to flow in the semiconductor device 301. As described in more detail herein with reference to FIGS. 4A/4B, the semiconductor device 302 is expected to have relatively higher current handling capability—e.g., when compared to the semiconductor device 301.

FIGS. 4A and 4B present experimental and simulation results illustrating electrical characteristics of the semiconductor devices in accordance with embodiments of the present disclosure. FIG. 4A show current-voltage (I-V) curves 410 (marked with “x” and square symbols) of the semiconductor device 301 and I-V curves 415 (marked with triangle and diamond symbols) of the semiconductor device 302. The I-V curves 410 and 415 may be referred to as transmission line pulsing (TLP) measurements of the semiconductor devices 301 and 302.

As shown in FIG. 4A, the semiconductor devices 301 and 302 remain inactive (e.g., does not conduct current except leakage current) until the voltage across the devices reaches V1 or greater—e.g., occurrence of ESD events. The voltage V1 may be related to the voltage that the diode Z1 experiences the reverse bias breakdown. In some embodiments, V1 may vary around 31 or 32 V. When the voltage reaches or exceeds V1, the semiconductor devices 301 and 302 activate and “snap back” to an operating point determined by Vh and Ih. In some embodiments, Vh may vary around 26 or 27 V. The activation of the semiconductor devices 301 and 302 may be attributed to the npn bipolar transistor action of the diodes Z1 and D1.

When the semiconductor device 301 and 302 activates, the current flows through the semiconductor device 301 and 302, thereby protecting the DUP during the ESD events. The slope of the I-V curve may be inversely proportional to the dynamic resistance of the semiconductor devices 301 and 302. FIG. 4A shows that the semiconductor devices 301 and 302 have comparable slopes (although the semiconductor device 301 can be regarded to exhibit a slightly steeper slope, i.e., indicating slightly less Ron than the semiconductor device 302). Without being bound by the theory, the comparable slopes (i.e., comparable Ron) may be attributable to the relatively smaller areas of the bypass diodes 315/335 in comparison to the areas of the LC diodes 310/330, through which the ESD current flows.

The I-V curves 410 indicate that the semiconductor device 301 can be destroyed when the current reaches (or exceeds) It2 in view of the I-V characteristics of the semiconductor device 301 deviating from the normal behavior that maintains the Ron generally constant. Typically, such destruction is irreversible, and the semiconductor device 301 may not be functional thereafter. In some embodiments, It2 of the semiconductor device 301 may vary around 26 Amperes (A).

The I-V curves 415 indicate that the semiconductor device 302 can sustain the current level (It2) that destroyed the semiconductor device 301 and operates normally at current levels greater than It2 of the semiconductor device 301. In some embodiments, the semiconductor device 302 can handle at least 28 A that corresponds to the maximum current limit of the TLP equipment can supply.

FIG. 4B shows simulation results depicting 2-dimensional (2D) current distribution throughout areas of semiconductor devices 401 and 402, which may be referred to as current contour maps. Each of the semiconductor device 401 and 402 includes an LC diode 420 and a bypass diode 425. The simulation conditions can be established such that current can flow between the LC diode 420 and the bypass diode 425—e.g., the LC diode 420 emulating the LC diode 310 of the first bidirectional diode 305 and the bypass diode 425 emulating the bypass diode 335 of the second bidirectional diode 325. As such, the semiconductor devices 401 and 402 can simulate the 2D current distribution of the semiconductor devices 301 and 302 during ESD events, respectively.

The LC diode 420 is divided into 15 segments (the segment located at lower left corner is not activated) to examine how each segment of the LC diode 420 participates in the ESD events as a function of the distance to the bypass diode 425. For example, the LC diode 420 includes a segment 420a positioned nearest to the bypass diode 425 and another segment 420b positioned farthest from the bypass diode 425.

The simulation results show that the semiconductor device 401 exhibits relatively localized 2D current distribution across the segments of the LC diode 420—e.g., when compared to that of the semiconductor device 402. In some embodiments, the segment 420b carries about 14% less current than the segment 420a. Contrastingly, the simulation results show that the semiconductor device 402 exhibits relatively well spread 2D current distribution across the segments of the LC diode 420—e.g., when compared to that of the semiconductor device 401. In some embodiments, the difference between the current carried by the segments 420a and 420b is about 1.2% or less.

The simulation results indicate that the improved current handling capability of the semiconductor device 302 (e.g., It2 of the semiconductor device 302 greater than It2 of the semiconductor device 301) can be attributable to the well spread 2D current distribution across the semiconductor device 302 when the bypass diode 315 (or 335) is spaced away from the LC diode 330 (or 310). The increased distance for the ESD current 360/361 to travel (when compared to the ESD current 350/351) is expected to facilitate spreading of the ESD current 360/361 in the substrate 105, thereby hindering localized crowding of the ESD current that tends to limit the current handling capability of the ESD protection devices.

FIGS. 5A and 5B illustrate schematic diagrams of a semiconductor device 500 in accordance with embodiments of the present disclosure. FIG. 5A is a plan view of the semiconductor device 500, which may be regarded as a composite layout of the semiconductor device 500, and FIG. 5B is a cross-sectional view of the semiconductor device 500 taken across an imaginary line AB as marked in FIG. 5A. The semiconductor device 500 is generally similar to the semiconductor device 100 described with reference to FIGS. 1A/1B. For example, the semiconductor device 500 may be configured to include a pair of bidirectional diodes 520 (also identified individually as first and second bidirectional diodes 520a/b).

The bidirectional diode 520 includes an LC diode 525 (e.g., a first LC diode 525a, a second LC diode 525b) that may include aspects of the LC diode 125 described with reference to FIGS. 1A/1B. The bidirectional diode 520 also includes the bypass diode 145 (e.g., the first bypass diode 145a, the second bypass diode 145b) described with reference to FIGS. 1A/1B. Moreover, the first LC diode 525a and the first bypass diode 145a are connected to the first terminal 160 (HIGH), and the second LC diode 525b and the second bypass diode 145b are connected to the second terminal 165 (LOW/GND) in the manner described with reference to FIGS. 1A/1B. Accordingly, the first and second bidirectional diodes 520a/b form the circuit 200 described with reference to FIG. 2.

The semiconductor device 500 is depicted to includes four isolation areas 580, 582, 584, and 586. Each isolation area is configured to surround corresponding individual LC diodes 525a/b and bypass diodes 145a/b. Moreover, the isolation areas 580, 582, 584, and 586 includes isolation structures 581, 583, 585, and 587 (also identified individually as isolation structures 581a/b, 583a/b, 585a/b, 587a/b in the cross-sectional view of FIG. 5B). The isolations structures 581, 583, 585, and 587 may be examples of or include aspects of the isolation structure 141 described with reference to FIGS. 1A/1B.

The LC diode 525 includes an n-type region 535 which may include aspects of the n-type region 135 described with reference to FIGS. 1A/1B. For example, the n-type region 535 may have a dopant concentration (e.g., phosphorus and/or arsenic concentration) of at least 1×10¹⁶ cm⁻³ or greater. Moreover, in some embodiments, the n-type region 535 may include an inner portion (which may include aspects of the inner portion of the n-type region 135—e.g., the average dopant concentration ranging from 1×10¹⁷ cm⁻³ to 3×10¹⁹ cm⁻³) and an outer portion (which may include aspects of the outer portion of the n-type region 135—e.g., the average dopant concentration ranging from 1×10¹⁶ cm⁻³ to 1×10¹⁷ cm⁻³). As depicted in FIGS. 5A/5B, the n-type region 535 may not laterally extend all the way to the isolation structure (e.g., the isolation structures 583a/b or the isolation structures 585a/b). In other words, the n-type region 535 may be spaced away from the isolation structures surrounding the n-type region 535.

As described above with reference to FIGS. 1A/1B, the p-type semiconductor layer 115 may include the p-type surface regions 117—e.g., as a result of the blanket ion-implantation step performed after forming the p-type semiconductor layer 115. As such, the p-type surface regions 117 may surround the n-type regions 535. For example, FIG. 5A illustrates the p-type surface regions 117 located between the n-type region 535 and the isolation area 582 (or the isolation area 584) while FIG. 5B illustrates the p-type surface regions 117 at both sides of the n-type regions 535. The increased dopant density of the p-type surface regions 117 at or near the surface 116 is expected to reduce likelihood of forming a depletion layer at or near the surface 116, which may result from electric charge that may be present in a dielectric layer (e.g., an oxide layer) above the surface 116. Such a depletion layer, if formed, may increase the capacitance of the semiconductor device 500—e.g., the capacitance associated with the D1 diode.

The present disclosure is not limited to the foregoing example layouts of the isolation areas—e.g., the isolation area 140 surrounding the first/second LC diodes and the first/second bypass diodes as depicted in FIG. 1A, the isolation areas 580, 582, 584, and 586 individually surrounding the first and second LC diodes and the first and second bypass diodes as depicted in FIG. 5A. For example, the isolation areas 580 and 582 may be merged (e.g., the isolation structures 581b and 583a merged together) in some embodiments. Similarly, the isolation areas 584 and 586 may be merged (e.g., the isolation structures 585b and 587a merged together) in some embodiments. Moreover, aspects of the present disclosure—e.g., various placement schemes for positioning the LC diodes and bypass diodes of the bidirectional diodes to facilitate the uniform distribution of ESD current—can be applied to stand-alone ESD protection devices that may be externally attached to DUPs, as well as on-die ESD protection devices that may be integrated as part of DUPs.

While various embodiments of the present disclosure have been described above, it is to be understood that they have been presented by way of example and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the present disclosure. In addition, while in the illustrated embodiments various features or components have been shown as having particular arrangements or configurations, other arrangements and configurations are possible. Moreover, aspects of the present technology described in the context of example embodiments may be combined or eliminated in other embodiments. Thus, the breadth and scope of the present disclosure is not limited by any of the above described embodiments.

Claims

1. A semiconductor device, comprising: an n-type substrate;an n-type layer on the substrate;a p-type layer over the n-type layer, the p-type layer including a surface facing away from the substrate; anda first bidirectional diode including: a first low capacitance (LC) diode having (1) a first p-type buried region extended from the p-type layer toward the substrate and terminated within the n-type layer and (2) a first n-type region extended from the surface toward the substrate and terminated above the first p-type buried region.

2. The semiconductor device of claim 1, wherein the first bidirectional diode further comprises a first isolation structure surrounding the first LC diode, the first isolation structure extended from the surface past an interface between the n-type layer and the substrate.

3. The semiconductor device of claim 2, wherein the first bidirectional diode further comprises: a first bypass diode having a first p-type region extended from the surface toward the substrate and terminated within the p-type layer; anda second isolation structure surrounding the first bypass diode, the second isolation structure extended from the surface past the interface.

4. The semiconductor device of claim 3, wherein the first bypass diode lacks the first p-type buried region.

5. The semiconductor device of claim 3, further comprising a second bidirectional diode including: a second LC diode having (1) a second p-type buried region extended from the p-type layer toward the substrate and terminated within the n-type layer and (2) a second n-type region extended from the surface toward the substrate and terminated above the second p-type buried region;a third isolation structure surrounding the second LC diode, the third isolation structure extended from the surface past the interface;a second bypass diode having a second p-type region extended from the surface toward the substrate and terminated within the p-type layer; anda fourth isolation structure surrounding the second bypass diode, the fourth isolation structure extended from the surface past the interface.

6. The semiconductor device of claim 5, wherein the substrate provides a common node for the first and second LC diodes and the first and second bypass diodes.

7. The semiconductor device of claim 5, further comprising: a first terminal connected to the first n-type region and the first p-type region of the first bidirectional diode; anda second terminal connected to the second n-type region and the second p-type region of the second bidirectional diode.

8. The semiconductor device of claim 5, wherein: during a first electrostatic discharge (ESD) event with a first polarity, first current flows between the first bypass diode and the second LC diode through a first portion of the substrate under the first LC diode; andduring a second ESD event with a second polarity opposite to the first polarity, second current flows between the second bypass diode and the first LC diode through a second portion of the substrate under the second LC diode.

9. The semiconductor device of claim 1, wherein the first n-type region is separated from the first p-type buried region by at least two (2) micrometers.

10. The semiconductor device of claim 1, wherein: the first n-type region includes an inner portion with a first average dopant concentration and an outer portion with a second average dopant concentration less than the first average dopant concentration; andthe outer portion in contact with the p-type layer forms a first pn junction at a first depth from the surface.

11. The semiconductor device of claim 10, wherein: the first average dopant concentration ranges from 1×1017 cm−3 to 3×1019 cm−3; andthe second average dopant concentration ranges from 1×1016 cm−3 to 1×1017 cm−3.

12. The semiconductor device of claim 10, wherein the first p-type buried region includes an interface contacting the n-type layer, the interface forming a second pn junction at a second depth from the surface greater than the first depth.

13. The semiconductor device of claim 12, wherein a third pn junction is formed across the p-type layer and the n-type layer at a third depth from the surface greater than the first depth and less than the second depth.

14. The semiconductor device of claim 1, wherein: the n-type substrate has an average dopant concentration greater than 1×1018 cm−3;the n-type layer has an average dopant concentration less than 1×1016 cm−3;the p-type layer has an average dopant concentration less than 1×1015 cm−3 the p-type buried region has a dopant concentration of at least 1×1017 cm−3; andthe p-type region has a dopant concentration of at least 1×1017 cm−3.

15. A semiconductor device, comprising: an n-type substrate;an n-type layer on the substrate;a p-type layer over the n-type layer, the p-type layer including a surface facing away from the substrate; anda first area including a first side and a second side opposite to the first side, wherein the first area includes (1) a first pn junction at a first depth from the surface, the first pn junction formed across the p-type layer and a first n-type region extended from the surface to the first depth and (2) a second pn junction at a second depth from the surface greater than the first depth, the second pn junction formed across the n-type layer and a first p-type buried region extended from the p-type layer toward the substrate.

16. The semiconductor device of claim 15, further comprising: a first isolation structure surrounding the first area, the first isolation structure extended from the surface past an interface between the n-type layer and the substrate.

17. The semiconductor device of claim 16, further comprising: a second area located proximate to the first side of the first area, the second area including a third pn junction at a third depth from the surface greater than the first depth and less than the second depth, wherein the third pn junction is formed across the p-type layer and the n-type layer; anda second isolation structure surrounding the second area, the second isolation structure extended from the surface past the interface.

18. The semiconductor device of claim 17, further comprising: a third area including a third side and a fourth side opposite to the third side, the third area located proximate to the first area with the fourth side facing the second side, wherein the third area includes (1) a fourth pn junction at the first depth, the fourth pn junction formed across the p-type layer and a second n-type region extended from the surface to the first depth and (2) a fifth pn junction at the second depth, the fifth pn junction formed across the n-type layer and a second p-type buried region extended from the p-type layer toward the substrate;a third isolation structure surrounding the third area, the third isolation structure extended from the surface past the interface;a fourth area located proximate to the third side of the third area, the fourth area including a sixth pn junction at the third depth, wherein the sixth pn junction is formed across the p-type layer and the n-type layer; anda fourth isolation structure surrounding the fourth area, the second isolation structure extended from the surface past the interface.

19. The semiconductor device of claim 18, further comprising: a first terminal connected to the first n-type region and a first p-type region of the second area, the first p-type region located in the p-type layer of the second area and extended to the surface; anda second terminal connected to the second n-type region and a second p-type region of the fourth area, the second p-type region located in the p-type layer of the fourth area and extended to the surface.

20. The semiconductor device of claim 18, wherein: during a first electrostatic discharge (ESD) event with a first polarity, first current flows between the first p-type region and the second n-type region through a first portion of the substrate corresponding to the first area; andduring a second ESD event with a second polarity opposite to the first polarity, second current flows between the second p-type region and the first n-type region through a second portion of the substrate corresponding to the third area.

21. A semiconductor device, comprising: an n-type substrate;an n-type layer on the substrate;a p-type layer over the n-type layer, the p-type layer including a first dopant concentration and a surface facing away from the substrate;a first diode area having a first side and a second side opposite to the first side;a second diode area proximate to the first side;a third diode area having a third side and a fourth side opposite to the third side, the third diode area located proximate to the second side having the fourth side facing the second side; anda fourth diode area proximate to the third side, wherein:each of the first and third diode areas includes (1) a p-type buried region having a second dopant concentration greater than the first dopant concentration, the p-type buried region extended from the p-type layer toward the substrate and terminated within the n-type layer, and (2) an n-type region extended from the surface toward the substrate and terminated within the p-type layer above the p-type buried region, andeach of the second and fourth diode areas include a p-type region extended from the surface toward the substrate and terminated within the p-type layer, wherein the p-type region has a third dopant concentration greater than the first dopant concentration.

22. The semiconductor device of claim 21, further comprising: an isolation area surrounding the first, second, third, and fourth diode areas, respectively, wherein the isolation area includes a dielectric isolation structure extended from the surface past an interface between the n-type layer and the substrate.

23. The semiconductor device of claim 22, wherein the dielectric isolation structure includes: a first dielectric isolation structure extended between the first and second diode areas;a second dielectric isolation structure extended between the second and third diode areas; anda third dielectric isolation structure extended between the third and fourth diode areas.

24. The semiconductor device of claim 23, wherein: the n-type region of the first diode area extends between the first and second isolation structures; andthe n-type region of the third diode area extends between the second and third isolation structures.

25. The semiconductor device of claim 23, wherein: the n-type region of the first diode area is spaced away from the first and second isolation structures; andthe n-type region of the third diode area is spaced away from the second and third isolation structures.

26. The semiconductor device of claim 21, further comprising: a first terminal connected to the n-type region of the first diode area and the p-type region of the second diode area; anda second terminal connected to the n-type region of the third diode area and the p-type region of the fourth diode area.

27. The semiconductor device of claim 21, wherein: during a first electrostatic discharge (ESD) event with a first polarity, first current flows between the p-type region of the second diode area and the n-type region of the third diode area through a first portion of the substrate corresponding to the first diode area; andduring a second ESD event with a second polarity opposite to the first polarity, second current flows between the p-type region of the fourth diode area and the n-type region of the first diode area through a second portion of the substrate corresponding to the third diode area.