Patent Application
20090309182
The present invention relates to an electrostatic discharge (ESD) protection structure for an integrated circuit device, and more particularly where the level of protection, i.e. voltage at which the structure can sustain the application of an ESD signal, and the level at which the structure can dissipate the ESD signal can be controlled.
Structures to protect integrated circuit devices from the deleterious effects of an Electrostatic Discharge (ESD) signal are well known in the art. See for example U.S. Pat. No. 6,493,199. In such a structure, a well of N type conductivity is provided in a substrate of P type conductivity. P+ region and N+ region are formed in the N well. Finally, a N+ region is formed adjacent to the N well. The formation of such a structure appears to be unnecessarily complicated involving the use of a number of mask steps, which increases cost. Accordingly, it is one object of the present invention to simply the formation of an ESD protection structure.
In the present invention, an Electrostatic Discharge (ESD) structure for an integrated circuit for protecting the integrated circuit from an ESD signal, has a substrate of a first conductivity type. The substrate has a top surface. A first region of a second conductivity type is near the top surface and receives the ESD signal. A second region of the second conductivity type is in the substrate, separated and spaced apart from the first region in a substantially vertical direction. A third region of the first conductivity type, heavier in concentration than the substrate, is immediately adjacent to and in contact with the second region, substantially beneath the second region.
Referring to
In the operation of the structure 50 of the present invention, when an input signal is applied to the first region 16, if the voltage thereof is not sufficiently high, i.e. it is not an ESD signal, then the signal would be processed in a conventional manner. However, if the ESD signal has a high voltage, then the voltage of the ESD signal would cause the ESD signal to punch through the substrate 10 between the first region 16 and the second region 18, where the signal is then dissipated. The second region 18 is connected to ground potential. Thus, in essence, the first region 16, the separation region 10, and the second region 18 form a bipolar transistor through which the ESD signal is dissipated to ground.
The punch through voltage of the ESD signal is mainly controlled by the concentration of the P type conductivity of the substrate 10 and by the distance W between the first region 16 and the second region 18. The location of the third region 20 and the second region 18 can be controlled by the energy of the ion implant that form those regions. In addition, those regions may be formed by epitaxial deposition, forming epi grown layers. Finally, the depth of the first region 16 below the top surface 14 can be controlled by the implanting energy of phosphorus and/or arsenic implants followed by a thermal anneal cycle. In the preferred embodiment, the first region 16 should be as close to the top surface 14 as possible. The contact of the second region 18 with the third region 20 becomes a degenerated metallurgical short.
Referring to
In the operation of the structure 50 of the present invention, when an input signal is applied to the first region 16 and the fourth region 15, if the voltage thereof is not sufficiently high, i.e. it is not an ESD signal, then the signal would be processed in a conventional manner. However, if the ESD signal has a high voltage, then the voltage of the ESD signal would cause the structure 150 to function as an SCR with the N well 11 break down voltage controlled by the doping concentration of the first conductivity type in the third region 20 beneath the second region 18. By adjusting the concentration of the P conductivity type, the SCR trigger voltage can be controlled to a desirable voltage. Again, similar to the first embodiment, the second region 18 is connected to ground potential.
Similar to the formation of the structure 50, the second region 18 and third region 20 of the protection structure 150 can be formed by epitaxial deposition, forming epi grown layers. Finally, the depth of the first region 16 and fourth region 15 below the top surface 14 can be controlled by the implanting energy of the dopant implants followed by a thermal anneal cycle. In the preferred embodiment, the first region 16 and the fourth region 15 should be as close to the top surface 14 as possible.
From the foregoing it can be seen that the ESD protection structure 50 or 150 of the present invention does not require the formation of a regions outside of the well, thereby saving processing steps.
