Patent Application
20210392742
The disclosure herein relates to high speed connection, particularly relates to high speed signal traces routed on inner layers of a semiconductor package or a printed circuit board (PCB).
Planar transmission lines, sometimes referred to as traces, have been used to interconnect components on printed circuits and integrated circuits for a long time. Typical types of planar transmission lines include microstrip and stripline. Microstrip is a surface structure not suitable for internal layers of integrated IC packages or printed circuit boards (PCBs) so stripline is generally used for internal layers. Signal speeds are getting faster in modern electronic circuits and high-speed signal traces have a high requirement for impedance control. Because the normal form of stripline has a high trace capacitance, it is hard to achieve targeted impedance for traces routed on inner layers of integrated IC packages or PCBs as stripline structure. Moreover, the required impedance may be achieved by reducing trace width or spacing out traces but some time the limitation of process capability makes this approach costly or hard to achieve. One other method is to increase the dielectric layers thickness to increase the distance between reference planes and traces, but this will increase the substrate or PCB thickness and make the IC package or PCB hard to meet height requirements.
A continuing need exists for improved high-speed signal traces on internal layers of integrated IC packages or PCBs. The disclosed subject matter relates to circuit assemblies and methods that provide reduced the capacitance to improve the chance of hitting the targeted impedance by a low-cost approach. In various embodiment, a signal layer may be located in dielectric material between two ground reference planes, and the metal area(s) on one of the two ground reference planes opposing to the traces may be removed to form an embedded microstrip structure.
In an exemplary embodiment, there is provided a circuit assembly. The circuit assembly may comprise a first ground reference plane, a second ground reference plane and a dielectric layer between the first ground reference plane and the second ground reference plane. The dielectric layer may comprise a trace embedded therein and the first ground reference plane may have an opening corresponding to the trace. The opening may have a width equal to or larger than a width of the trace.
In another exemplary embodiment, there is provided a circuit assembly. The circuit assembly may comprise a first ground reference plane, a second ground reference plane and a dielectric layer between the first ground reference plane and the second ground reference plane. The dielectric layer may comprise a pair of traces embedded therein and the first ground reference plane may have an opening corresponding to the pair of traces. The opening may have a width equal to or larger than a width of the pair of traces, which may be equal to widths of respective traces of the pair of traces and a gap between the pair of traces.
In yet another exemplary embodiment, there is provide a method for making a circuit assembly. The method may comprise forming a first conductive plane with an opening, forming a dielectric layer on the first conductive plane with a pair of traces corresponding to the opening embedded in the dielectric layer and forming a second conductive plane to sandwich the dielectric layer with the first conductive plane. The opening may have a width equal to or larger than a width of the pair of traces, which may be equal to widths of respective traces of the pair of traces and a gap between the pair of traces.
Specific embodiments according to the present disclosure will now be described in detail with reference to the accompanying figures. Like elements in the various figures are denoted by like reference numerals for consistency.
The first ground reference plane 102, the second ground reference plane 104 and the trace 108 may be made using same or different conductive materials, such as, but not limited to, copper. The dielectric layer 106 may be filled with a non-conductive dielectric material, such as, but not limited to, a prepreg material. The opening 110 may be filled with the same dielectric material as the dielectric layer 106 or a different non-conductive dielectric material.
In some embodiments, the circuit assembly 100 may be an integrated circuit (IC) package, and the first ground reference plane 102, the second ground reference plane 104 and the dielectric layer 106 with the embedded trace 108 may be part of a package substrate. In some other embodiments, the circuit assembly 100 may be a printed circuit board (PCB), and the first ground reference plane 102, the second ground reference plane 104 and the dielectric layer 106 may be part of PCB layers and the embedded trace 108 may be one of many traces of the PCB.
It should be noted that the circuit assembly 100 may have other layers in some embodiments. For example, there may be one or more layers on top of the ground reference plane 104, one or more layers underneath the ground reference plane 102, or one or more layers both on top of the ground reference plane 104 and underneath the ground reference plane 102. In some embodiments, the dielectric layer 106 may include two or more layers of different dielectric materials.
The first ground reference plane 202 may have an opening 210. In some embodiments, the traces 208.1 and 208.2 and the corresponding opening 210 may also form an embodiment of an open slot embedded microstrip structure.
The first ground reference plane 202, the second ground reference plane 204 and the traces 208.1 and 208.2 may be made using same or different conductive materials, such as, but not limited to, copper. The dielectric layer 206 may be filled with a non-conductive dielectric material, such as, but not limited to, a prepreg material. The opening 210 may be filled with the same dielectric material as the dielectric layer 206 or a different non-conductive dielectric material.
In some embodiments, the circuit assembly 200 may be an integrated circuit (IC) package, and the first ground reference plane 202, the second ground reference plane 204 and the dielectric layer 206 with the embedded traces 208.1 and 208.2 may be part of a package substrate. In some other embodiments, the circuit assembly 200 may be a printed circuit board (PCB), and the first ground reference plane 202, the second ground reference plane 204 and the dielectric layer 206 may be part of PCB layers and the embedded traces 208.1 and 208.2 may be two of many traces of the PCB.
It should be noted that the circuit assembly 200 may have other layers in various embodiments. For example, there may be one or more layers on top of the ground reference plane 204, one or more layers underneath the ground reference plane 202, or one or more layers both on top of the ground reference plane 204 and underneath the ground reference plane 202. In some embodiments, the dielectric layer 206 may include two or more layers of different dielectric materials.
The first ground reference plane 302 may have an opening 310. The opening 310 may have an elongated shape and run longitudinally parallel to the trace 308. The opening 310 may be a slot formed on the ground reference plane 302 by cutting off a portion of the ground reference plane 302 corresponding to a footprint of the trace 308 projected on the ground reference plane 302. The trace 308 may have a width D and the opening 210 may have a width W. In various embodiments, the width of the opening 310 may be equal to or larger than the width of the trace 308.
The first ground reference plane 302, the second ground reference plane 304 and the trace 308 may be made using same or different conductive materials, such as, but not limited to, copper. The dielectric layers 306.1, 306.2, 312.1 and 312.2 may be filled with the same or different non-conductive dielectric materials, such as, but not limited to, a prepreg material. The opening 310 may be filled with the same dielectric material as the dielectric layer 306.2 or a different non-conductive dielectric material.
In some embodiments, the circuit assembly 300 may be an integrated circuit (IC) package, and the first ground reference plane 302, the second ground reference plane 304, the dielectric layers 306.1 and 306.2 with the embedded trace 308 and the dielectric layers 312.1 and 312.2 may be part of a package substrate. In some other embodiments, the circuit assembly 300 may be a printed circuit board (PCB), and the first ground reference plane 302, the second ground reference plane 304 and the dielectric layers 306.1, 306.2, 312.1 and 312.2 may be part of PCB layers and the embedded trace 308 may be one of many traces of the PCB.
It should be noted that the circuit assembly 300 may have other layers in various embodiments. For example, there may be one or more layers on top of the dielectric layer 312.1, one or more layers underneath the ground reference plane 302, or one or more layers both on top of the dielectric layer 312.1 and underneath the ground reference plane 302.
It should be noted that an opening corresponding to a signal transmission line (or a pair of signal transmission lines) may be on either of the two ground reference planes sandwiching the dielectric layer in which the signal transmission line (or the pair of signal transmission lines) may be embedded therein. That is, in an embodiment of an open slot embedded microstrip structure, the opening may be in either one of the two ground reference planes sandwiching the dielectric layer in which the signal transmission line may be embedded therein. As an example,
In some embodiments, where there may be a plurality of open slot embedded microstrip structures, these multiple openings and their corresponding traces may be placed with their respective longitudinal directions according to design requirements. For example, the opening 416 (and pair of signal transmission lines 414.1 and 414.2) may have an elongated shape and run longitudinally parallel to the opening 410 (and pair of signal transmission lines 408.1 and 408.2) in
Moreover, in some embodiments, where there may be a plurality of open slot embedded microstrip structures, these traces or pairs of traces may be placed in different signal layers. For example, the pair of signal transmission lines 414.1 and 414.2 may be placed in a same signal layer as the pair of signal transmission lines 408.1 and 408.2 in
It should be noted that in some embodiments, the ground reference planes and openings may be formed using known and yet to be developed techniques for forming conductive patterns that may be insulated from other parts of a circuit assembly, which may be an IC package or a PCB. The ground reference planes may be formed using same or different conductive material, such as, but not limited to, copper or gold.
One exemplary embodiment according to the present disclosure may provide a circuit assembly that may comprise a first ground reference plane, a second ground reference plane and a dielectric layer between the first ground reference plane and the second ground reference plane. The dielectric layer may comprise a trace embedded therein and the first ground reference plane may have an opening corresponding to the trace. The opening may have a width equal to or larger than a width of the trace.
In one embodiment, the trace may be one of a pair of signal transmission lines and the opening may have a width equal to or larger than a width of the pair of signal transmission lines. The width of the pair of signal transmission lines may be equal to widths of respective signal lines of the pair of signal transmission lines and a gap between the pair of signal transmission lines.
In one embodiment, the pair of signal transmission lines may be a differential pair of signal transmission lines.
In one embodiment, the opening may have an elongated shape and run longitudinally parallel to the pair of signal transmission lines, and may be filled with a dielectric material.
In one embodiment, the trace may be part of a signal layer in a printed circuit board.
In one embodiment, the trace may be part of a signal layer in an integrated circuit package.
In one embodiment, the circuit assembly may further comprise at least another dielectric layer on a side of first ground reference plane opposite the dielectric layer, at least another dielectric layer on a side of second ground reference plane opposite the dielectric layer, or both.
Another exemplary embodiment according to the present disclosure may provide a circuit assembly that may comprise a first ground reference plane, a second ground reference plane and a dielectric layer between the first ground reference plane and the second ground reference plane. The dielectric layer may comprise a pair of traces embedded therein and the first ground reference plane may have an opening corresponding to the pair of traces. The opening may have a width equal to or larger than a width of the pair of traces, which may be equal to widths of respective traces of the pair of traces and a gap between the pair of traces.
In one embodiment, the pair of traces may be a differential pair of traces.
In one embodiment, the pair of traces may be part of a signal layer that may have a plurality of pairs of traces, and each pair of the plurality of pairs of traces may have a corresponding opening on the first ground reference plane or the second reference plane.
In one embodiment, the opening may have an elongated shape and run longitudinally parallel to the pair of traces, and may be filled with a dielectric material.
In one embodiment, the trace may be part of a signal layer in a printed circuit board.
In one embodiment, the trace may be part of a signal layer in an integrated circuit package.
In one embodiment, the circuit assembly may further comprise at least another dielectric layer on a side of first ground reference plane opposite the dielectric layer, at least another dielectric layer on a side of second ground reference plane opposite the dielectric layer, or both.
In yet another exemplary embodiment, there is provide a method for making a circuit assembly. The method may comprise forming a first conductive plane with an opening, forming a dielectric layer on the first conductive plane with a pair of traces corresponding to the opening embedded in the dielectric layer and forming a second conductive plane to sandwich the dielectric layer with the first conductive plane. The opening may have a width equal to or larger than a width of the pair of traces, which may be equal to widths of respective traces of the pair of traces and a gap between the pair of traces.
In one embodiment, the pair of traces may be a differential pair of traces.
In one embodiment, forming the dielectric layer may further comprise forming a first dielectric layer on the first conductive plane to cover the first conductive plane and the opening, forming a signal layer over the first dielectric layer and forming a second dielectric layer over the first dielectric layer and the signal layer to embed the signal layer in the second dielectric layer. The signal layer may have the pair of traces formed thereon.
In one embodiment, the opening may have an elongated shape and run longitudinally parallel to the pair of traces, and may be filled with a dielectric material.
In one embodiment, the trace may be part of a signal layer in a printed circuit board.
In one embodiment, the trace may be part of a signal layer in an integrated circuit package.
Various operations may be described as multiple discrete operations in turn, in a manner that may be helpful in understanding embodiments of the present invention; however, the order of description should not be construed to imply that these operations are order dependent. Moreover, some embodiments may include more or fewer operations than may be described.
The description may use the phrases “in an embodiment,” “in embodiments,” “in some embodiments,” or “in various embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present invention, are synonymous.
The terms “coupled to,” along with its derivatives, may be used herein. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other.
The terms chip, die, integrated circuit, monolithic device, semiconductor device, and microelectronic device are often used interchangeably in the microelectronics field. The present invention is applicable to all of the above as they are generally understood in the field.
While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.
