1. Technical Field
Embodiments of the present disclosure relate to electronic devices, and particularly to an embedded system for an electronic device.
2. Description of Related Art
Wake on LAN (WOL) is an Ethernet computer networking standard that allows a computer to be turned on or woken up by a network message. Often, an embedded system cannot perform the WOL as the computer, due to lack of a basic input and output system (BIOS). Therefore, the embedded system is designed to comprise a network interface controller (NIC) to act as the WOL of the computer. However, the resulting main chip with the NIC wastes power.
Therefore, it is desirable to provide an embedded system for power saving that addresses the described.
Referring to
The main chip 500 generates a sleep signal when the embedded system 10 is idle. In one embodiment, the term “idle” refers to the embedded system 10 receiving no packets from a network 20 and no user input within a predefined time period.
The NIC 200 receives a magic packet from the network 20, and generates a wake-up signal accordingly. In one embodiment, the magic packet is a wake on LAN (WOL) packet.
The MCU 300 sends a closing signal to the switch 400 upon receiving the wake-up signal from the NIC 200, or an opening signal to the switch 400 upon receiving the sleep signal from the main chip 500. In one embodiment, the term “closing signal” refers to one control signal to close the switch 400, and the term “opening signal” refers to another control signal to open the switch 400. The MCU 300 may be a system on chip (SOC). In another embodiment, the MCU 300 may be a transistor.
The switch 400 comprises a public terminal 401, a free terminal 402, and a control terminal 403. In one embodiment, the public terminal 401 connects to the power source 100, the free terminal 402 connects to the main chip 500 and the plurality of peripherals 600, and the control terminal 403 connects to the MCU 300. In one embodiment, the public terminal 401 connects to the free terminal 402 if the control terminal 403 receives the closing signal from the MCU 300, and disconnects from the free terminal 402 if the control terminal 403 receives the opening signal from the MCU 300.
The power source 100 connects to the NIC 200 and the MCU 300, to provide power to the NIC 200 and the MCU 300. Furthermore, the power source 100 connects to the public terminal 401 of the switch 400. The power source 100 provides power to the main chip 500 and the plurality of peripherals 600 if the public terminal 401 connects to the free terminal 402, and stops providing power to the main chip 500 and the plurality of peripherals 600 if the public terminal 401 disconnects from the free terminal 402.
In one embodiment, the power source 100 provides power to the NIC 200 and the MCU 300, and stops providing power to the main chip 500 when the embedded system 10 is in the sleep mode, thereby saving power.
The plurality of peripherals 600 comprise a flash memory, and a double data rate synchronous dynamic random access memory (DDR SDRAM). In one embodiment, the plurality of peripherals 600 exchange data with the main chip 500, and receive power from the power source 100 via the switch 400.
Referring to
In block S201, the main chip 500 generates a sleep signal, and sends the sleep signal to the MCU 300, when the embedded system 10 does not receive any packet from the network 20 or any instruction from a user within a predefined time period.
In block S202, the MCU 300 receives the sleep signal, and consequently sends an opening signal to the control terminal 403 of the switch 400.
In block S203, the public terminal 401 disconnects from the free terminal 402, when the control terminal 403 of the switch 400 receives the opening signal, and the power source 100 stops power to the main chip 500 and the plurality of peripherals 600, and the embedded system 10 enters the sleep mode.
In block S204, the NIC 200 receives a magic packet from the network 20, and consequently sends a wake-up signal to the MCU 300.
In block S205, the MCU 300 sends a closing signal to the control terminal 403 of the switch 400 upon receiving the wake-up signal.
In block S206, the public terminal 401 connects to the free terminal 402 when the control terminal 403 of the switch 400 receives the closing signal, the power source 100 provides power to the main chip 500 and the plurality of peripherals 600, and the embedded system 10 enters the operating mode.
In one embodiment, the embedded system 10 is designed to separate the NIC 200 from the main chip 500, so as to save power by stopping power to main chip 500 and the plurality of peripherals 600.
The description of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. Various embodiments were chosen and described in order to best explain the principles of the disclosure, the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
Number | Date | Country | Kind |
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201020301798.0 | Jan 2010 | CN | national |