EMITTER ASSEMBLY WITH LOCKING PINS

TECHNICAL FIELD

The present disclosure relates generally to vertical cavity surface emitting lasers (VCSELs) and to an emitter assembly with locking pins.

BACKGROUND

A vertical-emitting laser device, such as a VCSEL, is a laser in which a beam is emitted in a direction perpendicular to a surface of a substrate (e.g., vertically from a surface of a semiconductor wafer). Multiple vertical-emitting devices may be arranged in an array with a common substrate.

SUMMARY

In some implementations, an emitter assembly includes a VCSEL chip including a plurality of VCSELs. The emitter assembly may include a plurality of conductive pillars electrically connected to the VCSEL chip, and a conductive pillar, of the plurality of conductive pillars, may have a solder cap at an end of the conductive pillar. The emitter assembly may include a pin extending into the solder cap.

In some implementations, an emitter assembly includes a VCSEL chip including a plurality of VCSELs in a bottom-emitting configuration. The plurality of VCSELs may be respectively associated with a plurality of first electrical contacts. The emitter assembly may include a carrier having a plurality of second electrical contacts. The VCSEL chip may be in a flip chip configuration with the carrier. The emitter assembly may include a plurality of conductive pillars that electrically connect the plurality of first electrical contacts and the plurality of second electrical contacts. A conductive pillar, of the plurality of conductive pillars, may have a solder cap at an end of the conductive pillar. The emitter assembly may include a pin extending from one of the VCSEL chip or the carrier into the solder cap.

In some implementations, a method includes assembling a VCSEL chip in a flip chip configuration with a carrier to produce an emitter assembly. A plurality of conductive pillars may electrically connect the VCSEL chip and the carrier. A conductive pillar, of the plurality of conductive pillars, may have a solder cap at an end of the conductive pillar. One of the VCSEL chip or the carrier may include a pin for the solder cap. The method may include performing a solder reflow procedure on the emitter assembly.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are diagrams illustrating a top-view of an example emitter and a cross-sectional view of the example emitter along line X-X, respectively.

FIG. 2 shows a sectional view of an example emitter assembly.

FIG. 3A shows a sectional view of an example VCSEL with a pin.

FIG. 3B shows a sectional view of an example VCSEL with a pin.

FIG. 4 shows a sectional view of a portion of an example emitter assembly.

FIG. 5 shows a sectional view of a portion of an emitter assembly in an alternative configuration.

FIG. 6 is a flowchart of an example process associated with manufacturing an emitter assembly with locking pins.

DETAILED DESCRIPTION

The following detailed description of example implementations refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements.

In some examples, a top-emitting vertical cavity surface emitting laser (VCSEL) chip may be mounted on a substrate side-by-side with an integrated circuit (IC) driver chip for the VCSEL chip and connected by wire bonding and substrate traces. In some other examples, a bottom-emitting VCSEL chip may be flip chip bonded on an IC driver chip (which may be referred to as a VCSEL-on-driver (VoD) configuration), thereby shortening connections between the VCSEL chip and the IC driver chip and improving control over the VCSEL chip. A time-of-flight (ToF) camera may include such a VoD device to achieve improved three-dimensional (3D) sensing accuracy.

In a VoD device, an emitter pitch of a VCSEL chip may be in a range from approximately 35 micrometers (μm) to 50 μm depending on particular optical requirements for the VoD device. However, a pitch of electrical contacts (e.g., solder bumps or bond pads) of an IC driver chip of the VoD device may be 45 μm or greater (e.g., 60 μm). In other words, the VCSEL chip may have a finer pitch than the IC driver chip. In some cases, to resolve the mismatch in pitches, the pitch of the electrical contacts of the IC driver chip may be redistributed to match the pitch of the VCSEL chip by wafer reconstruction of the IC driver chip using a redistribution layer (RDL). In other words, the redistribution layer may provide reduction of the pitch of the electrical contacts of the IC driver chip. In some examples, conductive (e.g., copper (Cu)) pillars may be used for connecting the VCSEL chip to the IC driver chip.

When these conductive pillars have a fine pitch, achieving passive alignment using solder reflow in mass production is difficult because vibration in a transfer belt or a reflow oven belt may misalign the VCSEL chip before the solder is melted. Thus, for smaller pitches (e.g., 45 μm or less), bonding of the VCSEL chip to the IC chip may be achieved using thermal compression bonding (TCB) with active alignment rather than conventional solder mass reflow. Compared to solder mass reflow, TCB is complex, expensive, and associated with a low throughput, such as a low units per hour (UPH). For example, TCB may involve a temperature ramp-up and cooling down of a bonding head, which can be slow, resulting in low throughput. In some examples, chip-on-wafer TCB bonding of VCSEL chips to an IC wafer may be used to improve throughput. However, chip-on-wafer TCB bonding may be unsuitable for various solders (e.g., tin/silver solders) because the bonding temperature may remelt the solder of neighboring chips.

Some implementations described herein enable the use of solder mass reflow for an emitter assembly having an array of VCSELs arranged with a fine pitch. In some implementations, the emitter assembly may include a carrier (e.g., an IC chip, a circuit board, or the like), a VCSEL chip in a flip chip configuration with the carrier, and conductive pillars arranged according to the fine pitch that electrically connect the VCSEL chip and the carrier. In some implementations, the emitter assembly may include pins extending from one of the VCSEL chip or the carrier that extend into solder caps of the conductive pillars. The pins may minimize misalignment between the VCSEL chip and the carrier that may otherwise be caused by vibration of a conveyor belt and/or a reflow oven belt during solder mass reflow. Accordingly, the emitter assembly may be manufactured with a reduced cost and complexity and at a greater throughput using solder mass reflow.

FIGS. 1A and 1B are diagrams illustrating a top-view of an example emitter 100 and a cross-sectional view 150 of the example emitter 100 along line X-X, respectively. As shown in FIG. 1A, emitter 100 may include a set of emitter layers constructed in an emitter architecture. In some implementations, emitter 100 may correspond to one or more vertical-emitting devices described herein.

As shown in FIG. 1A, emitter 100 may include an implant protection layer 102 that is circular in shape in this example. In some implementations, implant protection layer 102 may have another shape, such as an elliptical shape, a polygonal shape, or the like. Implant protection layer 102 is defined based on a space between sections of implant material (not shown) included in emitter 100.

As shown by the medium gray and dark gray areas in FIG. 1A, emitter 100 includes an ohmic metal layer 104 (e.g., a P-Ohmic metal layer or an N-Ohmic metal layer) that is constructed in a partial ring-shape (e.g., with an inner radius and an outer radius). The medium gray area shows an area of ohmic metal layer 104 covered by a protective layer (e.g., a dielectric layer or a passivation layer) of emitter 100, and the dark gray area shows an area of ohmic metal layer 104 exposed by via 106, described below. As shown, ohmic metal layer 104 overlaps with implant protection layer 102. Such a configuration may be used, for example, in the case of a P-up/top-emitting emitter 100. In the case of a bottom-emitting emitter 100, the configuration may be adjusted as needed.

Not shown in FIG. 1A, emitter 100 includes a protective layer in which via 106 is formed (e.g., etched). The dark gray area shows an area of ohmic metal layer 104 that is exposed by via 106 (e.g., the shape of the dark gray area may be a result of the shape of via 106) while the medium gray area shows an area of ohmic metal layer 104 that is covered by some protective layer. The protective layer may cover all of the emitter other than the vias. As shown, via 106 is formed in a partial ring-shape (e.g., similar to ohmic metal layer 104) and is formed over ohmic metal layer 104 such that metallization on the protection layer contacts ohmic metal layer 104. In some implementations, via 106 and/or ohmic metal layer 104 may be formed in another shape, such as a full ring-shape or a split ring-shape.

As further shown, emitter 100 includes an optical aperture 108 in a portion of emitter 100 within the inner radius of the partial ring-shape of ohmic metal layer 104. Emitter 100 emits a laser beam via optical aperture 108. As further shown, emitter 100 also includes a current confinement aperture 110 (e.g., an oxide aperture formed by an oxidation layer of emitter 100 (not shown)). Current confinement aperture 110 is formed below optical aperture 108.

As further shown in FIG. 1A, emitter 100 includes a set of trenches 112 (e.g., oxidation trenches) that are spaced (e.g., equally, unequally) around a circumference of implant protection layer 102. How closely trenches 112 can be positioned relative to the optical aperture 108 is dependent on the application, and is typically limited by implant protection layer 102, ohmic metal layer 104, via 106, and manufacturing tolerances.

The number and arrangement of layers shown in FIG. 1A are provided as an example. In practice, emitter 100 may include additional layers, fewer layers, different layers, or differently arranged layers than those shown in FIG. 1A. For example, while emitter 100 includes a set of six trenches 112, in practice, other configurations may be used, such as a compact emitter that includes five trenches 112, seven trenches 112, or another quantity of trenches. In some implementations, trenches 112 may encircle emitter 100 to form a mesa structure d_t(shown in FIG. 1B). As another example, while emitter 100 is a circular emitter design, in practice, other designs may be used, such as a rectangular emitter, a hexagonal emitter, an elliptical emitter, or the like. Additionally, or alternatively, a set of layers (e.g., one or more layers) of emitter 100 may perform one or more functions described as being performed by another set of layers of emitter 100, respectively.

Notably, while the design of emitter 100 is described as including a VCSEL, other implementations are contemplated. For example, the design of emitter 100 may apply in the context of another type of optical device, such as a light emitting diode (LED), or another type of vertical emitting (e.g., top emitting or bottom emitting) optical device. Additionally, the design of emitter 100 may apply to emitters of any wavelength, power level, and/or emission profile. In other words, emitter 100 is not particular to an emitter with a given performance characteristic.

As shown in FIG. 1B, the example cross-sectional view may represent a cross-section of emitter 100 that passes through, or between, a pair of trenches 112 (e.g., as shown by the line labeled “X-X” in FIG. 1A). As shown, emitter 100 may include a backside cathode layer 128, a substrate layer 126, a bottom mirror 124, an active region 122, an oxidation layer 120, a top mirror 118, an implant isolation material 116, a protective layer 114 (e.g., a dielectric passivation/mirror layer), and an ohmic metal layer 104. As shown, emitter 100 may have, for example, a total height that is approximately 10 micrometers (μm).

Backside cathode layer 128 may include a layer that makes electrical contact with substrate layer 126. For example, backside cathode layer 128 may include an annealed metallization layer, such as an AuGeNi layer, a PdGeAu layer, or the like.

Substrate layer 126 may include a base substrate layer upon which epitaxial layers are grown. For example, substrate layer 126 may include a semiconductor layer, such as a GaAs layer, an InP layer, and/or another type of semiconductor layer.

Bottom mirror 124 may include a bottom reflector layer of emitter 100. For example, bottom mirror 124 may include a distributed Bragg reflector (DBR).

Active region 122 may include a layer that confines electrons and defines an emission wavelength of emitter 100. For example, active region 122 may be a quantum well.

Oxidation layer 120 may include an oxide layer that provides optical and electrical confinement of emitter 100. In some implementations, oxidation layer 120 may be formed as a result of wet oxidation of an epitaxial layer. For example, oxidation layer 120 may be an Al₂O₃layer formed as a result of oxidation of an AlAs or AlGaAs layer. Trenches 112 may include openings that allow oxygen (e.g., dry oxygen, wet oxygen) to access the epitaxial layer from which oxidation layer 120 is formed.

Current confinement aperture 110 may include an optically active aperture defined by oxidation layer 120. A size of current confinement aperture 110 may range, for example, from approximately 4 μm to approximately 20 μm. In some implementations, a size of current confinement aperture 110 may depend on a distance between trenches 112 that surround emitter 100. For example, trenches 112 may be etched to expose the epitaxial layer from which oxidation layer 120 is formed. Here, before protective layer 114 is formed (e.g., deposited), oxidation of the epitaxial layer may occur for a particular distance (e.g., identified as d_oin FIG. 1B) toward a center of emitter 100, thereby forming oxidation layer 120 and current confinement aperture 110. In some implementations, current confinement aperture 110 may include an oxide aperture. Additionally, or alternatively, current confinement aperture 110 may include an aperture associated with another type of current confinement technique, such as an etched mesa, a region without ion implantation, lithographically defined intra-cavity mesa and regrowth, or the like.

Top mirror 118 may include a top reflector layer of emitter 100. For example, top mirror 118 may include a DBR.

Implant isolation material 116 may include a material that provides electrical isolation. For example, implant isolation material 116 may include an ion implanted material, such as a hydrogen/proton implanted material or a similar implanted element to reduce conductivity. In some implementations, implant isolation material 116 may define implant protection layer 102.

Protective layer 114 may include a layer that acts as a protective passivation layer, and which may act as an additional DBR. For example, protective layer 114 may include one or more sub-layers (e.g., a dielectric passivation layer and/or a mirror layer, a SiO₂layer, a Si₃N₄layer, an Al₂O₃layer, or other layers) deposited (e.g., by chemical vapor deposition, atomic layer deposition, or other techniques) on one or more other layers of emitter 100.

As shown, protective layer 114 may include one or more vias 106 that provide electrical access to ohmic metal layer 104. For example, via 106 may be formed as an etched portion of protective layer 114 or a lifted-off section of protective layer 114. Optical aperture 108 may include a portion of protective layer 114 over current confinement aperture 110 through which light may be emitted.

Ohmic metal layer 104 may include a layer that makes electrical contact through which electrical current may flow. For example, ohmic metal layer 104 may include a Ti and Au layer, a Ti and Pt layer and/or an Au layer, or the like, through which electrical current may flow (e.g., through a bondpad (not shown) that contacts ohmic metal layer 104 through via 106). Ohmic metal layer 104 may be P-ohmic, N-ohmic, or other forms known in the art. Selection of a particular type of ohmic metal layer 104 may depend on the architecture of the emitters and is well within the knowledge of a person skilled in the art. Ohmic metal layer 104 may provide ohmic contact between a metal and a semiconductor, may provide a non-rectifying electrical junction, and/or may provide a low-resistance contact. In some implementations, emitter 100 may be manufactured using a series of steps. For example, bottom mirror 124, active region 122, oxidation layer 120, and top mirror 118 may be epitaxially grown on substrate layer 126, after which ohmic metal layer 104 may be deposited on top mirror 118. Next, trenches 112 may be etched to expose oxidation layer 120 for oxidation. Implant isolation material 116 may be created via ion implantation, after which protective layer 114 may be deposited. Via 106 may be etched in protective layer 114 (e.g., to expose ohmic metal layer 104 for contact). Plating, seeding, and etching may be performed, after which substrate layer 126 may be thinned and/or lapped to a target thickness. Finally, backside cathode layer 128 may be deposited on a bottom side of substrate layer 126.

The number, arrangement, thicknesses, order, symmetry, or the like, of layers shown in FIG. 1B are provided as an example. In practice, emitter 100 may include additional layers, fewer layers, different layers, differently constructed layers, or differently arranged layers than those shown in FIG. 1B. Additionally, or alternatively, a set of layers (e.g., one or more layers) of emitter 100 may perform one or more functions described as being performed by another set of layers of emitter 100, and any layer may comprise more than one layer.

FIG. 2 shows a sectional view of an example emitter assembly 200. The emitter assembly 200 may include a VCSEL chip 202 (e.g., a VCSEL device). The VCSEL chip 202 may include a plurality of VCSELs 204 (i.e., a VCSEL array). For example, the VCSEL chip 202 may include a semiconductor die with the VCSELs 204 formed therein. In some implementations, the VCSELs 204 may be arranged in a plurality of rows, and alternating rows may be shifted relative to each other. The VCSELs 204 may be configured in a similar manner as described in connection with FIGS. 1A-1B. In some implementations, the VCSELs 204 may be in a bottom-emitting configuration. For example, in a bottom-emitting configuration, a top of a VCSEL 204 may be covered by an electrical contact (e.g., a bond pad), and the VCSEL 204 may emit light down through a substrate of the VCSEL 204.

The VCSELs 204 may be respectively associated with a plurality of first electrical contacts 206 (e.g., bond pads) in a similar manner as described in connection with FIGS. 1A-1B. A location of an electrical contact 206 of a VCSEL 204 may dictate a location of an emission area of the VCSEL 204. A first spacing of the first electrical contacts 206 from each other (from centers of the first electrical contacts 206) may define a first pitch associated with the VCSEL chip 202. Stated differently, the first spacing of the VCSELs 204 may define the first pitch associated with the VCSEL chip 202.

The emitter assembly 200 may include a carrier 208 for the VCSEL chip 202. The carrier 208 may include a base layer 208a, such as an IC chip (e.g., a driver chip for the VCSEL chip 202), a substrate (e.g., a circuit board, such as a printed circuit board), or the like. For example, the emitter assembly 200 may include a VoD device. The carrier 208 may include a plurality of second electrical contacts 210 (e.g., bond pads). A second spacing of the second electrical contacts 210 from each other (from centers of the second electrical contacts 210) may define a second pitch associated with the carrier 208. In some implementations, the second pitch may be different from the first pitch. For example, the second pitch may be greater than the first pitch. In some implementations, the first pitch may be less than 45 μm (e.g., 40 μm), which may be referred to as a “fine pitch,” and the second pitch may be greater than or equal to 45 μm (e.g., 60 μm). In some implementations, the first pitch and the second pitch may be the same.

In some implementations, the carrier 208 may include a surface layer 212 disposed on the base layer 208a. The surface layer 212 may include an isolation layer, a protective layer, or a redistribution layer. The surface layer 212 may include a polymer, such as polyimide, or SiO₂. As a redistribution layer, the surface layer 212 may include a dielectric material (e.g., polyimide). In some implementations, as a redistribution layer, the surface layer 212 may be configured to decrease a pitch of the second electrical contacts 210 to the first pitch associated with the VCSEL chip 202. For example, the surface layer 212 may include (e.g., in the polyimide) a plurality of conductive traces 214 (e.g., composed of copper, aluminum, gold, and/or silver, among other examples) configured to redistribute the second electrical contacts 210 over a smaller area. The conductive traces 214 may be respectively connected to the second electrical contacts 210. In some implementations, an isolation layer 216 may be disposed between the base layer 208a and the surface layer 212. For example, the isolation layer 216 may include silicon nitride.

In some implementations, the VCSEL chip 202 may be in a flip chip configuration (i.e., a direct chip attach configuration) with the carrier 208. That is, the VCSEL chip 202 may be disposed on the carrier 208. The emitter assembly 200 may include a plurality of conductive pillars 218 (e.g., posts, columns, or the like) that connect the VCSEL chip 202 and the carrier 208. The conductive pillars 218 may include a metal, such as copper, silver, gold, or the like. A conductive pillar 218 may include a solder cap 220 (e.g., composed of a tin/silver solder) at an end of the conductive pillar 218 (e.g., with a nickel layer between the conductive pillar 218 and the solder cap 220).

The conductive pillars 218 may be arranged according to the first spacing that defines the first pitch associated with the VCSEL chip 202. The conductive pillars 218 may electrically connect the first electrical contacts 206 associated with the VCSELs 204 and the second electrical contacts 210 (e.g., via the surface layer 212). For example, first ends of the conductive pillars 218 may be electrically and mechanically connected to the first electrical contacts 206, and second ends of the conductive pillars 218 may be electrically and mechanically connected to the conductive traces 214 of the surface layer 212 (and electrically connected to the second electrical contacts 210 via the conductive traces 214). As an example, the surface layer 212 may be disposed on the base layer 208a of the carrier 208 between the base layer 208a and the conductive pillars 218, and the surface layer 212 may electrically connect the second electrical contacts 210, with the second pitch, and the conductive pillars 218 with the first pitch. In some implementations, the conductive pillars 218 may extend from the VCSEL chip 202 to the carrier 208 (e.g., the solder caps 220 may be on the side of the carrier 208). In some implementations, the conductive pillars 218 may extend from the carrier 208 to the VCSEL chip 202 (e.g., the solder caps 220 may be on the side of the VCSEL chip 202, as shown). In some implementations, each of the conductive pillars 218 may have a maximum diameter less than 25 μm.

The emitter assembly 200 may include one or more pins 222 (which may also be referred to as “needles”). For example, the emitter assembly 200 may include multiple pins 222. A pin 222 may include an elongated cylinder, cone, cuboid, or the like. A pin 222 may extend from one of the VCSEL chip 202 or the carrier 208. For example, the pin 222 may extend from a different one of the VCSEL chip 202 or the carrier 208 from which the conductive pillars 218 extend. As shown in FIG. 2, the conductive pillars 218 may extend from the carrier 208 to the VCSEL chip 202, and the pins 222 may extend from the VCSEL chip 202. For example, the pins 222 may extend from respective electrical contacts 206 of the VCSEL chip 202. In some implementations, the conductive pillars 218 may extend from the VCSEL chip 202 to the carrier 208, and the pins 222 may extend from the carrier 208. For example, the pins 222 may extend from the surface layer 212 (e.g., from respective conductive traces 214 of the surface layer 212).

In some implementations, a pin 222 may be composed of an electrically-conductive material (e.g., copper). In some implementations, a pin 222 may be electrically connected to a conductive pillar 218, to the VCSEL chip 202 (e.g., to an electrical contact 206), and/or to the carrier 208 (e.g., to an electrical contact 210). In some implementations, a pin 222 may be composed of a non-electrically-conductive material, and the pin 222 may be mechanically connected to the VCSEL chip 202 or the carrier 208.

A pin 222 may align with a conductive pillar 218, and the pin 222 may extend into a solder cap 220 of the conductive pillar 218. For example, as shown in FIG. 2, one or more pins 222 may extend from respective VCSELs 204 of the VCSEL chip 202 into solder caps 220 of conductive pillars 218 that extend from the carrier 208. Additionally, or alternatively, one or more pins 222 may extend from the carrier 208 (e.g., from conductive traces 214 of the surface layer 212) into solder caps 220 of conductive pillars 218 that extend from the VCSEL chip 202.

In some implementations, pins 222 may extend from or toward each VCSEL 204 (e.g., from or toward each electrical contact 206) of the VCSEL chip 202. For example, a first quantity of the pins 222 corresponds to a second quantity of the VCSELs 204. In some implementations, pins 222 may extend from or toward less than all of the VCSELs 204 (e.g., from or toward each electrical contact 206) of the VCSEL chip 202. For example, a first quantity of the pins 222 is less than a second quantity of the VCSELs 204. In some implementations, the first electrical contacts 206 may be arranged in an array (e.g., a grid), and pins 222 may extend from or toward one or more electrical contacts 206 at a perimeter (e.g., at corners) of the array.

Prior to reflow, solder caps 220 of conductive pillars 218 may be heated at a temperature below a melting point of the solder caps 220 (e.g., to a soft consistency), and the pins 222 may be tacked into the heated solder caps 220. The pins 222 tacked into the solder caps 220 may minimize misalignment between the VCSEL chip 202 and the carrier 208 that may otherwise be caused by vibration of a conveyor belt and/or a reflow oven belt during solder mass reflow. Moreover, the pins 222 may impose minimal restriction to self-alignment of the conductive pillars 218 and the first electrical contacts 206 during solder reflow. Accordingly, the emitter assembly 200 may be suitable for solder mass reflow (e.g., for bonding the VCSEL chip 202 and the carrier 208), thereby facilitating manufacture of the emitter assembly 200 at reduced cost and complexity and with improved throughput. In some implementations, TCB may be used for bonding the VCSEL chip 202 and the carrier 208.

As indicated above, FIG. 2 is provided as an example. Other examples may differ from what is described with regard to FIG. 2.

FIG. 3A shows a sectional view of an example VCSEL 204 with a pin 222 (inverted from the orientation shown in FIG. 2). As shown, the pin 222 may extend from an electrical contact 206 (e.g., a bond pad) disposed on a top of the VCSEL 204. The electrical contact 206 may include an Ohmic metal layer, as described herein. The pin 222 (e.g., composed of copper) may be plated on the electrical contact 206. In some implementations, the pin 222 may be covered in an Ohmic metal layer (e.g., a platinum or palladium layer and/or a gold layer). As shown in FIG. 3A, the pin 222 may be in the shape of a cylinder or a cuboid.

As indicated above, FIG. 3A is provided as an example. Other examples may differ from what is described with regard to FIG. 3A.

FIG. 3B shows a sectional view of an example VCSEL 204 with a pin 222 (inverted from the orientation shown in FIG. 2). As shown, the pin 222 may extend from an electrical contact 206 (e.g., a bond pad) disposed on a top of the VCSEL 204, in a similar manner as described in connection with FIG. 3A. As shown in FIG. 3B, the pin 222 may be in the shape of a cone.

As indicated above, FIG. 3B is provided as an example. Other examples may differ from what is described with regard to FIG. 3B.

FIG. 4 shows a sectional view of a portion of the emitter assembly 200. The left diagram in FIG. 4 shows the emitter assembly 200 before solder reflow is performed on the emitter assembly 200, and the right diagram in FIG. 4 shows the emitter assembly 200 after solder reflow is performed on the emitter assembly 200. In particular, FIG. 4 shows bonding of a pin 222 to a conductive pillar 218 of the carrier 208 (e.g., an IC chip).

As shown, the pin 222 may extend from an electrical contact 206 associated with a VCSEL 204 of the VCSEL chip 202, as described herein. Prior to reflow, a solder cap 220 of the conductive pillar 218 may be heated to just below a melting point of the solder cap 220, the VCSEL chip 202 may be aligned with the carrier 208, and the VCSEL chip 202 and the carrier 208 may be brought together to tack the pin 222 into the solder cap 220. The pin 222 tacked into the solder cap 220 may hold the conductive pillar 218 in alignment with the VCSEL 204 prior to reflow. After reflow, the pin 222 may sink further into the solder cap 220 to facilitate electrical connection of the electrical contact 206 and the solder cap 220.

As indicated above, FIG. 4 is provided as an example. Other examples may differ from what is described with regard to FIG. 4.

FIG. 5 shows a sectional view of a portion of the emitter assembly 200 in an alternative configuration. The left diagram in FIG. 5 shows the emitter assembly 200 before solder reflow is performed on the emitter assembly 200, and the right diagram in FIG. 5 shows the emitter assembly 200 after solder reflow is performed on the emitter assembly 200.

As shown, a pin 222 may extend from the carrier 208, as described herein. Prior to reflow, a solder cap 220 of a conductive pillar 218 may be heated to just below a melting point of the solder cap 220, the VCSEL chip 202 may be aligned with the carrier 208, and the VCSEL chip 202 and the carrier 208 may be brought together to tack the pin 222 into the solder cap 220. The pin 222 tacked into the solder cap 220 may hold the conductive pillar 218 in alignment with the carrier 208 prior to reflow. After reflow, the pin 222 may sink further into the solder cap 220 to facilitate electrical connection of the carrier 208 and the solder cap 220.

The pin 222 may include a set of layers that may include, from bottom to top, a copper layer, a nickel layer, and a gold layer. In some implementations, the pin 222 may include a base element 224 that provides a wider area for the electrical connection with the solder cap 220.

As indicated above, FIG. 5 is provided as an example. Other examples may differ from what is described with regard to FIG. 5.

FIG. 6 is a flowchart of an example process 600 associated with manufacturing an emitter assembly with locking pins. In some implementations, one or more process blocks of FIG. 6 may be performed by various semiconductor manufacturing equipment, various circuit board assembly equipment, and/or various solder reflow equipment (e.g., which may include one or more conveyors and/or one or more reflow ovens).

As shown in FIG. 6, process 600 may include assembling a VCSEL chip in a flip chip configuration with a carrier to produce an emitter assembly (block 610). In some implementations, a plurality of conductive pillars electrically connect the VCSEL chip and the carrier, and a conductive pillar, of the plurality of conductive pillars, may have a solder cap at an end of the conductive pillar. In some implementations, one of the VCSEL chip or the carrier includes a pin for the solder cap. In some implementations, assembling the VCSEL chip in the flip chip configuration with the carrier includes heating the solder cap below a melting point of the solder cap, and tacking the pin into the solder cap. In some implementations, process 600 includes applying solder flux on the carrier prior to assembling the VCSEL chip in the flip chip configuration with the carrier.

As further shown in FIG. 6, process 600 may include performing a solder reflow procedure on the emitter assembly (block 620). In some implementations, process 600 may include forming the VCSEL chip, forming the carrier, and/or forming an assembly that includes the emitter assembly.

Although FIG. 6 shows example blocks of process 600, in some implementations, process 600 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 6. Additionally, or alternatively, two or more of the blocks of process 600 may be performed in parallel.

The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the implementations. Furthermore, any of the implementations described herein may be combined unless the foregoing disclosure expressly provides a reason that one or more implementations may not be combined.

Even though particular combinations of features are recited in the claims and/or disclosed in the specification, these combinations are not intended to limit the disclosure of various implementations. In fact, many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various implementations includes each dependent claim in combination with every other claim in the claim set. As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiple of the same item.

No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles “a” and “an” are intended to include one or more items, and may be used interchangeably with “one or more.” Further, as used herein, the article “the” is intended to include one or more items referenced in connection with the article “the” and may be used interchangeably with “the one or more.” Furthermore, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items), and may be used interchangeably with “one or more.” Where only one item is intended, the phrase “only one” or similar language is used. Also, as used herein, the terms “has,” “have,” “having,” or the like are intended to be open-ended terms. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. Also, as used herein, the term “or” is intended to be inclusive when used in a series and may be used interchangeably with “and/or,” unless explicitly stated otherwise (e.g., if used in combination with “either” or “only one of”). Further, spatially relative terms, such as “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the apparatus, device, and/or element in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

EMITTER ASSEMBLY WITH LOCKING PINS

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