NSF Award
0829824
Hybrid CMOS-Nano-CMOS Architectures and CAD Tools <br/>for Nanoelectronic and Bio-Inspired Applications<br/><br/>Abstract<br/><br/>Emerging within the still novel field of nanoelectronics are many technologies that offer features such as reconfigurability, non-volatile memory, and low power consumption. Through this work, we intend to explore ways in which such attractive properties can be exploited in the design and development of a high-density reconfigurable architecture. This project combines two leading technological concepts for the development of future electronic systems: hybrid CMOS-nanoelectronic circuits and 3D integration. Our project will focus on studying methodologies associated with the design and development of novel 3D CMOS-nano-CMOS circuits. Specifically, we will prototype and evaluate a small hybrid CMOS-nano circuit consisting of a multistage nanoscale PLA based on metal oxide nanoelectronic switches with a direct interface to a layer of CMOS circuitry. The goal of this project is to lay the groundwork for developing more complex 3D CMOS-nano systems in the future. As part of this research, we will study methods for accurately modeling nanoelectronic devices and circuits for robust design, optimizing CMOS-nano-CMOS circuit designs using state of the art CAD techniques and fabricating and integrating these different technologies on a single die.
