Patent Application
20130346680
1. Field
This disclosure relates generally to memory systems, and more specifically, to emulated electrically erasable (EEE) memory.
2. Related Art
Emulated electrically erasable (EEE) memories typically use a random access memory (RAM) and a non-volatile memory such as flash memory that is electrically erasable combined to provide a memory system that has increased endurance over a regular non-volatile memory for a comparable size to that of the RAM. This is achieved using a non-volatile memory much larger than the RAM but EEE memory operates as if it were only the size of the RAM. Thus the EEE memory emulates an electrically erasable memory of a reduced size from that which is used by the EEE memory but with an increase in endurance.
EEE memories use the RAM to display the contents of the emulated memory, but become non-competitive when the intended emulated EEprom becomes large. Elimination of the RAM means slow access time via search based methodologies.
Accordingly, there is a need to provide an EEE memory that improves upon the issue described above to allow the non-volatile flash memory to be competitive with electrically-erasible programmable read-only memory (EEPROM).
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
In one aspect an emulated electrically erasable (EEE) memory has a non-volatile memory (NVM) divided into sectors and a random access memory (RAM) for storing address information for the NVM. Address information is stored in a type of RAM memory that allows access to the data records held in the NVM in two clock cycles. The NVM and the address RAM work together to protect against loss of data that can occur during a power supply surge or drop during record creation. Distributed compress/erase operations can be implemented in conjunction with burst program modes to allow for quick response to commands. This is better understood by reference to the drawings and the following description.
In one embodiment, a flash memory is used as the NVM. In one example, and as used herein, programming refers to storing a logic level zero to a bitcell and erasing refers to storing a logic level one to a bitcell. However, in alternate embodiments, programming may refer to storing a logic level one to a bitcell and erasing may refer to storing a logic level zero to a bitcell. A logic level zero may also be referred to as a logic low and a logic level one may also be referred to as a logic high.
The terms “assert” or “set” and “negate” (or “deassert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.
Processor 102 can be any type of processor, such as a microprocessor, digital signal processor, etc., or may be any other type of interconnect master which can access EEE memory system 114. System 100 can also include components that are not shown in
In operation, processor 102 can send access requests (read or write access requests) to memory system 114. The access requests from processor 102, which include a full address, and, in the case of a write access, associated write data, are provided to memory controller 104. The full address includes a lookup address and the corresponding location in the data block associated with the lookup address. Address RAM 106 includes a table that translates the lookup addresses to a corresponding data portion address. In the case of a read access, data section 110 provides processor 104 the data corresponding to the location specified by the full address. In the case of a write access, data section 110 stores the received write data as new records at the received address location. In the case of a write access, memory controller 104 may detect an update of flash array 108 and provide updated data block addresses from address system 112 to address RAM 106.
As an example with an address system 112 that uses 32 bit records, the top 16 bits can hold a 64 byte location within a 128 k EEE image. The lower 16 bits point to the physical location of a 64 byte block within the data portion 110. For a 128 k EEE image with 64 byte blocks, 8 k of flash memory would include 2 k for address locations within address system 112. The entire system can include two or more EEE images, and would require 8 k of flash memory for each EEE image.
The physical address of all 64 byte blocks is transferred into address RAM at the address corresponding to the 64 byte offset in the upper word. The transfer process can be automated using test logic with an overhead of 1 cycle per record within the 8 k address system 112. Thus, updating the address RAM 106 for a system with an 8 k address system 112 would require 10 us for a 25 mHz clock rate.
Blocks in data portion 110 can be read as a standard electrically erasable programmable read-only memory in two automated steps that include (1) removing upper address bits from a lookup address to determine the data portion address in address RAM 106, and (2) combining the data portion address with the location of the data in the data section 110 to access the specific data within the data section 110. The automated steps each require 1 clock cycle.
The unused bytes 510 can be used as record status fields for additional blocks, tracking sector erase counts, or left unused, depending on the size of data portion 110.
Process 904 can include determining a setting for record status fields 504-508 (
Process 906 can include programming or writing to the data block. Note that data can be written to either a single bit in the flash array, dr a burst program mode can be used to write to a group of bits with the address giving the starting bit to be written within a block identified by the address. The corresponding record status fields 502-508 can also be written in data portion 110 as part of process 906. A single write operation, as opposed to a burst write operation, can be used to write to one of the record status fields 502-508.
Process 908 can include writing the data portion address and the location in the data block to the address system 112. The data portion address and the location in the data block corresponds to the data being written to data portion 110. Note that no search is required to determine the data portion address since the information is readily determined using the lookup address in the address system 112.
In process 909, memory controller 104 changes the record status to complete and sends the updated record status to flash array 108.
Process 910 can include determining whether a compress or an erase operation is to be performed. In accordance with the determination that a compress operation will be performed in process 910, process 912 can compress the input data according to a predetermined compression algorithm, thereby reducing the size of data stored in the memory block. In accordance with the determination that an erase operation will be performed in process 910, process 914 performs an erase operation during which data stored in one or more pages in a single block are sequentially erased;
After process 912 or 914 is performed, or after process 910 determines that no compress or erase operation is to be performed with the write operation, process 916 includes updating memory controller 104 and address RAM 106 with updated lookup addresses from address system 112.
As an example, Table 1 below shows the time required to perform method 900:
When system 100 is used for a copy down process, the data portion address and corresponding lookup addresses need to be provided to the address RAM 106, which can be accomplished by only copying records in the active sectors in the address system 112 to the address RAM 106. No search is required since the data record location can be obtained from the address RAM 106. The address records are unique and as such can be added and differentiated easily during a compression.
By now it should be appreciated that there has been provided systems and methods that use separate record systems for addresses and data to manage EEE image(s) in data portion 110. Read access to the data portion 110 is performed via the address RAM 106 enabling a much larger EE space to be emulated without a large RAM and still have fast read access. Record status fields 504-508 help ensure that data portion 110 is not corrupted during power surges or drop-offs. Additionally, copydown is eliminated for data since only address records need to be copied at reset. Searches for the most recent data in one or more EEE images do not need to be done at any time in system 100. System 100 thus emulates much larger EEE systems than previously possible while improving performance over known EEPROM arrays.
In some embodiments, a memory system comprises a memory controller 104; an address RAM 106 coupled to the memory controller 106; and a non-volatile memory 108 coupled to the memory controller. The non-volatile memory has an address portion 112 and a data portion 110. The address portion 112 of the non-volatile memory 108 provides data portion addresses and lookup addresses of valid data to the memory controller. The memory controller loads the data portion addresses and stores them in the address RAM at locations defined by the data portion addresses of valid data into the address RAM. The memory controller uses the data portion addresses, and locations of data blocks within the address RAM, to locate the data blocks within the data portion of non-volatile memory. The memory controller uses the data portion addresses, and locations of the data portion addresses within the address RAM, to locate data blocks within the data portion of non-volatile memory.
In another aspect, the memory system can further comprise a processor coupled to the data portion of the non-volatile memory. Responsive to a system address provided by the processor, the address RAM provides, to the non-volatile memory, a data portion address from a location in the address RAM selected by the system address.
In another aspect, the system address can comprise a lookup address that identifies a location in the address RAM.
In another aspect, the system address further comprises a data portion address, the memory system can further comprise a logic gate 116 that combines a data portion address provided from the address RAM with the data portion address to select valid data from the data portion 110.
In other embodiments, a method of operating a memory system 100 having a non-volatile memory (NVM), can comprise identifying a first NVM location in the NVM, wherein the first NVM location has first valid data; loading, in a first RAM location of an address RAM 106, an address of the first NVM location; providing a system address for selecting the first RAM location; responsive to the system address for selecting the first RAM location, providing the address of the first NVM location to the NVM from the address RAM; and providing the first valid data from the first NVM location in response to receiving the address of the first NVM location from the address RAM.
In another aspect, the identifying the first NVM location is further characterized by the first NVM location having additional valid data; and the providing the system address is further characterized by the system address having a first portion for selecting the first RAM location and a second portion for selecting the first valid data from among the first valid data and the additional valid data.
In another aspect, the method can further comprise writing the first valid data and the additional valid data into the NVM location as part of a burst operation.
In another aspect, the method can further comprise compressing valid data in the NVM by copying the valid data from sectors that include invalid data into one or more sectors that include only the valid data; and changing a status indicator for each of the sectors that include only the invalid data.
In another aspect, the method can further comprise providing second valid data to be written to the NVM to the memory controller with a corresponding system address; and writing the second valid data into a second NVM location in a data portion of the NVM using an address system of the NVM.
In another aspect, the method can further comprise loading the address RAM with the location of the second valid data.
In another aspect, the method can further comprise providing the address corresponding to the second valid data; obtaining the location of the second valid data from the address RAM; and providing the location of the second valid data obtained from the address RAM to the NVM to obtain the second valid data from the NVM.
In another aspect, the second valid data can be obtained from the data portion 110 of NVM.
In another aspect, the data portion can include status information.
In another aspect, the data portion can comprise data blocks wherein access to a location includes a combination of identifying the data block and a location within the data block.
In another aspect, during a read, the location within the data block is provided by the system address and the identification of the data block is from the address RAM.
In still other embodiments, a memory system 100, comprises a non-volatile memory 108 having a data portion 110 and an address system 112; a data processor 102 that writes data to the data portion according to system addresses; a memory controller 104, coupled to the non-volatile memory and the processor, for receiving the system addresses and the data; and an address RAM 106, coupled to the memory controller, that provides look-up addresses that correspond to system addresses. The memory controller can provide the look-up addresses to the address system and writes data into locations in the data portion selected by the look-up addresses.
In another aspect, the data portion can store status information.
In another aspect, the data portion stores sector ID information.
In another aspect, the data processor can read data from the data portion according to system addresses, the memory controller can obtain data portion addresses from the address RAM corresponding to system addresses and provides the data portion addresses to the address system to identify locations in the data portion for reading, and the data portion can provide data to the processor from locations corresponding to the data portion addresses.
In another aspect, the data portion can have data blocks and the addresses can each have a data block portion and a location in data block portion.
In another aspect, during a read, the nonvolatile memory can receive a selection address that is a combination 116 of the location in data block from the system address and the data block portion from the RAM address.
Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.
Some of the above embodiments, as applicable, may be implemented using a variety of different information processing systems. For example, although
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
The following are various embodiments of the present invention.
