Patent Application
20140136823
Many computer users seek to maximize performance in a computer system. A familiar example is a so-called gamer who seeks to operate a system at high or extreme performance levels to enable a better gaming experience. To this end, some users will cause system components such as a processor and memory to be overclocked, that is, to operate at higher performance levels (such as frequency) than that specified by the manufacturer. Although this can lead to performance enhancement, such operation also reduces lifetime of the system, and can lead to catastrophic failure, particularly without the presence of an enhanced computer system design, including enhanced cooling system, voltage and current delivery mechanisms and so forth.
To reach these higher processing levels, typically an advanced user accesses certain settings within a pre-boot or basic input/output system (BIOS) environment, which requires the user to exit normal system operation, shut down and restart the system to enable entry into BIOS. This sequence can be time consuming and is undesirable for at least certain users, as it requires a good deal of knowledge to even determine the location of this control. Thus to make a performance change, a user exits an operating system, enters BIOS set up, makes a change to one or more settings in BIOS, reboots into an operating system (OS), and finally reloads the application/game desired. This process is slow and not user friendly, leading to an unsatisfactory user experience.
In various embodiments, during normal system operation, namely outside of a pre-boot environment and within an operating system (OS) environment, a user can dynamically control various performance tuning knobs or configuration settings in real time. In this way, performance optimizations can be realized in real time within the OS environment such that changes take effect immediately, providing instant results. As such, the need for a user to access a pre-boot environment to effect changes to configuration settings (e.g., associated with processor performance) can be avoided. By managing overclocking in a dynamic fashion, risks such as potential system failures associated with overclocking can be reduced by transitioning into and out of out of specification modes in real-time on demand. In addition to user-based control of such settings, embodiments may further provide for automated updates to one or more configuration settings, e.g., via an OS or application executing under the OS, responsive to a type of application or other code being executed by the user.
Embodiments may be implemented in many different platforms, which can include a processor such as a multicore, multi-domain processor. As used herein the term “domain” is used to mean a collection of hardware and/or logic that operates at the same voltage and frequency point. As an example, a multicore processor can further include other non-core processing engines such as fixed function units, graphics engines, and so forth. Other computing elements can include digital signal processors, processor communications interconnects (buses, rings, etc.), and network processors. A processor can include multiple independent domains, including a first domain associated with the cores (referred to herein as a core or central processing unit (CPU) domain) and a second domain associated with a graphics engine (referred to herein as a graphics or a graphics processing unit (GPU) domain). Although many implementations of a multi-domain processor can be formed on a single semiconductor die, other implementations can be realized by a multi-chip package in which different domains can be present on different semiconductor die of a single package or multiple packages.
Although the scope of the present invention is not limited in this regard, in various embodiments configuration settings associated with processor performance that can be controlled include a core clock frequency, also referred to herein as a core clock ratio, in that an example processor may be controlled to operate at a frequency corresponding to a ratio between a core clock frequency and a base clock frequency (referred to herein as BCLK). Other configuration settings may include control of a graphics engine frequency, e.g., according to a graphics engine clock ratio, voltage for core and/or graphics engine, along with other power/thermal performance values. Collectively, control of one or more of these configuration settings to increase performance is referred to herein as overclocking.
In general overclocking theory seeks to maximize frequency and minimize voltage/current while removing as much heat as possible such that stability requirements are met. To enable extra overclocking, a higher air flow and/or more efficient heat sink and/or aggressive cooling (such as via liquid cooling) may be provided to the processor and voltage regulators. In this way the allowable power and current limits of the processor can be increased.
Since modifications to these configuration settings can adversely affect system lifetime and can even lead to catastrophic failures, embodiments may also provide a mechanism to enable a system manufacturer to prevent such user-controlled dynamic configuration changes, referred to herein as overclock locking, such that when enabled, a user is prevented from dynamically modifying these performance tunings.
Note that embodiments that perform overclocking as described herein may be independent of OS-based power management. For example, according to an OS-based mechanism, namely the Advanced Configuration and Platform Interface (ACPI) standard (e.g., Rev. 3.0b, published Oct. 10, 2006), a processor can operate at various performance states or levels, namely from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that can be requested by an OS. In addition to this P1 state, the OS can further request a higher performance state, namely a P0 state. This P0 state may thus be an opportunistic state in which, when power and/or thermal budget is available, processor hardware can configure the processor or at least portions thereof to operate at a higher than guaranteed frequency, also referred to as a turbo mode. In many implementations a processor can include multiple so-called bin frequencies above this P1 frequency. By enabling user controlled overclocking as described herein, embodiments enable turbo mode operation at higher than specified maximum operating frequencies. In addition, according to ACPI, a processor can operate at various power states or levels. With regard to power states, ACPI specifies different power consumption states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-C6 states). When all cores of a multicore processor are in a core low power state, the processor can be placed in a package low power state, such as a package C6 low power state.
Embodiments may provide a communication interface between the processor and a device driver and application layers of the operating system. This interface allows users or authorized applications to effect changes to standard or default power/performance algorithms used by the processor. In one embodiment a power control unit (PCU) of a processor executes microcode stored in the processor. This microcode contains instructions that govern the power and performance modes of the system. Under normal circumstances the PCU operates autonomously with predefined tuning parameters. Via a communications mechanism in accordance with an embodiment of the present invention, user or application defined parameters regarding various processor performance can be dynamically updated. Specifically, structures including memory mapped input/output (MMIO) mail boxes and machine specific registers (MSR's) are exposed to an OS driver and then to application layers. A software implementation such as a utility can be given access to the structures to make adjustments to configuration settings in processor structures. Once these structures are updated, the PCU recognizes the change and the performance characteristics are changed in real-time (with no reboot).
Referring now to
As another example a maximum current (Icc max) can be changed to increase maximum Icc for both core and graphics units when in turbo mode, such that a phase locked loop (PLL) overvoltage increases an internal processor voltage regulator to allow additional frequency scaling on a series of PLLs that manage frequency within the processor.
In an example embodiment controllable multipliers may be provided for core frequency with unlocked turbo limits to provide unlocked core ratios up to 63 in 100 megahertz (MHz) increments, and also provides a programmable voltage offset (which may provide an increased voltage of between approximately 1.0 and 1.52 volts). Graphics frequency with unlocked graphics turbo limits provides unlocked graphics ratios up to 60 in 50 MHz increments, and a programmable voltage offset. Also, in some embodiments an update to increase the BCLK via this GUI can change several of these subsystem frequencies at once. Select voltages can be adapted to support frequency on each interface impacted. Although shown with these particular configuration settings in the illustration of
For example, the above described configuration settings are for a processor package. Other system parameters can similarly be dynamically controlled by a user during runtime. Still further, via a GUI such as GUI 10, additional information can be provided to a user. For example, various monitoring of processor conditions such as temperature, utilization, frequency, thermal design power (TDP), among many other parameters can be displayed in real time to a user, e.g., via a graphical presentation of the information. A tuning utility, in addition to providing an interface for receiving tuning parameters, can also perform stress tests by applying application/workload stress on the processor at an updated frequency after a change is effected. Also, a mechanism can be provided to enable a user to apply changes and save them into a profile, such that multiple profiles can be stored, e.g., in a non-volatile storage of a system. This profile storage can enable the user to recall these profiles, e.g., upon a different execution of an application such as a particular gaming application for which the user has set a group of configuration settings.
As described above, dynamic runtime changes to processor performance settings can be effected by a user or automated software/firmware. Certain manufacturers, such as those selling high-end stable systems may not want their platforms to be able to change performance settings outside of a pre-boot environment. As such, embodiments may further provide a mechanism to prevent a real-time user-controlled change to performance settings. In one embodiment, a configuration parameter, e.g., a bit of a configuration register such as a MSR within a processor can be set to prevent dynamic user performance setting changes. Generally, such settings are referred to herein as overclocking settings and as such, this indicator may be referred to as an overclocking lock indicator. In one embodiment, this indicator may correspond to a field such as a one bit field of an MSR such as a power management MSR, e.g., located within a PCU of the processor. Understand the scope of the present invention is not limited in this regard, and this overclocking lock indicator can be located in other registers or storages of a processor. Also, by providing an overclocking lock indicator, malicious activity such as malicious code can be avoided, to protect against reverse engineering a tuning utility to determine what registers are changing.
In operation, dynamic changing of configuration settings are prevented, in that processor microcode or other such logic that receives a request for a user-controlled dynamic configuration change will disallow the change to be effected responsive to this set overclocking indicator. Of course the scope of the present invention is not limited in this aspect and other mechanisms to prevent a user from dynamic overclocking of a platform can be realized. For example an overclocking lock indicator may be associated with each register or other storage that stores processor performance configuration settings instead of a single global lock bit to lock all overlocking parameters collectively.
Referring now to
Still referring to
If instead the manufacturer does not seek to lock out dynamic overclocking control, control passes from diamond 140 to block 170 directly. As such, the platform is enabled for user controlled dynamic configuration setting updates as described herein. Although shown at this high level in the embodiment of
As described above, embodiments may also provide for an automatic dynamic update to the configuration settings based on actual system operation. For example, in some embodiments, an OS can monitor a type of workload, e.g., application being executed, and trigger requests to update one or more configuration settings. As an example, the OS can cause a core clock frequency to be increased when a first application (e.g., a game is executing and cause the core clock frequency to be decreased when a second application (e.g., a web browser) is executing.
Referring now to
In the embodiment shown in
Regardless of the manner in which the interface is displayed, method 200 continues to block 220 where one or more user requests to update a configuration setting of the processor can be received along with associated update values. For purposes of discussion assume that a single configuration setting, namely a core clock ratio is requested to be updated. Such request can be effected via a user selecting this setting, e.g., via a click and further input of an updated value for the setting, e.g., by click of a mouse to increase this value via a bar, or via input of a number by keyboard or in any other manner.
Still referring to
Still referring to
Otherwise, if it is determined at diamond 240 that user control of the configuration settings is not allowed, control passes instead to block 260 where no change is effected and instead an indication may be provided that such updates are not allowed. As an example, a display indication can be made to the user to indicate that these updated values are not allowed. Although described with this implementation in the embodiment of
In some embodiments, performance monitoring and tuning of a platform can be realized using smartphones, tablets or other second systems, e.g., utilizing a wireless connection. This interface enables a tuning utility executing on the target platform to control various parameters, monitor system status, e.g., processor utilization, frequencies, temperature, and system statistics even when a user is immersed in a full screen activity, and to communicate the information for display on a second system.
Referring now to
Thus in the embodiment shown in
Referring now to
In various embodiments, power control unit 355 may include a power sharing logic 359, which may be a logic to control of one or more domains of the processor to be overlocked to enable greater performance than available according to specified maximum performance level. In the embodiment of
With further reference to
Referring now to
Note that while only shown with three domains, understand the scope of the present invention is not limited in this regard and additional domains can be present in other embodiments. For example, multiple core domains may be present each including at least one core.
In general, each core 410 may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) 4400-440n. In various embodiments, LLC 440 may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect 430 thus couples the cores together, and provides interconnection between the cores, graphics domain 420 and system agent circuitry 450.
In the embodiment of
To enable communication of at least certain of the user updates, a mailbox interface 456 can be present. In general, interface 456 can include a storage 457. This storage can store user inputs regarding at least some of the updated values and provide an interface for handshake-based communications between the PCU and other domains. In one embodiment, PCU 455 can receive updates to the graphics engine configuration settings via this mailbox interface. While described with this particular protocol in the embodiment of
As further seen in
Referring to
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 1100, as illustrated in
As depicted, core 1101 includes two hardware threads 1101a and 1101b, which may also be referred to as hardware thread slots 1101a and 1101b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 1100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 1101a, a second thread is associated with architecture state registers 1101b, a third thread may be associated with architecture state registers 1102a, and a fourth thread may be associated with architecture state registers 1102b. Here, each of the architecture state registers (1101a, 1101b, 1102a, and 1102b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 1101a are replicated in architecture state registers 1101b, so individual architecture states/contexts are capable of being stored for logical processor 1101a and logical processor 1101b. In core 1101, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 1130 may also be replicated for threads 1101a and 1101b. Some resources, such as re-order buffers in reorder/retirement unit 1135, ILTB 1120, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 1115, execution unit(s) 1140, and portions of out-of-order unit 1135 are potentially fully shared.
Processor 1100 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In
Core 1101 further includes decode module 1125 coupled to fetch unit 1120 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1101a, 1101b, respectively. Usually core 1101 is associated with a first ISA, which defines/specifies instructions executable on processor 1100. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 1125 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, decoders 1125, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 1125, the architecture or core 1101 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions.
In one example, allocator and renamer block 1130 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 1101a and 1101b are potentially capable of out-of-order execution, where allocator and renamer block 1130 also reserves other resources, such as reorder buffers to track instruction results. Unit 1130 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 1100. Reorder/retirement unit 1135 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
Scheduler and execution unit(s) block 1140, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
Lower level data cache and data translation buffer (D-TLB) 1150 are coupled to execution unit(s) 1140. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.
Here, cores 1101 and 1102 share access to higher-level or further-out cache 1110, which is to cache recently fetched elements. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache 1110 is a last-level data cache—last cache in the memory hierarchy on processor 1100—such as a second or third level data cache. However, higher level cache 1110 is not so limited, as it may be associated with or includes an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder 1125 to store recently decoded traces.
In the depicted configuration, processor 1100 also includes bus interface module 1105 and a power controller 1160, which may perform power sharing control in accordance with an embodiment of the present invention. Historically, controller 1170 has been included in a computing system external to processor 1100. In this scenario, bus interface 1105 is to communicate with devices external to processor 1100, such as system memory 1175, a chipset (often including a memory controller hub to connect to memory 1175 and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus 1105 may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.
Memory 1175 may be dedicated to processor 1100 or shared with other devices in a system. Common examples of types of memory 1175 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 1180 may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.
Note however, that in the depicted embodiment, the controller 1170 is illustrated as part of processor 1100. Recently, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor 1100. For example in one embodiment, memory controller hub 1170 is on the same package and/or die with processor 1100. Here, a portion of the core (an on-core portion) includes one or more controller(s) 1170 for interfacing with other devices such as memory 1175 or a graphics device 1180. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, bus interface 1105 includes a ring interconnect with a memory controller for interfacing with memory 1175 and a graphics controller for interfacing with graphics processor 1180. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory 1175, graphics processor 1180, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
Embodiments may be implemented in many different system types. Referring now to
Still referring to
Furthermore, chipset 590 includes an interface 592 to couple chipset 590 with a high performance graphics engine 538, by a P-P interconnect 539. In turn, chipset 590 may be coupled to a first bus 516 via an interface 596. As shown in
Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
