This invention relates generally to electronic imaging systems and, more particularly, to starting and stopping critical systems clocks without creating glitches or spurious pulses.
A series of logic-level pulses can typically be created by performing a logical AND of a continuously running pulse train with a positive logic enable signal. To avoid shortened pulses or glitches at turn-on or turn-off, the enable signal should transition from low to high and high to low when the pulse train is low.
If the phase of the continuously running pulse train is varied, the phase of the enable signal must be varied accordingly. However, the enable signal is typically generated by logic running from a non-adjustable system clock of fixed phase. Consequently, a mechanism is needed for varying the phase of the enable signal so that shortened pulses or glitches are not created.
The present invention is directed to providing a mechanism for varying the phase of the enable signal. Briefly summarized, according to one aspect of the present invention, the invention includes a system for generating a gated periodic waveform, the system includes (a) a generator for generating a periodic waveform of adjustable phase; (b) a device for providing a delayed enable signal based on the phase of the periodic waveform so that the gated periodic waveform can be started and stopped without creating undesirable changes in the gated periodic waveform; and (c) a logic element for generating a gated periodic waveform based on the delayed enable signal and the periodic waveform of adjustable phase.
These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.
In
The delay path from signal “GATE—16” uses AND gate 100 to allow the system enable to pass to flip-flop 110. The clock for flip-flop 110 is the rising edge of “CORE_CLK—0”. This delays the system enable by a full clock period and correspondingly delays the enabling and disabling of the selected pulse train at AND gate 90. By performing similar analysis of the delay paths for “GATE—32”, “GATE—48”, and “GATE—56” it is observed that the enabling and disabling at AND gate 90 is delayed by 1.25, 1.5 and 1.75 clock periods, respectively. It is noted that the flip-flops associated with these gates function substantially similar to flip-flops 80 and 110 to create the delays and will not be discussed in detail herein. It is noted that two flip-flops are in each path to create additional delay as those skilled in the art will readily recognize.
The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.
Number | Name | Date | Kind |
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5574753 | Vartti et al. | Nov 1996 | A |
5627795 | Nitta | May 1997 | A |
5652536 | Nookala et al. | Jul 1997 | A |
5808486 | Smiley | Sep 1998 | A |
Number | Date | Country |
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1 077 529 | Feb 2001 | EP |
Number | Date | Country | |
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20040217796 A1 | Nov 2004 | US |