Patent Application
20240104043
The present application generally relates to the field of computing devices with input-output (IO) ports.
Computing devices such as laptops and desktop computers typically have one or more input-output (IO) ports which allow the computing device to connect to external components to send and receive data, or provide or receive power. Examples of such external components include monitors, keyboards, mouse/pointing devices, portable storage devices, hubs, Bluetooth adapters, Direct Current (DC) chargers (power adapters) and batteries. Typically, a user plugs in a cable to a port to connect the external component. Various types of ports include Universal Serial Bus (USB), Thunderbolt (TBT), DisplayPort (DP) and High-Definition Multimedia Interface (HDMI). However, even for a particular model of a computing device of a manufacturer, different types of ports are often provided based on factors such as the intended use, the price point and customer preferences. However, various challenges are presented in accommodating the various types of ports.
The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.
As mentioned at the outset, various challenges are presented in accommodating various types of IO ports in a laptop, desktop or other computing device, also referred to as a client platform. For example, the internal components typically have to be customized according to the types of ports. This results in increased complexity and expense for the manufacturer.
A first issue is that a client platform System-on-Chip (SoC) supports a wide range of TDP (thermal design power), e.g., 15-45 W, enabling various consumer segments that require varied feature sets and system sizes. For example, the OEM/ODM (Original Equipment Manufacturer/Original Design Manufacturer) of a laptop typically must design multiple PCB (printed circuit boards) for the same SoC (System on a Chip) package according to multiple different IO (input/output) port requirements based on factors such as the target market segment. Example of such IO ports include USB 3.0, TBT, DP, HDMI, DC barrel plug or Type-C charging port (EPR/SPR). Currently, the OEM/ODM designs separate motherboards or daughterboards for different system feature requirements which need separate efforts in terms of electrical, mechanical and development concerns. This can directly impact the overall design cost of the system and the time to market.
One potential solution involves a hub/dongle which connects by cable to the IO port of interest, e.g., a USB-C-HDMI dongle. However, this result in additional cost for the customer and clutter near the computing device. This approach also requires a dedicated USB-C Port controller, PD (Power Delivery) circuits and additional protocol convertors/repeaters on the host system to meet the electrical specification at the IO connector (e.g., DP/HDMI). This increases the cost of the computing device and can impact performance and power efficiency.
A second issue is a desire for the consolidation of AC (alternating current) adapter type (e.g., barrel, flat, USB Type-C, etc.) and data port. USB Type-C is one choice for delivery of both power and data as it accommodates multiple protocol such as USB, TBT, DP and HDMI. There are some use cases which utilize both power delivery (e.g., provider/power source) data path simultaneously. One example is an external USB-C SSD (solid state drive) which transfers data to/from the computing device as well as receiving power from the computing device. However, there are many other use cases which do not need both power and data concurrently at all times. For example, when the USB-C port is utilized only for power delivery (e.g., as a consumer/power sink), the user cannot use the data path and, similarly, when the USB-C port is utilized only for data (e.g., for a DisplayPort), the user cannot use the power path. Most of the time, based on the use case, either the power delivery path resources or the data path resources are redundant, resulting in a less than optimal utilization of the available system features.
One potential solution involves increasing the number of USB-C ports. This involves a SoC integrated solution, which increases the cost of the SoC, or a discrete solution, which increases the cost of the platform components. Both solutions significantly impact the overall system form factor, cost, power consumption and thermal solution. For example, each USB Type-C Port requires an approximately 2 mm square silicon area, a count of 25-30 balls in a ball grid array and additional packaging efforts.
Another potential solution involves a docking station which extends the capabilities of a laptop with additional ports, different type of ports and other features. However, this is generally an expensive laptop accessary, and is mainly targeted for non-portable setups.
The techniques herein address the above and other issues.
In one aspect, a module is provided which can be easily and quickly inserted into or removed from a computing device by the user. That is, the module is removable by the user. The module includes a port which is configured for a desired specification, such as USB-A, USB-C, TBT, DP or HDMI. The module can comprise an expansion card such as an M.2 card. M.2 is a specification for internally mounted computer expansion cards and associated connectors. The module further includes circuitry for communicating with a host platform such as a SoC or motherboard, for example.
The host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. Additionally, the user has the flexibility to quickly and easily change out the types of modules.
In another aspect, the modules are fixed within the computing device and not intended to be changed out.
In another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.
These and other features will be apparent in view of the following discussion.
The following acronyms and terms are used:
IO: input-output
DC: Direct Current
USB: Universal Serial Bus
USB-C EPR (Extended Power Range): a standard which allows USB-C to support power delivery up to 240 W, e.g., up to 48 V at 5 A.
USB-C SPR (standard power range): a standard which allows USB-C to support power delivery up to 100 W, e.g., up to 20 V at 5 A.
TBT: Thunderbolt. A brand name of a hardware interface for the connection of external peripherals to a computer. It combines Peripheral Component Interconnect Express (PCIe) and DisplayPort (DP) into two serial signals, and provides DC power, all in one cable. Up to six peripherals may be supported by one connector. Thunderbolt 1 and 2 use the same connector as Mini DisplayPort (MDP), and Thunderbolt 3 and 4 reuse the USB-C connector from USB. Thunderbolt 3 and 4 can transfer data at high speeds than USB-C. For example, Thunderbolt 3 and 4 can transfer data at up to 40 Gbps which is twice as fast as the 20 Gbps maximum throughput speed of the fastest USB-C ports.
DP: DisplayPort. A digital display interface used to connect a video source to a display device such as a computer monitor. It can also carry audio, USB, and other forms of data.
HDMI: High-Definition Multimedia Interface. A proprietary audio/video interface for transmitting uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controller, to a compatible computer monitor, video projector, digital television, or digital audio device. HDMI is a digital replacement for analog video standards.
PCIe: Peripheral Component Interconnect Express. A high-speed serial computer expansion bus standard. It is the common motherboard interface for personal computers' graphics cards, hard disk drive host adapters, Solid-state drives (SSDs), Wi-Fi and Ethernet hardware connections.
MDP: Mini DisplayPort (MDP). A miniaturized version of the DisplayPort audio-visual digital interface.
OEM/ODM (Original Equipment Manufacturing/Original Design Manufacturing)
TDP: Thermal Design Power.
PCB: Printed Circuit Board.
GPIO: General-purpose input-output. An uncommitted digital signal pin on an integrated circuit or electronic circuit board which may be used as an input or output, or both, and is controllable by software.
SoC: System on a Chip. An integrated circuit that integrates all or most components of a computer or other electronic system. These components can include, e.g., a central processing unit (CPU), a graphics processing unit (GPU), memory interfaces, on-chip input/output devices, input/output interfaces, and secondary storage interfaces.
VBUS: Virtual Bus. A power path between a host and a device which carries a nominal 5 V supply.
TCP: USB Type-C Port.
PPS: Programmable Power Supply. A standard that refers to an advanced charging technology for USB-C devices. It can modify in real time the voltage and current by feeding maximum power based on a device's charging status.
Motherboard: The main printed circuit board (PCB) in general-purpose computers and other expandable systems. It holds and allows communication between many of the important electronic components of a system, such as the central processing unit (CPU) and memory, and provides connectors for other peripherals. Unlike a backplane, a motherboard usually contains significant sub-systems, such as the central processor, the chipset's input/output and memory controllers, interface connectors, and other components integrated for general use.
The PCB has expansion capabilities such that components which can be attached to a motherboard include peripherals, interface cards, and daughterboards: sound cards, video cards, network cards, host bus adapters, TV tuner cards, IEEE 1394 cards; and a variety of other custom components.
Daughterboard: An expansion card that attaches to a system directly. Daughterboards often have plugs, sockets, pins or other attachments for other boards. Daughterboards often have only internal connections within a computer or other electronic devices, and usually access the motherboard directly rather than through a computer bus. Such boards can be used to improve various memory capacities of a computer, enable the computer to connect to certain kinds of networks that it previous could not connect to, or to allow for users to customize their computers for various purposes such as gaming.
TCSS SerDes: Type-C Subsystem Serializer/Deserializer. A SerDes is an integrated circuit (IC or chip) transceiver that converts parallel data to serial data and serial data to parallel data. The SerDes has a transmitter section which is a serial-to-parallel converter, and a receiver section which is a parallel-to-serial converter.
PCH: Platform Controller Hub.
SMBus: System Management Bus is a two-wire interface through which various system component chips can communicate with each other and with the rest of the system. It is based on the principles of operation of I2C.
I2C: Inter-Integrated Circuit. A synchronous, multi-controller/multi-target, packet switched, single-ended, serial communication bus used for attaching lower-speed peripheral ICs to processors and microcontrollers for short-distance, intra-board communication.
EEPROM: Electrically Erasable Programmable Read-Only Memory.
MFD: Multi-function Display. This can be a small-screen surrounded by multiple soft keys that can be used to display information to the user in various configurable ways.
The PCH includes a CPU 130, memory 140, and an IO area 150 which includes four modules 151-154 with associated connectors 161-164, respectively, for communicating with the CPU via a TCSS SerDes path 170. The host platform further includes a fan 180 and a battery 190. Although four modules are depicted, this is an example only, as one or more modules can be provided. Each module can include one or more IO ports. The ports can be of various types including USB, TBT, DP and HDMI. Each port can be a different type, or multiple ports can be of the same type. For example, multiple USB-C ports can be provided due to the widespread use of these ports.
The memory 140 can store instructions which are to be executed by the CPU 130 or other processor to perform the functions described herein.
The computing system consolidates multiple IO protocols in the client silicon over a Type-C Subsystem (TCSS) Serializer/Deserializer instead of designing separate motherboards for different system IO port requirements. The motherboard can be standardized, thereby reducing development costs including design, validation and debugging. The TBT/USB4 lanes from the SoC can be used to provide a data link for the different IO port requirements, such as TBT, USB-C, USB-A, DP and HDMI. The IO ports in a laptop, for example, can be incorporated into separate modules which can be provided in a standard form factor or an OEM-specific form factor. With different modules, also referred to herein as personality modules, the system personality/feature set can be varied according to the desired requirements. The OEM/customer has the freedom to buy any personality module based on the IO port requirements and to install the module in a plug and play manner. The user can pay for modules when needed. The modules can further be used across multiple generations of the computing device.
The IO port 200 is secured to one edge 310 of the expansion card and the connector 161 is provided on an opposing edge 320. The M.2 expansion card has a key ID=M, in this example. There is one notch which results in a pin count of 59-66 pins. The provided interfaces are PCIe×4, SATA and SMBus.
In one approach, each expansion card is of the same type, even if the ports are of different types, so that the circuitry on the cards can communicate with the host platform in a standardized way.
The USB-C Module 410 is coupled to the host platform via its connector 411 and paths 412. The module 410 can send high speed (HS) data to, or receive HS data from, the host platform via a path 413 which is coupled to a re-timer 414. The HS data can be 40 Gbps per lane for USB-C, for example. The LS data is at a speed lower than HS. A re-timer is a mixed signal analog/digital device that is usually implemented as an integrated circuit (IC) chip. It is protocol-aware and has the ability to fully recover data from a received signal, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. The re-timer eliminates jitter, noise and other imperfections from the signal to provide a more reliable, less error prone transmission. A re-timer includes equalization functions and a clock data recovery (CDR) function to compensate both deterministic and random jitter, and in turn transmit a clean signal downstream. This is particularly important for high speed data transmissions. The re-timer can send HS data to, or receive HS data from, the USB-C port 415.
The module 410 can send low speed (LS) data to, or receive LS data from, the host platform via a path 416 which is coupled to a Power Delivery (PD) controller/EEPROM 417. The PD controller/EEPROM in turn can send LS data to, or receive LS data from, the USB-C port 415. Alternatively, the module 410 can send power from the USB-C port to the host platform via the PD controller/EEPROM 417, path 416, connector 411 and paths 412, or provide power to an external component which is plugged into the USB-C port by receiving power from the host platform via the paths 412, connector 411, path 416 and PD controller/EEPROM 417.
The HDMI module 420 is coupled to the host platform via its connector 421 and paths 422. The module 420 can send HS data to, or receive HS data from, the host platform via a path 423 which is coupled to an HDMI re-driver 424. A re-driver performs signal conditioning through equalization, providing compensation for input channel loss from deterministic jitter such as inter-symbol interference. A re-driver tends to be more suited for video applications and has a lower cost and power consumption than a re-timer. The re-driver can send HS data to, or receive HS data from, the HDMI port 425.
The module 420 can send LS data to, or receive LS data from, the host platform via a path 426 which is coupled to an EEPROM 427. The EEPROM in turn can send LS data to, or receive LS data from, the HDMI port 425. Alternatively, the module 420 can send power from the HDMI port to the host platform via the EEPROM 427, path 426, connector 421 and paths 422, or provide power to an external component which is plugged into the HDMI port by receiving power from the host platform via the paths 422, connector 421, path 426 and EEPROM 427.
The DP/MFD module 430 is coupled to the host platform via its connector 431 and paths 432. The module 430 can send HS data to, or receive HS data from, the host platform via a path 433 which is coupled to the DP/MFD port 435.
The module 430 can send LS data to, or receive LS data from, the host platform via a path 436 which is coupled to an EEPROM 437. The EEPROM in turn can send LS data to, or receive LS data from, the DP/MFD port 435. Alternatively, the module 430 can send power from the DP/MFD port to the host platform via the EEPROM 437, path 436, connector 431 and paths 432, or provide power to an external component which is plugged into the DP/MFD port by receiving power from the host platform via the paths 432, connector 431, path 436 and EEPROM 437.
The USB-C dual port adapter module 440 includes a first USB-C port 448 and a second USB-C port 449.
The module 440 is coupled to the host platform via its connector 441 and paths 442. The module 440 can send HS data to, or receive HS data from, the host platform via a path 443 which is coupled to one of the USB-C ports 448 or 449 via paths 450 and 451, respectively, and a multiplexer 444, which is controlled by a PD controller/EEPROM 447 via a path 445.
The module 440 can send LS data to, or receive LS data from, the host platform via an I2C path 446 which is coupled to the PD controller/EEPROM 447. The PD controller/EEPROM in turn can send LS data to, or receive LS data from, one of the USB-C ports 448 or 449 via paths 452 or 453, respectively. Alternatively, the module 440 can send power from one of the USB-C ports 448 or 449 to the host platform via one of the paths 452 or 453, respectively, the PD controller/EEPROM 447, path 446, connector 441 and paths 442. Or, the module 440 can power to an external component which is plugged into one of the USB-C ports 448 or 449 by receiving power from the host platform via the paths 442, connector 441, path 446, PD controller/EEPROM 447 and one of the paths 452 or 453, respectively.
In the case of module 440, the computing system overcomes a redundancy which occurs when a port used for power delivery is treated independently from a port used for data delivery. This multiplexer-based solution can be controlled by an existing system PD controller. At the time a new external device, such as a power adapter or a DP monitor, is connected to a USB port, the PD controller communicates with the port to identify the type of the device. The PD controller can concurrently enable both a power path for a first port and a data path for a second port. This reduces the size of the silicon logic. The SoC package size is also reduced by 25-30 pins per USB-C Port. The financial cost is also reduced.
In one approach, the TCSS (e.g., TBT/USB4) lanes coming from the SoC can support TBT, USB-4, USB-3, DP and other interfaces. The TCSS SerDes can be configured to support other interface protocols such as HDMI through soft strap changes, e.g., the default configuration set during boot. This provides the opportunity to modularize the IO connectors and support the personality modules inside the chassis as a pluggable form factor module to the laptop IO area 150 (
Based on the system requirements, the personality module can be assembled in the laptop chassis by the OEM or the user. In one approach, an embedded controller (EC) 401a such as in the SoC detects the personality module based on a GPIO interrupt and initiates an Inter-Integrated Circuit (I2C) communication with the EEPROM inside the module, where the EEPROM contains module configuration data such as supported IO device type and power profiles. This configuration data can be used to detect the type of personality module in the system and configure the TCSS SerDes and low speed interfaces (e.g., LSx/Aux/I2C) accordingly.
The SoC and/or embedded controller can be considered to be one or more processors.
In the modules, the connector pinout, or assignment of functions/signals to pins, can be standardized to support the superset features such as TBT, system charging (e.g., EPR and PPS) and module power. Based on the personality module plugged in, the system features can be varied and the setting of system SKUs could be done by the OEMs (e.g., USB-C, TBT, HDMI, DP etc.). A Stock Keeping Unit (SKU) refers to a unique identifier for a particular stock of goods. The personality module could be detachable by the user or could be enclosed inside the chassis by the manufacturer.
The personality module can have only the necessary components for its specific IO requirement (e.g., PD controller, re-timers, connectors, etc.). This will eliminate the same components on the system motherboard and thus optimize the overall solution cost for a given IO port. For example, for an HDMI module, a PD controller is not required for the operations performed.
Moreover, redundant resources can be avoided with the module 440. With the existing PD controller and additional multiplexer on the data path, the user can utilize the available TCP-1 resources fully. As in
The multiplexer can be coupled to the pins of the modules using pinouts such as in
In the example configuration, the SPR power delivery module 600 includes a USB-C port 602 which provides data to a SPR PD controller 604, which is in communication with an EEPROM 606 and a connector 610. The USB-C port is also coupled to a repeater 608. The connector 610 provides the power to a host platform 620 via its connector 622. The power is received at a 20 V battery charger 624, for example, which can charge a battery 626 and provide power to other system components 628.
This example includes a DP module 430a which is similar to the DP module 430 of
As mentioned, each module can generate a module present signal. This is depicted by Module Present_1, Module Present_2, Module Present_3 and Module Present_4 for modules 430a, 420, 710 and 410, respectively. The module present signals are received at an I/O expander 710, which in turn communicates with the EC 401a via an I2C bus 712. A port communication path PORT_0, PORT_1, PORT_2 and PORT_3 is provided to allow communication between the SoC and the modules 430a, 420, 710 and 410, respectively. A two-bit address is further provide for each module, including bits ADDR_0 and ADDR_1 which are pulled high (1) or low (0). For example, ADDR_0=high and ADDR_1=low, ADDR_0=low and ADDR_1=high, ADDR_0=low and ADDR_1=low, and ADDR_0=high and ADDR_1=high, identify modules 430a, 420, 710 and 410, respectively.
The module 410 can communicate with the SoC via the I2C path 446 as in
As mentioned, a standardized module such as M.2 can be used for different port types. However, different pins can have different functions based on the port type. In
C2 depicts the signals for a USB-A module. C3 depicts the IO direction as P, Bi (bidirectional) or O. C4 depicts whether high speed IO (HSIO) is used.
Column 5 depicts the signals for high bit rate (HBR) TBT module or USB-3 module. C6 depicts the IO direction. C7 depicts whether HSIO is used.
Column 8 depicts the signals for an HDMI module. C9 and C11 depict the IO direction. C10 and C12 depict whether HSIO is used.
C13 provides a description.
The power management controller (PMC) is responsible for platform-wide power management. On some Intel processors, it is on the Platform Controller Hub (PCH)
First, an IO module is connected. The process triggers a boot up of the computing device by a power button or a charger connection. Subsequently, the process detects the IO module connectivity and a G3 (mechanical off state) exit is triggered if applicable. Subsequently, the PMC checks the PD controller I2C access with new error handling requirements. Phase 4 of the boot process is then reached. The BIOS then reads the IO module connectivity and writes a port configure override to the PMC. The PMC caches the override value. The BIOS then performs a global reset of the platform and CSE, a Converged Security Engine.
The PMC then resolves the port enable based on strap override information form the BIOS override, after which a phase 3 of the boot process is reached. The PMC resolves port configuration information based on the dynamic over-ride information obtained from BIOS post module detection. The PMC then updates IOM to TYPEC_CONFIGURATION, after which phase 4 is reached again. The BIOS reads the IO module connectivity from the EC, then saves the module IO type to a Hand Off Block (HOB). Subsequently, the BIOS checks to see if the PMC has override information. The PM responses with an acknowledgement (ack) to receive the override. If the ack is not received by the BIOS, it writes a port configure override to the PMC, and the PMC caches the override value. Subsequently, the BIOS performs a global reset to the platform and CSE. If the ack is received by the BIOS, the process ends.
The flow of the process can be further understood in the following detailed example.
The flow proceeds time wise from top to bottom.
There are three types of data flow in a USB connection. In the first type, the downstream-facing port (DFP) sends data downstream. It is typically the port on a host or a hub to which devices connect. A DFP will source VBUS power (the power path between host and device) and can also source VCONN power (to power electronically marked cables). An example of an application that may include a DFP is a docking station.
A second type is the upstream-facing port (UFP), which connects to a host or DFP of a hub, receives the data on a device or hub. These ports usually sink VBUS. An example of an application that may include a UFP is a display monitor.
A third type is a dual-role data (DRD) port which can operate as either a DFP (host) or a UFP (device). The port's power role at attach determines its initial role. A source port takes on the data role of a DFP, while the sink port takes on the data role of a UFP. Using USB PD data role swap can dynamically change the port's data role, however. Example applications include DRD ports include laptops, tablets and smartphones.
Additionally, there are three types of power flow in a USB connection.
In the first type, a sink is a port that when attached consumes power from VBUS and a sink is most often a device. A sink could include USB peripherals such as a USB powered light or fan.
In a second type, a source is a port that when attached provides power over VBUS. Common sources are a host or hub DFP. An example of a source application is a USB Type-C wall charger.
In a third type, a dual-role power (DRP) port can operate as either a sink or source, and may alternate between these two states. When a DRP initially operates as a source, the port takes the data role of a DFP. Alternatively, when a DRP initially operates as a sink, the port takes the data role of a UFP. Using USB PD power role swap can dynamically change the DRP's power role, however. For example, a laptop may include a DRP port that can receive power to charge the laptop's battery, but it can also deliver power to charge external accessories. Additionally, there are two special subclasses of a DRP.
In the first subclass, a sourcing device is capable of supplying power, but not capable of acting as a DFP. One example of this subclass is a USB Type-C and USB PD-compatible monitor that receives data from a laptop's DFP, but also charges the laptop.
In the second subclass, a sinking host is capable of consuming power, but not capable of acting as a UFP. An example could be a hub's DFP that sends data to an accessory while being powered by that accessory.
A downstream facing port (DFP), such as a host computer, exposes pull-up terminations, Rp, on its CC pins (CC1 and CC2). An upstream facing port (UFP), such as a peripheral, exposes pull-down terminations, Rd, on its CC pins. The purpose of Rp and Rd terminations on CC pins is to identify the DFP to UFP connection and the CC pin that will be used for communication. To do this, the DFP monitors both CC pins for a voltage lower than its unterminated voltage.
In the flow of
Although the TBT controller is by default in USB mode, there is no data transfer on the lanes making them redundant. When the PD controller is in sink mode only on port-1, it indicates the MUX to switch the data lanes to port-2. This can happen, e.g., when there is nothing connected on port-2. A device only (UFP) is plugged in port 2, here DP device only is mentioned but the device can be a bus powered USB/TBT device. The explicit contract is established, and respective native/alternate mode is configured, and the data path is established.
In the example flow, for the DFP 1800a, a policy engine (block 1801) is implemented and the CC line is asserted by Rp (block 1802). For the DRP 1800b, a policy engine (block 1803) is implemented and the CC line toggles between Rp and Rd (block 1804). A device policy manager (block 1805) and a TBT control (block 1806) are also implemented.
Subsequently, a port-1 type-C power adapter plug event occurs (block 1807), e.g., when the USB-C power adapter 548 of
For the DFP, the CC lines sees Rd (block 1809) and for the DRP, the CC line sees Rp (block 1810). A connect event is notified to the TBT control and VBUS ramps to vSafe5V (750 mW). The policy engine 1803 waits for a source capability message (block 1811) while the TBT control is configured to USB mode by default (block 1812).
The policy engine 1801 advertises power capabilities to the policy engine 1803 and the policy engine 1803 responds with requests for a power profile. The policy engine 1801 accepts a request and the policy engine 1803 notifies the negotiated power profile to the device policy manager (block 1805). The sink goes to pSnkStdby mode at 2.5 W (block 1813) and the device policy manager 1805 updates the battery controller and turbo boost settings for the negotiated power profile (block 1814). The device policy manager uses SYS_RDY to notify the policy engine 1803 that the system can draw the negotiated power. In response, VBUS ramps to the explicit contracted value.
The policy engine 1801 then sends PS_RDY to the policy engine 1803 to draw the negotiated power. The policy engine 1803 exits the pSnkStdby mode at block 1815. The policy engine 1801 the causes the VBUS current to ramp up to the negotiated power. At block 1816, Port1 is in a power only mode. An in sink mode (block 1817) sends an indication to select data on Port2 to a mux/re-timer (block 1818). The process of block 1814 can follow. The processing of the policy engine 1801, policy engine 1803 and TBT control 1806 continues at steps A, B and C, respectively in
Subsequently, the policy engine 1803 communicates a discover identity message to the policy engine 1801, which responds by sending a cable capability. The policy engine 1803 then communicates a discover SVIDs message to the policy engine 1801, which responds by sending a list of SVIDs supported. SVID refers to Standard or Vendor ID (SVID), which a unique 16-bit number assigned by the USB Implementers Forum. The SVID is used to identify alternate modes such as DisplayPort over USB-C or HDMI over USB-C. At block 1822, the policy engine 1803 determines whether the DFP supports the SVIDs listed.
The policy engine 1803 then communicates a discover modes message to the policy engine 1801, which responds by sending a list of modes supported. At block 1823, the policy engine evaluates the modes supported by the system. The policy engine then informs the policy engine 1801 to enter a mode. In the response, at block 1824, the policy engine 1801 enters the DP alt mode, for example, e.g., DP over USB-C.
The processing of the policy engine 1801, policy engine 1803 and TBT control 1806 continues at step D, E and F, respectively in
In the closed position as shown, the shutter 2310 includes a portion 2310a which blocks the second port and a portion 2310b which extends in a slot 2320.
In one approach, depicts in
The computing system 2550 may include any combinations of the hardware or logical components referenced herein. The components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or a combination thereof adapted in the computing system 2550, or as components otherwise incorporated within a chassis of a larger system. For one embodiment, at least one processor 2552 may be packaged together with computational logic 2582 and configured to practice aspects of various example embodiments described herein to form a System in Package (SiP) or a System on Chip (SoC).
The system 2550 includes processor circuitry in the form of one or more processors 2552. The processor circuitry 2552 includes circuitry such as, but not limited to one or more processor cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface circuit, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose I/O, memory card controllers such as secure digital/multi-media card (SD/MMC) or similar, interfaces, mobile industry processor interface (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports. In some implementations, the processor circuitry 2552 may include one or more hardware accelerators (e.g., same or similar to acceleration circuitry 2564), which may be microprocessors, programmable processing devices (e.g., FPGA, ASIC, etc.), or the like. The one or more accelerators may include, for example, computer vision and/or deep learning accelerators. In some implementations, the processor circuitry 2552 may include on-chip memory circuitry, which may include any suitable volatile and/or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, Flash memory, solid-state memory, and/or any other type of memory device technology, such as those discussed herein
The processor circuitry 2552 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acorn RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio-frequency integrated circuits (RFIC), one or more microprocessors or controllers, a multi-core processor, a multithreaded processor, an ultra-low voltage processor, an embedded processor, or any other known processing elements, or any suitable combination thereof. The processors (or cores) 2552 may be coupled with or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications or operating systems to run on the platform 2550. The processors (or cores) 2552 is configured to operate application software to provide a specific service to a user of the platform 2550. In some embodiments, the processor(s) 2552 may be a special-purpose processor(s)/controller(s) configured (or configurable) to operate according to the various embodiments herein.
As examples, the processor(s) 2552 may include an Intel® Architecture Core™ based processor such as an i3, an i5, an i7, an i9 based processor; an Intel® microcontroller-based processor such as a Quark™, an Atom™, or other MCU-based processor; Pentium® processor(s), Xeon® processor(s), or another such processor available from Intel® Corporation, Santa Clara, California. However, any number other processors may be used, such as one or more of Advanced Micro Devices (AMD) Zen® Architecture such as Ryzen® or EPYC® processor(s), Accelerated Processing Units (APUs), MxGPUs, Epyc® processor(s), or the like; A5-A12 and/or S1-S4 processor(s) from Apple® Inc., Snapdragon™ or Centrig™ processor(s) from Qualcomm® Technologies, Inc., Texas Instruments, Inc.® Open Multimedia Applications Platform (OMAP)™ processor(s); a MIPS-based design from MIPS Technologies, Inc. such as MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; an ARM-based design licensed from ARM Holdings, Ltd., such as the ARM Cortex-A, Cortex-R, and Cortex-M family of processors; the ThunderX2® provided by Cavium™, Inc.; or the like. In some implementations, the processor(s) 2552 may be a part of a system on a chip (SoC), System-in-Package (SiP), a multi-chip package (MCP), and/or the like, in which the processor(s) 2552 and other components are formed into a single integrated circuit, or a single package, such as the Edison™ or Galileo™ SoC boards from Intel® Corporation. Other examples of the processor(s) 2552 are mentioned elsewhere in the present disclosure.
The system 2550 may include or be coupled to acceleration circuitry 2564, which may be embodied by one or more AI/ML accelerators, a neural compute stick, neuromorphic hardware, an FPGA, an arrangement of GPUs, one or more SoCs (including programmable SoCs), one or more CPUs, one or more digital signal processors, dedicated ASICs (including programmable ASICs), PLDs such as complex (CPLDs) or high complexity PLDs (HCPLDs), and/or other forms of specialized processors or circuitry designed to accomplish one or more specialized tasks. These tasks may include AI/ML processing (e.g., including training, inferencing, and classification operations), visual data processing, network data processing, object detection, rule analysis, or the like. In FPGA-based implementations, the acceleration circuitry 2564 may comprise logic blocks or logic fabric and other interconnected resources that may be programmed (configured) to perform various functions, such as the procedures, methods, functions, etc. of the various embodiments discussed herein. In such implementations, the acceleration circuitry 2564 may also include memory cells (e.g., EPROM, EEPROM, flash memory, static memory (e.g., SRAM, anti-fuses, etc.) used to store logic blocks, logic fabric, data, etc. in LUTs and the like.
In some implementations, the processor circuitry 2552 and/or acceleration circuitry 2564 may include hardware elements specifically tailored for machine learning and/or artificial intelligence (AI) functionality. In these implementations, the processor circuitry 2552 and/or acceleration circuitry 2564 may be, or may include, an AI engine chip that can run many different kinds of AI instruction sets once loaded with the appropriate weightings and training code. Additionally or alternatively, the processor circuitry 2552 and/or acceleration circuitry 2564 may be, or may include, AI accelerator(s), which may be one or more of the aforementioned hardware accelerators designed for hardware acceleration of AI applications. As examples, these processor(s) or accelerators may be a cluster of artificial intelligence (AI) GPUs, tensor processing units (TPUs) developed by Google® Inc., Real AI Processors (RAPs™) provided by AlphaICs®, Nervana™ Neural Network Processors (NNPs) provided by Intel® Corp., Intel® Movidius™ Myriad™ X Vision Processing Unit (VPU), NVIDIA® PX™ based GPUs, the NM500 chip provided by General Vision®, Hardware 3 provided by Tesla®, Inc., an Epiphany™ based processor provided by Adapteva®, or the like. In some embodiments, the processor circuitry 2552 and/or acceleration circuitry 2564 and/or hardware accelerator circuitry may be implemented as AI accelerating co-processor(s), such as the Hexagon 685 DSP provided by Qualcomm®, the PowerVR 2NX Neural Net Accelerator (NNA) provided by Imagination Technologies Limited®, the Neural Engine core within the Apple® A11 or A12 Bionic SoC, the Neural Processing Unit (NPU) within the HiSilicon Kirin 970 provided by Huawei®, and/or the like. In some hardware-based implementations, individual subsystems of system 2550 may be operated by the respective AI accelerating co-processor(s), AI GPUs, TPUs, or hardware accelerators (e.g., FPGAs, ASICs, DSPs, SoCs, etc.), etc., that are configured with appropriate logic blocks, bit stream(s), etc. to perform their respective functions.
The system 2550 also includes system memory 2554. Any number of memory devices may be used to provide for a given amount of system memory. As examples, the memory 2554 may be, or include, volatile memory such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other desired type of volatile memory device. Additionally or alternatively, the memory 2554 may be, or include, non-volatile memory such as read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable (EEPROM), flash memory, non-volatile RAM, ferroelectric RAM, phase-change memory (PCM), flash memory, and/or any other desired type of non-volatile memory device. Access to the memory 2554 is controlled by a memory controller. The individual memory devices may be of any number of different package types such as single die package (SDP), dual die package (DDP) or quad die package (Q17P). Any number of other memory implementations may be used, such as dual inline memory modules (DIMMs) of different varieties including but not limited to microDIMMs or MiniDIMMs.
Storage circuitry 2558 provides persistent storage of information such as data, applications, operating systems and so forth. In an example, the storage 2558 may be implemented via a solid-state disk drive (SSDD) and/or high-speed electrically erasable memory (commonly referred to as “flash memory”). Other devices that may be used for the storage 2558 include flash memory cards, such as SD cards, microSD cards, XD picture cards, and the like, and USB flash drives. In an example, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, phase change RAM (PRAM), resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a Domain Wall (DW) and Spin Orbit Transfer (SOT) based device, a thyristor based memory device, a hard disk drive (HDD), micro HDD, of a combination thereof, and/or any other memory. The memory circuitry 2554 and/or storage circuitry 2558 may also incorporate three-dimensional (3D) cross-point (XPOINT) memories from Intel® and Micron®.
The memory circuitry 2554 and/or storage circuitry 2558 is/are configured to store computational logic 2583 in the form of software, firmware, microcode, or hardware-level instructions to implement the techniques described herein. The computational logic 2583 may be employed to store working copies and/or permanent copies of programming instructions, or data to create the programming instructions, for the operation of various components of system 2550 (e.g., drivers, libraries, application programming interfaces (APIs), etc.), an operating system of system 2550, one or more applications, and/or for carrying out the embodiments discussed herein. The computational logic 2583 may be stored or loaded into memory circuitry 2554 as instructions 2582, or data to create the instructions 2582, which are then accessed for execution by the processor circuitry 2552 to carry out the functions described herein. The processor circuitry 2552 and/or the acceleration circuitry 2564 accesses the memory circuitry 2554 and/or the storage circuitry 2558 over the interconnect (IX) 2556. The instructions 2582 direct the processor circuitry 2552 to perform a specific sequence or flow of actions, for example, as described with respect to flowchart(s) and block diagram(s) of operations and functionality depicted previously. The various elements may be implemented by assembler instructions supported by processor circuitry 2552 or high-level languages that may be compiled into instructions 2588, or data to create the instructions 2588, to be executed by the processor circuitry 2552. The permanent copy of the programming instructions may be placed into persistent storage devices of storage circuitry 2558 in the factory or in the field through, for example, a distribution medium (not shown), through a communication interface (e.g., from a distribution server (not shown)), over-the-air (OTA), or any combination thereof.
The IX 2556 couples the processor 2552 to communication circuitry 2566 for communications with other devices, such as a remote server (not shown) and the like. The communication circuitry 2566 is a hardware element, or collection of hardware elements, used to communicate over one or more networks 2563 and/or with other devices. In one example, communication circuitry 2566 is, or includes, transceiver circuitry configured to enable wireless communications using any number of frequencies and protocols such as, for example, the Institute of Electrical and Electronics Engineers (IEEE) 802.11 (and/or variants thereof), IEEE 802.23.4, Bluetooth® and/or Bluetooth® low energy (BLE), ZigBee®, LoRaWAN™ (Long Range Wide Area Network), a cellular protocol such as 3GPP LTE and/or Fifth Generation (5G)/New Radio (NR), and/or the like. Additionally or alternatively, communication circuitry 2566 is, or includes, one or more network interface controllers (NICs) to enable wired communication using, for example, an Ethernet connection, Controller Area Network (CAN), Local Interconnect Network (LIN), DeviceNet, ControlNet, Data Highway+, or PROFINET, among many others.
The IX 2556 also couples the processor 2552 to interface circuitry 2570 that is used to connect system 2550 with one or more external devices 2572. The external devices 2572 may include, for example, sensors, actuators, positioning circuitry (e.g., global navigation satellite system (GNSS)/Global Positioning System (GPS) circuitry), client devices, servers, network appliances (e.g., switches, hubs, routers, etc.), integrated photonics devices (e.g., optical neural network (ONN) integrated circuit (IC) and/or the like), and/or other like devices.
In some optional examples, various input/output (I/O) devices may be present within or connected to, the system 2550, which are referred to as input circuitry 2586 and output circuitry 2584. The input circuitry 2586 and output circuitry 2584 include one or more user interfaces designed to enable user interaction with the platform 2550 and/or peripheral component interfaces designed to enable peripheral component interaction with the platform 2550. Input circuitry 2586 may include any physical or virtual means for accepting an input including, inter alia, one or more physical or virtual buttons (e.g., a reset button), a physical keyboard, keypad, mouse, touchpad, touchscreen, microphones, scanner, headset, and/or the like. The output circuitry 2584 may be included to show information or otherwise convey information, such as sensor readings, actuator position(s), or other like information. Data and/or graphics may be displayed on one or more user interface components of the output circuitry 2584. Output circuitry 2584 may include any number and/or combinations of audio or visual display, including, inter alia, one or more simple visual outputs/indicators (e.g., binary status indicators (e.g., light emitting diodes (LEDs)) and multi-character visual outputs, or more complex outputs such as display devices or touchscreens (e.g., Liquid Crystal Displays (LCD), LED displays, quantum dot displays, projectors, etc.), with the output of characters, graphics, multimedia objects, and the like being generated or produced from the operation of the platform 2550. The output circuitry 2584 may also include speakers and/or other audio emitting devices, printer(s), and/or the like. Additionally or alternatively, sensor(s) may be used as the input circuitry 2584 (e.g., an image capture device, motion capture device, or the like) and one or more actuators may be used as the output device circuitry 2584 (e.g., an actuator to provide haptic feedback or the like). Peripheral component interfaces may include, but are not limited to, a non-volatile memory port, a USB port, an audio jack, a power supply interface, etc. In some embodiments, a display or console hardware, in the context of the present system, may be used to provide output and receive input of an edge computing system; to manage components or services of an edge computing system; identify a state of an edge computing component or service; or to conduct any other number of management or administration functions or service use cases.
The components of the system 2550 may communicate over the IX 2556. The IX 2556 may include any number of technologies, including ISA, extended ISA, I2C, SPI, point-to-point interfaces, power management bus (PMBus), PCI, PCIe, PCIx, Intel® UPI, Intel® Accelerator Link, Intel® CXL, CAPI, OpenCAPI, Intel® QPI, UPI, Intel® OPA IX, RapidIO™ system IXs, CCIX, Gen-Z Consortium IXs, a HyperTransport interconnect, NVLink provided by NVIDIA®, a Time-Trigger Protocol (TTP) system, a FlexRay system, PROFIBUS, and/or any number of other IX technologies. The IX 2556 may be a proprietary bus, for example, used in a SoC based system.
The number, capability, and/or capacity of the elements of system 2550 may vary, depending on whether computing system 2550 is used as a stationary computing device (e.g., a server computer in a data center, a workstation, a desktop computer, etc.) or a mobile computing device (e.g., a smartphone, tablet computing device, laptop computer, game console, IoT device, etc.). In various implementations, the computing device system 2550 may comprise one or more components of a data center, a desktop computer, a workstation, a laptop, a smartphone, a tablet, a digital camera, a smart appliance, a smart home hub, a network appliance, and/or any other device/system that processes data.
The techniques described herein can be performed partially or wholly by software or other instructions provided in a machine-readable storage medium (e.g., memory). The software is stored as processor-executable instructions (e.g., instructions to implement any other processes discussed herein). Instructions associated with the flowchart (and/or various embodiments) and executed to implement embodiments of the disclosed subject matter may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of sequences of instructions.
The storage medium can be a tangible machine readable medium such as read only memory (ROM), random access memory (RAM), flash memory devices, floppy and other removable disks, magnetic storage media, optical storage media (e.g., Compact Disk Read-Only Memory (CD ROMS), Digital Versatile Disks (DVDs)), among others.
The storage medium may be included, e.g., in a communication device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communication device, a cellular phone, a notebook computer, a tablet, a game console, a set top box, an embedded system, a TV (television), or a personal desktop computer.
Some non-limiting examples of various embodiments are presented below.
Example 1 includes an apparatus, comprising: an expansion card; a port carried on the expansion card; a connector on the expansion card; and circuitry on the expansion card, wherein the circuitry is to communicate information to a host platform to identify a type of the port.
Example 2 includes the apparatus of Example 1, wherein the type of the IO port comprises Universal Serial Bus (USB) Type A, USB Type C, Thunderbolt, DisplayPort or High-Definition Multimedia Interface (HDMI).
Example 3 includes the apparatus of Example 1 or 2, wherein the circuitry is to communicate a module present signal to the host platform.
Example 4 includes the apparatus of any one of Examples 1 to 3, wherein the circuitry comprises a re-driver in a high-speed data path and an Electrically Erasable Programmable Read-Only Memory in a low speed data path.
Example 5 includes the apparatus of any one of Examples 1 to 4, wherein the circuitry comprises a re-timer in a high-speed data path and an Electrically Erasable Programmable Read-Only Memory in a low speed data path.
Example 6 includes the apparatus of any one of Examples 1 to 5, wherein the expansion card comprises an M.2 expansion card.
Example 7 includes the apparatus of any one of Examples 1 to 6, wherein the IO port is a first IO port on the expansion card, the apparatus further comprises a second IO port on the expansion card, and the circuitry comprises a multiplexer to couple at least one of the first IO port or the second IO port to the connector.
Example 8 includes the apparatus of Example 7, further comprising a servo motor on the expansion card, and a shutter coupled to the servo motor, the shutter is carried on guideways to move to a first position to block access to the second IO port when the first IO port but not the second IO port is coupled to the connector by the multiplexer, and to a second position to allow access to the second IO port when the first IO port and the second IO port are coupled to the connector by the multiplexer.
Example 9 includes the apparatus of any one of Examples 1 to 8, wherein the IO port is a first IO port on the expansion card, the apparatus further comprises a second IO port on the expansion card, and the circuitry comprises a multiplexer to couple the first IO port and the second IO port concurrently to the connector.
Example 10 includes the apparatus of Example 9, wherein the first IO port is to carry data but not power while the second IO port is to carry power but not data.
Example 11 includes the apparatus of any one of Examples 1 to 10, wherein the apparatus is a removable module of a computing device.
Example 12 includes a host platform, comprising: one or more processors; a connector; a serialization/deserialization path to couple the one or more processors to the connector; and low speed data and power paths to couple the one or more processors to the connector, wherein the one or more processors are to receive an identification of a type of input-output (IO) port on a module and to communicate with the module via the connector according to the type of IO port.
Example 13 includes the host platform of Example 12, wherein the one or more processor are to communicate with the module based on an assignment of signals to pins of the module, the assignment is based on the type of the IO port.
Example 14 includes the host platform of Example 12 or 13, wherein the module is among a plurality of modules coupled to the host platform, and for each module of the plurality of modules, the one or more processors are to receive an identification of a type of IO port on the module and to communicate with the module via the connector according to the identification of the type of the IO port.
Example 15 includes the host platform of Example 14, wherein each module of the plurality of modules has a different assignment of signals to pins of the module, and for each module of the plurality of modules, the one or more processors are to communicate with the module via the connector according to the assignment of signals to pins of the module.
Example 16 includes the host platform of any one of Examples 12 to 15, wherein, wherein the IO port is a first IO port on the module, the module further includes a second IO port, and the one or are processors are to concurrently receive power from the first IO port via the connector and transmit data to the second IO port via the connector.
Example 17 includes the host platform of any one of Examples 12 to 16, wherein, the one or more processors are to communicate high speed data to the IO port via the serialization/deserialization path.
Example 18 includes a computing device, comprising: a host platform; and a plurality of modules, wherein: each module of the plurality of modules comprises an expansion card plugged into the host platform, an input-output (IO) port carried on the expansion card and circuitry carried on the expansion card; each IO port is of a different type; and the host platform is to communicate with each IO port according to the type of the IO port.
Example 19 includes the computing device of Example 18, wherein: each expansion card comprises a connector; the connectors of the expansion cards have a common number of pins and a different assignment of signals and functions to pins according to the type of the IO port carried on the expansion card; and for each expansion card, the host platform is to communicate with the IO port via the connector according to the assignment of signals and functions to pins of the connector.
Example 20 includes the computing device of Example 18 or 19, wherein one module of the plurality of modules comprises a first Universal Serial Bus (USB) port and a second USB port, and the host platform is to receive power from the first USB port while transmitting DisplayPort-over-USB-C data via the second USB port.
In the present detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value. Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
For the purposes of the present disclosure, the phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
As used herein, the term “circuitry” may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. As used herein, “computer-implemented method” may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.
The terms “coupled,” “communicatively coupled,” along with derivatives thereof are used herein. The term “coupled” may mean two or more elements are in direct physical or electrical contact with one another, may mean that two or more elements indirectly contact each other but still cooperate or interact with each other, and/or may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact with one another. The term “communicatively coupled” may mean that two or more elements may be in contact with one another by a means of communication including through a wire or other interconnect connection, through a wireless communication channel or link, and/or the like.
Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic “may,” “might,” or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the elements. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional elements.
Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.
While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.
In addition, well-known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.
