Claims
- 1. A decoder comprising:
- a syndrome circuit to receive a 72-tuple y with components in GF(2) to provide a syndrome s in GF(2);
- wherein s=Hy (when y is expressed in column vector form) and H is a 8 by 72 matrix in GF(2) given by ##EQU1## where H.sub.1, i=1, 2, are each 4 by 36 matrices in GF(2) given by ##EQU2##
- 2. The decoder as set forth in claim 1, further comprising:
- a first circuit to provide a signal indicative of whether a first group of four bits of s has weight three, and to provide a signal indicative of whether a second group of four bits of s has weight three, the first and second groups of four bits representing all eight bits of s; and
- a second circuit to provide a signal indicative of whether s has an odd weight.
- 3. The decoder as set forth in claim 2, wherein the first circuit is to provide a signal indicative of whether the first group of four bits of s has weight two, and to provide a signal indicative of whether the second group of four bits of s has weight two.
- 4. The decoder as set forth in claim 2, wherein the first circuit is to provide a signal indicative of whether the first group of four bits of s has a weight of at least one, and to provide a signal indicative of whether the second group of four bits of s has a weight of at least one.
- 5. A decoder comprising:
- a syndrome circuit to receive a 72-tuple y with components in GF(2) to provide a syndrome s in GF(2) where s=Hy (when y is expressed in column vector form) and where H is a 8 by 72 matrix in GF(2);
- wherein the decoder is to provide a signal indicating a single bit error if there is one bit error in the 72-tuple y;
- wherein the decoder is to provide a signal indicating a double error if there are two bit errors in the 72-tuple y;
- wherein the decoder is to provide a signal indicating a nibble error if there is a four-bit error pattern in the 72-tuple y, the four-bit error pattern beginning at �y!.sub.i, where i belongs to the set {4n, 0.ltoreq.n.ltoreq.17};
- wherein the matrix H is such that each row of H has weight 27, and the matrix H has rotational symmetry so that ##EQU3## where H.sub.i, i=1, 2, are each 4 by 36 matrices.
- 6. The decoder as set forth in claim 5, wherein the H.sub.i, i=1, 2, are each given by ##EQU4##
- 7. A decoder comprising:
- a syndrome circuit to receive a 36-tuple y.sub.1 with components in GF(2) and a 36-tuple y.sub.2 with components in GF(2); the syndrome circuit to provide a first partial syndrome s.sub.1 in GF(2), a second partial syndrome s.sub.2 in GF(2), and a syndrome s according to s=s.sub.1 +s.sub.2 in GF(2));
- wherein the syndrome circuit is to provide s.sub.1 according to ##EQU5## in GF(2) (when s.sub.1 and y.sub.1 are expressed in column vector form), where H.sub.i, i=1, 2, are each 4 by 36 matrices in GF(2);
- wherein the syndrome circuit is to provide s.sub.2 according to ##EQU6## (when s.sub.2, p.sub.1, and p.sub.2 are expressed in column vector form), where p.sub.1 and p.sub.2 are each 4-tuples, wherein p.sub.1 is the first four bits of an 8-tuple p and p.sub.2 is the second four bits of the 8-tuple p;
- wherein the syndrome circuit is to provide the 8-tuple p according to ##EQU7## in GF(2) (when y.sub.2 is in column vector form); wherein ##EQU8##
- 8. An encoder to generate a set of 72-tuple codewords, the encoder comprising:
- a generator circuit, wherein for any codeword x belonging to the set of 72-tuple codewords, when in column vector form, satisfies 0=Hx where H is a 8 by 72 matrix in GF(2) given by ##EQU9## where H.sub.i, i=1, 2, are each 4 by 36 matrices in GF(2) given by ##EQU10##
- 9. A set of at least one processor, comprising:
- an encoder to generate a set of 72-tuple codewords, wherein for any codeword x belonging to the set of 72-tuple codewords, when in column vector form, satisfies 0=Hx; and
- a decoder circuit to receive a 72-tuple y with components in GF(2) to provide a syndrome s in GF(2) where s=Hy (when y is expressed in column vector form);
- wherein H is a 8 by 72 matrix in GF(2) given by ##EQU11## where H.sub.i, i=1, 2, are each 4 by 36 matrices in GF(2) given by ##EQU12##
Parent Case Info
This is a continuation of application Ser. No. 08/535,782, filed Sep. 28, 1955, now abandoned, which is a continuation of application Ser. No. 08/176,351, filed Dec. 30, 1993, now abandoned.
US Referenced Citations (4)
Non-Patent Literature Citations (1)
Entry |
Rao, T.R.N. & E. Fujiwara: Error-Control Coding for Computer Systems, 1989, pp. 221-299. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
535782 |
Sep 1995 |
|
Parent |
176351 |
Dec 1993 |
|