Encoding and decoding methods and systems

Abstract

An encoder for use in information processing applications includes an input configured to provide information bits to be encoded and a feedforward convolutional outer code encoder configured to encode the information bits to generate encoded information bits including the information bits and parity bits. The encoder may also include at least one interleaver configured to interleave the encoded information bits to generate an outer codeword. Further, the encoder may include a rate-1 1/(1+D) accumulate code based inner code encoder configured to encode the outer codeword to generate one or more codewords corresponding to the information bits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an exemplary information system 100 that incorporates certain embodiments consistent with the present invention;

FIG. 2 illustrates a block diagram of an exemplary encoder consistent with the present invention;

FIG. 3 illustrates an exemplary configuration of an encoder consistent with the present invention;

FIG. 4 illustrates another exemplary configuration of an encoder consistent with the present invention;

FIG. 5 illustrates another exemplary configuration of an encoder consistent with the present invention;

FIG. 6 illustrates another exemplary configuration of an encoder consistent with the present invention;

FIG. 7 illustrates a block diagram of an exemplary decoder consistent with the present invention; and

FIG. 8 illustrates an exemplary encoding and/or decoding process consistent with the present invention.

Claims

1. An encoder for use in information processing applications, comprising: an input configured to provide information bits to be encoded;a feedforward convolutional outer code encoder configured to encode the information bits to generate encoded information bits including the information bits and parity bits;at least one interleaver configured to interleave the encoded information bits to generate an outer codeword; anda rate-1 1/(1+D) accumulate code based inner code encoder configured to encode the outer codeword to generate one or more codewords corresponding to the information bits.

2. The encoder according to claim 1, further including: an output configured to provide the codewords for modulation and transmission.

3. The encoder according to claim 1, wherein: provided that m and rare integers and the information bits have a length of mr, and i is an integer, the outer code encoder further includesm number of branch encoders represented by gi(D)=1+D for i=0, . . . , m−1 for generating the parity bits with a length of r.

4. The encoder according to claim 3, wherein: the at least one interleaver includes m number of interleavers; andeach branch encoder is respectively coupled to one of the m number of interleavers such that output parity bits from each branch encoder are interleaved by the respectively coupled interleaver.

5. The encoder according to claim 4, wherein a first one of the branch encoders, g0(D), is not coupled to an interleaver to interleave the output from the first branch encoder.

6. The encoder according to claim 3, wherein: the at least one interleaver includes a single interleaver coupled to the inner code encoder; andoutput parity bits from each branch encoder, without being coupled to an additional interleaver, are directly provided to the single interleaver.

7. The encoder according to claim 1, wherein: provided that m and rare integers and the information bits have a length of r, and i is an integer, the outer code encoder further includesm number of branch encoders represented by gi(D)=1+D for i=0, . . . , m−1 for generating the parity bits with a length of mr.

8. The encoder according to claim 7, wherein: the at least one interleaver includes m number of interleavers; andeach branch encoder is respectively coupled through one of the m number of interleavers to the input such that the information bits from the input are interleaved by the one of the m number of interleaver before being encoded by each branch encoder.

9. The encoder according to claim 8, wherein a first one of the branch encoders, g0(D), is not coupled to an interleaver and the first branch encoder receives the information bits from the input un-interleaved.

10. A decoder for use in information processing applications, comprising: an input configured to provide received information to be decoded;an inner decoder configured to decode inner codewords encoded by a rate-1 1/(1+D) accumulate code based inner code encoder to generate a log-likelihood ratio;an outer decoder configured to decode outer codewords encoded by a feedforward convolutional outer codeword to generate extrinsic information;an interleaver configured to interleave the extrinsic information from the outer decoder to the inner decoder; anda de-interleaver configured to de-interleave the log-likelihood ratio from the inner decoder to the outer decoder.

11. The decoder according to claim 10, further including: a decision device configured to determine original message bits based on the extrinsic information and to generate a decoded message after a predetermined number of iterations between the outer decoder and the inner decoder.

12. The decoder according to claim 11, further including: an output configured to provide the decoded message to other applications.

13. A method for encoding information bits in information processing applications, comprising: obtaining the information bits to be encoded;encoding the information bits using a feedforward convolutional outer code encoder to generate encoded information bits including the information bits and parity bits;interleaving the encoded information bits to generate an outer codeword by using at least one interleaver; andencoding the outer codeword by using a rate-1 1/(1+D) accumulate code based inner code encoder to generate one or more codewords corresponding to the information bits.

14. The method according to claim 13, wherein provided that m and r are integers and the information bits have a length of mr, and i is an integer, the encoding the information bits further includes: configuring the outer encoder as m number of branch encoders represented by gi(D)=1+D for i=0, . . . , m−1; andgenerating the parity bits with a length of r by using the m number of branch encoders.

15. The method according to claim 14, further including: coupling an interleaver between each branch encoder and the input such that the information bits from the input are interleaved by the interleaver before being encoded by each branch encoder.

16. The method according to claim 13, wherein provided that m and r are integers and the information bits have a length of r, and i is an integer, the encoding the information bits further includes: configuring the outer encoder as m number of branch encoders represented by gi(D)=1+D for i=0, . . . , m−1; andgenerating the parity bits with a length of mr by using the m number of branch encoders.

17. The method according to claim 16, further including: coupling an interleaver between each branch encoder and the input such that the information bits from the input are interleaved by the interleaver before being encoded by each branch encoder.

18. The method according to claim 13, further including: setting a code rate of a value between ½ and 32/33.