Encoding, decoding and transcoding of audio/video signals using combined parallel and serial processing techniques

Information

  • Patent Application
  • 20070230586
  • Publication Number
    20070230586
  • Date Filed
    April 02, 2007
    17 years ago
  • Date Published
    October 04, 2007
    17 years ago
Abstract
An efficient system and process is utilized to achieve encoding, decoding and transcoding of audio/visual signals, as desired within an audio/visual processing system. The system coordinates the operations of several optimum components to achieve the necessary encoding/decoding/transcoding operations. Most significantly, the coordinated use of both a parallel processor and a bitstream processor, along with most effective interface techniques, are utilized to most efficiently carry out processing operations. The bitstream processor generally carries out those operations which include timing and sequence information, while the parallel processor is available to perform processing steps which are most efficiently carried out in parallel. Such processing steps include the actual compression/decompression of video signals. When combined with a system controller to orchestrate operations, along with memory and related interface components, a system and method to efficiently encode, decode or transcode A/V data is achieved.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects and advantages of the present invention will be seen by studying the following detailed description, in conjunction with the drawings in which:



FIG. 1 illustrates a block diagram of the video processing system;



FIG. 2 illustrates schematically the data flow during encoding operations;



FIG. 3 illustrates schematically the decoding process of the present invention;



FIG. 4 illustrates in block format the transcoding operation of the present invention;



FIG. 5 is a block diagram illustrating the main components making up the system controller module;



FIG. 6 is a block diagram illustrating the structure of the present invention's parallel processors;



FIG. 7 is a schematic drawing illustrating the mapping process of the present invention;



FIG. 8 further illustrates remapping operations;



FIG. 9 is a flow chart showing the sequential processes required for decoding;



FIG. 10 is a flow chart illustrating the parallel video decoding operations;



FIG. 11 is a flow chart generally illustrating the parallel process of encoding information;



FIG. 12 is a flow chart illustrating final steps to encode video data.


Claims
  • 1. An A/V data processing system for efficiently managing A/V data, comprising: a control processor,a memory device operatively coupled to the control processor;an analog input device for receiving analog video streams and producing a corresponding digital data stream to be transferred to the control processor;a digital input device for receiving digital a/v data and appropriately transferring data to the control processor;a bitstream processor coupled to the control processor, the bitstream processor configured to parse received a/v data and provide timing data related the parsed a/v data, the bitstream processor also capable of receiving a processed video signal an appending timing data therefore; anda parallel processor capable of multiple data processing operations in parallel including the processing of analog video streams received from the input device to produce the processed video signal, the parallel processor for further receiving parsed a/v data and produce a processed analog video signal, wherein the control processor coordinates efficiencies by communicating with the bitstream processor and the parallel processor to allow parallel processing of parsed data streams.
  • 2. The A/V data processing system of claim 1 wherein the control processor further comprises: a process bus controller coupled to the bitstream processor;a bus bridge coupled to the process bus controller, the bus bridge further coupled to a system bus controller, a parallel processor bus controller and a peripheral bus controller, the system bus controller configured to accommodate communication via a system interface, the parallel processor bus controller configured to accommodate communication with the parallel processor, and the peripheral bus controller configured to accommodate communication with the analog input device and the digital input device; anda memory controller coupled to the memory device to accommodate communication with the memory device.
  • 3. The system of claim 2 wherein the memory device is a separate component.
  • 4. The system of claim 1 further comprising a management processor coupled to the system controller and the bitstream processor to manage the exchange of information therebetween, including providing timing information for insertion by the bitstream processor.
  • 5. A method for managing and processing audio/visual signals in a processing system, comprising: receiving the audio/visual signals in a first format;determining if encoding processes, decoding processes or transcoding processes are necessary to generate an audio/visual signal in a desired format, andif encoding processes are necessary, receiving the audio/visual signal of the first format which is an analog format, digitizing the audio/visual signal and remapping to a block format before transferring the bock format to a parallel processor for encoding the image in a digital format and passing the digital format to a bitstream processor to insert timing information, thus creating an encoded audio/visual signal capable of storage and further processing;if decoding processes are necessary, transferring the audio/visual signals to the bitstream processor to parse timing information and signal information, and then transferring the parsed timing and signal information to the parallel processor for decoding of images and the production of a decoded audio/visual signal which is capable of being output by an a/v output interface; andif transcoding processes are necessary, receiving the audio/visual signal of the first format and transferring to the bitstream processor for parsing of timing information and signal information and then transferring the parsed timing and signal information to the parallel processor for partial decoding of the signal and subsequent encoding in a second format, and then transferring back to the bitstream processor to complete the encoding into the second format.
Provisional Applications (1)
Number Date Country
60787854 Mar 2006 US