Patent Grant
12113549
This application relates to the field of communication technologies, and in particular, to an encoding method and apparatus.
Bose-Chaudhuri-Hocquenghem codes (BCH codes) are important linear block codes, and are one of few error-correcting codes that can ensure a code distance of a constructed code by using an algebraic structure. At a medium/high code rate, a minimum code distance is, in many cases, an upper limit of a minimum code distance of a known error-correcting code at a current code length and a current code rate. Because a code distance is a key performance indicator of an error-correcting code, the BCH codes are widely used in engineering.
With improvement of a decoding algorithm and a hardware capability, an application scope of the BCH codes in next-generation wireless communication may be increasingly wide. However, a code length and a code rate supported by a current BCH code are limited, and a requirement for flexible scheduling of a code length and a code rate of a short packet in wireless communication may fail to be supported.
This application provides an encoding method and apparatus, to propose a construction and encoding scheme of a BCH code. A code length and a code rate of an obtained BCH code are flexible, to satisfy a requirement of flexible channel encoding in wireless communication.
According to a first aspect, this application provides an encoding method. The method may include: determining a first encoding parameter based on a first BCH code, and performing BCH encoding based on the first encoding parameter, where the first BCH code is a to-be-coded BCH code, the first encoding parameter is a first code or a generator matrix of a first code, the first code has a code length of n and an information bit length of k, n is greater than 0, and k is greater than 0. The foregoing method is used, so that a code length and a code rate of an obtained BCH code are flexible, to satisfy a requirement of flexible channel encoding in wireless communication.
In a possible design, a specific method for determining a first encoding parameter based on a first BCH code may be: determining a generator matrix of the first BCH code; and determining the first encoding parameter based on the generator matrix of the first BCH code and a puncturing sequence, where an element included in the puncturing sequence is a column index in the generator matrix of the first BCH code. In this way, the first encoding parameter can be accurately obtained, so that subsequent encoding can be accurately performed, and implementation complexity is low.
In a possible design, a specific method for determining the first encoding parameter based on the generator matrix of the first BCH code and a puncturing sequence may be: selecting the last k rows of the generator matrix of the first BCH code to obtain a first matrix; and sequentially puncturing, according to the puncturing sequence, locations corresponding to elements in the puncturing sequence in the first matrix to obtain the first encoding parameter, where the first encoding parameter is a matrix including k rows and n columns. In this way, the first encoding parameter can be accurately obtained, subsequent encoding can be accurately performed, and implementation complexity is low.
In a possible design, a code rate k/n of the first code may be less than or equal to a code rate threshold. In this way, an optimal first encoding parameter can be obtained by selecting a puncturing method.
In a possible design, a specific method for determining a first encoding parameter based on a first BCH code may be: determining a generator matrix of the first BCH code; and determining the first encoding parameter based on the generator matrix of the first BCH code and a shortening sequence, where an element included in the shortening sequence is a column index in the generator matrix of the first BCH code. In this way, the first encoding parameter can be accurately obtained, subsequent encoding can be accurately performed, and implementation complexity is low.
In a possible design, a specific method for determining the first encoding parameter based on the generator matrix of the first BCH code and a shortening sequence may be: sequentially setting, according to the shortening sequence, locations corresponding to elements in the shortening sequence to zero in the generator matrix to obtain a second matrix; and performing selection starting from the last row of the second matrix, and skipping a row in which 1 exists at a location corresponding to an element in the shortening sequence until k rows are selected to obtain the first encoding parameter, where the first encoding parameter is a matrix including k rows and n columns. In this way, the first encoding parameter can be accurately obtained, subsequent encoding can be accurately performed, and implementation complexity is low.
In a possible design, a code rate k/n of the first code may be greater than or equal to a code rate threshold. In this way, an optimal first encoding parameter can be obtained by selecting a shortening method.
In a possible design, the code rate threshold may be any one of 1/4, 1/2, 3/4, 1/3, 2/3, 1/8, 3/8, 5/8, 7/8, 1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16, or 15/16.
In a possible design, a specific method for determining a generator matrix of the first BCH code may be: determining the generator matrix of the first BCH code based on a generator polynomial group of the first BCH code, where the generator polynomial group of the first BCH code includes the following polynomials: g1, g2, g3, . . . , and gx, and x is an integer greater than or equal to 1. Polynomial is a well-known term in mathematics. In mathematics, an algebraic expression formed by adding several monomials is called a polynomial, an algebraic expression formed by a product of numbers or letters is called a monomial, and a single number or letter is also called a monomial. Any g herein represents a polynomial. In this way, the generator matrix of the first BCH code can be accurately obtained, so that an accurate first encoding parameter can be subsequently obtained.
In a possible design, a specific method for determining the generator matrix of the first BCH code based on a generator polynomial group of the first BCH code may be: determining the generator matrix of the first BCH code based on a row vector corresponding to each polynomial in the generator polynomial group of the first BCH code and a row vector obtained by performing right shift on the row vector, where a length of a row vector corresponding to each row in the generator matrix of the first BCH code is equal to a mother code length of the first BCH code, and a quantity of rows is equal to the mother code length; the first row is a row vector corresponding to the polynomial g1, and the second row, . . . , and the (k1−k2)th row are row vectors obtained by shifting the row vector corresponding to the first row by one bit to the right, . . . , and k1−k2−1 bits to the right respectively; . . . ; the (N−ki+1)th row is a row vector corresponding to the polynomial gi, and the (N−ki+2)th row, . . . , and the (N−kj)th row are row vectors obtained by shifting the row vector corresponding to the (N−ki+1)th row by one bit to the right, . . . , and ki−kj−1 bits to the right; . . . ; and the (N−kx+1)th row is a row vector corresponding to the polynomial gx, and the (N−kx+2)th row is row vector obtained by shifting the row vector corresponding to the (N−kx+1)th row by one bit, . . . , and kx−1 bits to the right; and k1 is an information bit length corresponding to g1, k2 is an information bit length corresponding to g2, ki is an information bit length corresponding to gi, kj is an information bit length corresponding to gj, kx is an information bit length corresponding to gx, j=i+1, and N is the mother code length. In this way, the generator matrix of the first BCH code can be accurately obtained, and an accurate first encoding parameter can be subsequently obtained.
In a possible design, when the first encoding parameter is the first code, a specific method for determining a first encoding parameter based on a first BCH code may be: determining a target polynomial gi in a generator polynomial group of the first BCH code; determining a second code based on gi, where the second code has a code length of N and an information bit length of ki, N is a mother code length of the first BCH code, and ki is an information bit length corresponding to gi; and determining the first code based on the second code. In this way, the first code can be accurately obtained, and subsequent encoding can be accurately performed, where gi is one of polynomials g1, g2, g3, . . . , and gx included in the generator polynomial group, and x is an integer greater than or equal to 1.
In a possible design, a specific method for determining the first code based on the second code may be: shortening the second code to obtain a third code; when a code rate of the third code is less than k/n, puncturing the third code to obtain the first code; and when the code rate of the third code is greater than k/n, adding redundant bits to the third code to obtain the first code, where an information bit length of the third code is k. In this way, the first code can be flexibly obtained.
In a possible design, a specific method for shortening the second code to obtain a third code may be: shortening the second code by ki−k bits to obtain the third code, where a code length of the third code is N+k−ki. In this way, the third code can be accurately obtained.
In a possible design, ki corresponding to gi is a first information bit length in information bit lengths corresponding to the polynomials included in the polynomial group, and the first information bit length is a maximum value less than N+k−n; and a specific method for puncturing the third code to obtain the first code may be: puncturing the third code to n bits to obtain the first code. In this way, the first code can be accurately obtained when the code rate of the third code is less than k/n.
In a possible design, a specific method for puncturing the third code to n bits to obtain the first code may be: puncturing N+k−ki−n bits of the third code to obtain the first code. In this way, the first code can be accurately obtained, so that subsequent encoding can be accurately performed.
In a possible design, a specific method for puncturing N+k−ki−n bits of the third code may be: when the first BCH code is a non-systematic code, puncturing the first N+k−ki−n bits of the third code; or puncturing the last N+k−ki−n bits of the third code; or puncturing the N+k−ki−n bits of the third code according to a preset puncturing sequence; and when the first BCH code is a systematic code, puncturing the first N+k−ki−n bits in non-systematic bits of the third code; or puncturing the last N+k−ki−n bits in non-systematic bits of the third code; or puncturing the first N+k−ki−n bits in systematic bits of the third code; or puncturing the last N+k−ki−n bits in systematic bits of the third code; puncturing N+k−ki−n bits in non-systematic bits of the third code according to the preset puncturing sequence; or puncturing N+k−ki−n bits in systematic bits of the third code according to the puncturing sequence; or puncturing the N+k−ki−n bits of the third code according to the puncturing sequence. In this way, the third code can be flexibly punctured according to an actual case.
In a possible design, when the first BCH code is an extended BCH eBCH code, extension bits of the eBCH code are punctured, where the extension bits are parity bits of information bits.
In a possible design, ki corresponding to gi is a second information bit length in information bit lengths corresponding to the polynomials included in the polynomial group, and the second information bit length is a minimum value greater than N+k−n; and a specific method for adding redundant bits to the third code to obtain the first code may be: adding the redundant bits to the third code to n bits to obtain the first code. In this way, the first code can be accurately obtained when the code rate of the third code is greater than k/n.
In a possible design, a specific method for adding the redundant bits to the third code to n bits to obtain the first code may be: adding n−N+k+ki redundant bits to the third code to obtain the first code. In this way, the first code can be accurately obtained, and subsequent encoding can be accurately performed.
In a possible design, a specific method for adding n−N−k+ki redundant bits to the third code may be: adding n−N−k+ki parity bits to the third code; adding repeated bits of n−N−k+ki bits of the third code; and adding A parity bits and B repeated bits to the third code, where A+B=n−N−k+ki. In this way, redundant bits can be flexibly added to the third code in different manners.
In a possible design, a specific method for adding n−N−k+ki parity bits to the third code may be: generating a parity check sum for k information bits of the third code to obtain one parity bit; and generating a parity check sum for k−d information bits in the k information bits to obtain one parity bit until the n−N−k+ki parity bits are obtained, where d is 1, 2, . . . , and k−1; or performing simplex encoding on the k information bits of the third code to obtain the n−N−k+ki parity bits. In this way, redundant bits can be flexibly added to the third code in different manners.
In a possible design, when the first BCH code is a non-systematic code, a specific method for adding repeated bits of n−N−k+ki bits of the third code may be: adding repeated bits of the first n−N−k+ki bits of the third code to the third code; adding repeated bits of the last n−N−k+ki bits of the third code to the third code; and adding, to the third code according to a preset sequence, repeated bits of n−N−k+ki bits of the third code that are corresponding to the preset sequence. In this way, redundant bits can be flexibly added to the third code in different manners.
In a possible design, when the first BCH code is a systematic code, a specific method for adding repeated bits of n−N−k+ki bits of the third code may be: adding repeated bits of the first n−N−k+ki systematic bits of the third code to the third code; adding repeated bits of the last n−N−k+ki systematic bits of the third code to the third code; and adding, to the third code according to a preset sequence, repeated bits of n−N−k+ki systematic bits of the third code corresponding to the preset sequence. In this way, redundant bits can be flexibly added to the third code in different manners.
In a possible design, a specific method for adding A parity bis and B repeated bits to the third code may be: adding the B repeated bits after the A parity bis are added to the third code; or adding the A parity bis after the B repeated bits are added to the third code, where in the A parity bits and the B repeated bits that are added to the third code, a bit adjacent to any parity bit is a repeated bit, and an adjacent bit of any repeated bit is a parity bit. In this way, redundant bits can be flexibly added to the third code in different manners.
In a possible design, a specific method for shortening the second code by ki−k bits may be: when the first BCH code is a non-systematic code, shortening the first ki−k bits of the second code; or shortening the last ki−k bits of the second code; or shortening the ki−k bits of the second code according to a preset shortening sequence; and when the first BCH code is a systematic code, shortening the first ki−k bits in systematic bits of the second code; or shortening the last ki−k bits in systematic bits of the second code; or shortening the ki−k bits in systematic bits of the second code according to the shortening sequence. In this way, the second code can be flexibly shortened by using different methods according to an actual case.
According to a second aspect, this application further provides an encoding apparatus. The encoding apparatus has functional modules for implementing the method in the first aspect or each possible design example of the first aspect. Functions may be implemented by using hardware, or may be implemented by using hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the foregoing functions.
In a possible design, a structure of the encoding apparatus includes a memory and a processor, and optionally further includes a transceiver. The transceiver is configured to send and receive data, and is configured to communicate and interact with another device in a communication system. The processor is configured to support the encoding apparatus in performing corresponding functions in the first aspect or each possible design example of the first aspect. The memory is coupled to the processor, and the memory stores program instructions and data that are necessary for the encoding apparatus.
According to a third aspect, embodiments of this application provide a communication system, and the communication system may include the foregoing encoding apparatus and the like.
According to a fourth aspect, embodiments of this application provide a computer-readable storage medium. The computer-readable storage medium stores program instructions. When the program instructions are run on a computer, the computer is enabled to perform any one of the first aspect or the possible designs of the first aspect in embodiments of this application. For example, the computer-readable storage medium may be any usable medium accessible to the computer. By way of example and not limitation, the computer-readable medium may include a non-transient computer-readable medium, a random-access memory (RAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (electrically EPROM, EEPROM), a CD-ROM or another optical disc storage, a magnetic disk storage medium or another magnetic storage device, or any other medium that can be used to carry or store expected program code in a form of instructions or a data structure and can be accessed by the computer.
According to a fifth aspect, embodiments of this application provide a computer program product including computer program code or instructions. When the computer program product runs on a computer, the computer is enabled to implement the method in any one of the first aspect and the possible designs of the first aspect.
According to a sixth aspect, this application further provides a chip. The chip is coupled to a memory, and is configured to read and execute program instructions stored in the memory, to implement the method in any one of the first aspect and the possible designs of the first aspect.
For the second aspect to the sixth aspect and technical effect that can be achieved in the second aspect to the sixth aspect, refer to descriptions of technical effect that can be achieved in any one of the first aspect and the possible solutions of the first aspect. Details are not described herein again.
The following further describes in detail this application with reference to accompanying drawings.
Embodiments of this application provide an encoding method and apparatus, to propose a construction and encoding scheme of a BCH code. A code length and a code rate of an obtained BCH code are flexible, to satisfy a requirement of flexible channel encoding in wireless communication. The method and the apparatus in this application are based on a same technical concept. Because problem-resolving principles of the method and the apparatus are similar, mutual reference may be made to implementations of the apparatus and the method, and repeated parts are not described again.
In the descriptions of this application, terms such as “first” and “second” are only for distinction and description, but cannot be understood as indicating or implying relative importance, or as indicating or implying an order.
To describe the technical solutions in embodiments of this application more clearly, the following describes the encoding method and apparatus according to embodiments of this application in detail with reference to the accompanying drawings.
The encoding method provided in embodiments of this application may be applied to various wireless communication scenarios (including but not limited to massive machine type communication (mMTC), ultra-reliable low latency communication (uRLLC), and the like), and is used to transmit signaling or short data, including uplink, downlink cellular communication, distributed networks of various user centers, or the like.
The network device is a device that has a wireless transceiver function or a chip that can be disposed in the network device. The network device includes but is not limited to a gNB, a radio network controller (RNC), a NodeB (NB), a base station controller (BSC), a base transceiver station (BTS), a home evolved NodeB (for example, a home evolved NodeB, or a home NodeB, HNB), a baseband unit (BBU), an access point (AP) in a wireless fidelity (Wi-Fi) system, a wireless relay node, a wireless backhaul node, and a transmission and reception point (TRP, or transmission point, TP). The network device may alternatively be a network node that constitutes a gNB or a transmission point, for example, a baseband unit (BBU), or a distributed unit (DU).
In some deployments, a gNB may include a central unit (CU) and a DU. The gNB may further include a radio frequency unit (RU). The CU implements a part of functions of the gNB, and the DU implements a part of the functions of the gNB. For example, the CU implements functions of a radio resource control (RRC) layer and a packet data convergence protocol (PDCP) layer. The DU implements functions of a radio link control (RLC) layer, a media access control (MAC) layer, and a physical layer (PHY). Information at the RRC layer eventually becomes information at the PHY layer, or is converted from the information at the PHY layer. Therefore, in the architecture, higher layer signaling such as RRC layer signaling or PHCP layer signaling may also be considered as being sent by the DU or sent by the DU and the RU. It may be understood that the network device may be a CU node, a DU node, or a device including a CU node and a DU node. In addition, the CU may be classified as a network device in an access network RAN, or the CU may be classified as a network device in a core network CN. This is not limited herein.
The terminal device may also be referred to as user equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user apparatus. The terminal device in embodiments of this application may be a mobile phone, a smartphone, a tablet computer (Pad), a computer with a wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical, a wireless terminal in a smart grid, a wireless terminal in transportation safety, or a wireless terminal in a smart city, a wireless terminal in a smart home, a personal digital assistant (PDA), a vehicle-mounted mobile apparatus, and the like. Application scenarios are not limited in embodiments of this application. A terminal device having a wireless transceiver function and a chip that may be disposed in the terminal device are collectively referred to as a terminal device in this application.
In this application, both the network device and the terminal device may serve as a transmitting end or a receiving end to perform the encoding method.
It should be noted that the architecture of the communication system shown in
At present, BCH codes are important linear block codes, and are one of the few error-correcting codes that can ensure a code distance of a constructed code through an algebraic structure. At a medium/high code rate, a minimum code distance is, in many cases, an upper limit of a minimum code distance of a known error-correcting code at a current code length and code rate. Because a code distance is a key performance indicator of an error-correcting code, BCH codes are widely used in engineering. BCH codes have an efficient decoding method. A Berlekamp-Massey (BM) decoding algorithm is an extremely simple and efficient hard decoding algorithm. If an input signal is a log likelihood ratio (LLR) soft value, the BCH code may also obtain performance close to a theoretical limit by using an ordered statistical decoding (or ordered statistical decoding) (OSD) decoding algorithm.
However, an existing BCH code supports only a specific code length and code rate. Specifically, a code length N is obtained by subtracting 1 from an integer power of 2, that is, 2m−1 (BCH code), or an integer power of 2, that is, 2m (extended (e) BCH code). For a code rate, only a specific value is also supported. For example, for an eBCH code with N=16, only a quantity of information bits (information bit length) K=2, 6, 8, 12, or 16 is supported; and for an eBCH code with N=32, only a quantity of information bits K=2, 7, 12, 17, 22, 27, 32, or the like is supported.
With the improvement of a decoding algorithm and a hardware capability, the application scope of BCH codes in next-generation wireless communication standards may be wider. However, a code length and a code rate supported by a current BCH code are limited, and a requirement for flexible scheduling of a code length and a code rate of a short packet in wireless communication fails to be supported. Based on this, this application proposes a construction and encoding scheme of a BCH code. A code length and a code rate of an obtained BCH code are flexible, to satisfy a requirement of flexible channel encoding in wireless communication.
In the following method description, an example in which an execution body is an encoding apparatus is used for description. The encoding apparatus may be the terminal device, the network device, or another device in the communication system shown in
An encoding method provided in embodiments of this application is applicable to the communication system shown in
Step 201: An encoding apparatus determines a first encoding parameter based on a first BCH code, where the first BCH code is a to-be-coded BCH code, the first encoding parameter is a first code or a generator matrix of a first code, the first code has a code length of n and an information bit length of k, n is greater than 0, and k is greater than 0.
The first BCH code may be a conventional BCH code, or may be an eBCH code.
Step 202: The encoding apparatus performs BCH encoding based on the first encoding parameter.
In an optional implementation, when the first encoding parameter is the generator matrix of the first code, that the encoding apparatus determines the first encoding parameter based on the first BCH code may specifically include the following two methods.
Method a1: The encoding apparatus determines a generator matrix of the first BCH code; and determines the first encoding parameter based on the generator matrix of the first BCH code and a puncturing sequence, where an element included in the puncturing sequence is a column index in the generator matrix of the first BCH code.
Method a2: The encoding apparatus determines a generator matrix of the first BCH code; and determines the first encoding parameter based on the generator matrix of the first BCH code and a shortening sequence, where an element included in the shortening sequence is a column index in the generator matrix of the first BCH code.
In the foregoing methods a1 and a2, a specific method for determining, by the encoding apparatus, a generator matrix of the first BCH code may be: The encoding apparatus determines the generator matrix of the first BCH code based on a generator polynomial group of the first BCH code. The generator polynomial group of the first BCH code may include the following polynomials: g1, g2, g3, . . . , and gx, and x is an integer greater than or equal to 1. Polynomial is a well-known term in mathematics. In mathematics, an algebraic expression formed by adding several monomials is called a polynomial, an algebraic expression formed by a product of numbers or letters is called a monomial, and a single number or letter is also called a monomial. Any g herein represents a polynomial.
The BCH code itself has a nesting characteristic, and a generator polynomial of a high code rate BCH code is a factor of a generator polynomial of a low code rate BCH code. Therefore, a group of nested polynomials may be used to represent a group of nested BCH codes. For example, generator polynomial groups g1, g2, g3, . . . , and gx of the first BCH code correspond to a group of BCH codes with code rates of r1=k1/N=1, r2=k2/N r3=k3/N, . . . , and rx=kx/N; and correspond to a group of eBCH codes with code rates of r01=k1/N0=1, r02=k2/N0, r03=k3/N0, . . . , and r0x=kx/N0. r1, . . . , rx and r01, . . . , r0x are code rates, and k1, . . . , kx are information bit lengths. Based on a property of BCH, it may be learned that r1>r2>r3> . . . >rx, k1>k2>k3> . . . >kx, and N=2m−1 is a mother code length of a corresponding BCH code, or N0=2m is a mother code length of a corresponding eBCH code. g1=1 is a generator polynomial corresponding to a BCH code with the highest code rate, and gx is a generator polynomial corresponding to a BCH code with the lowest code rate. If i<j, a BCH code rate corresponding to gi is higher than a BCH code rate corresponding to gj, and gi is a factor of gj. Specifically, two polynomial representation forms may be specified:
For the eBCH code, a code of (N,k) is first coded according to the foregoing steps, and then one codeword bit is added, which is a parity check value of k information bits.
For example, it is assumed that a generator polynomial group of a BCH code with N=15 includes g1=1, g2=x 4+x 3+1, g3=x 8+x 4+x 2+x+1, and g4=x 10+x 9+x 8+x 6+x 5+x 2+1, code rates of original BCH codes are r1=15/15, r2=11/15, r3=7/15, and r4=5/15, code rates of original eBCH codes are r1=15/16, r2=11/16, r3=7/16, r4=5/16, and corresponding information bit lengths are k1=15, k2=11, k3=7, and k4=5.
If a code rate of a target BCH code is 2/3=8/12, a code length is 12, and an information bit length is 8, the original BCH codes shown in the foregoing example are not supported. In this case, the eight information bits may be first padded with three zeros to obtain 11 bits, and then BCH encoding is performed by using a shift register, so that an obtained codeword length is 15. Because it is known that three bits are zeros, the encoding apparatus does not need to send the codeword, and a quantity of actually sent codeword bits is 15−3=12. In addition, a quantity of bits that actually carry information is 11−3=8. In this way, the new BCH code of (12, 8) is supported.
Specifically, a specific method for determining, by the encoding apparatus, the generator matrix of the first BCH code based on a generator polynomial group of the first BCH code may be: determining the generator matrix of the first BCH code based on a row vector corresponding to each polynomial in the generator polynomial group of the first BCH code and a row vector obtained by performing right shift on the row vector, where a length of a row vector corresponding to each row in the generator matrix of the first BCH code is equal to a mother code length of the first BCH code, and a quantity of rows is equal to the mother code length; the first row is a row vector corresponding to the polynomial gi, and the second row, . . . , and the (k1−k2)th row are row vectors obtained by shifting the row vector corresponding to the first row by one bit to the right, . . . , and k1−k2−1 bits to the right respectively; . . . ; the (N−ki+1)th row is a row vector corresponding to the polynomial gi, and the (N−ki+2)th row, . . . , and the (N−kj)th row are row vectors obtained by shifting the row vector corresponding to the (N−ki+1)th row by one bit to the right, . . . , and ki−kj−1 bits to the right; . . . ; and the (N−kx+1)th row is a row vector corresponding to the polynomial gx, and the (N−kx+2)th row is row vector obtained by shifting the row vector corresponding to the (N−kx+1)th row by one bit, . . . , and kx−1 bits to the right; and k1 is an information bit length corresponding to g1, k2 is an information bit length corresponding to g2, ki is an information bit length corresponding to gi, kj is an information bit length corresponding to gj, kx is an information bit length corresponding to gx, j=i+1, and N is the mother code length.
For example, for a generator polynomial group g=x 4+x 3+1, a row vector corresponding to the generator polynomial group is [11001], and a vector obtained after the generator polynomial group is extended to a mother code length N=15 by adding zeros is [110010000000000]. The generator polynomial group is shifted to the right by one bit, denoted as g(1), and a row vector form of g(1) is [011001000000000]. An N-long row vector that is obtained by shifting the generator polynomial group to the right by t bits is denoted as g(t).
If the first BCH code is a conventional BCH code, the scale of a generator matrix GN of the first BCH code may be N×N. If the first BCH code is an eBCH code, the scale of a generator matrix GNo may be (N+1)×(N+1). Two equivalent generator matrices of the eBCH code may be generated by using the following two methods.
Method b1:
where 1 is an all-1 column vector whose height is N, 0 is an all-0 row vector whose width is N, and GN is a nested generator matrix of the BCH code.
Method b2:
where 1 is an all-1 row/column vector whose width/height is N, 0 is an all-0 row/column vector whose width/height is N, and GN−1 is a matrix formed by the first N−1 rows and the first N−1 columns of a generator matrix of the BCH code.
The foregoing example is still used. For example, for a BCH code whose N=15, a generator matrix GN of the BCH code may be:
For an eBCH code with N=16, a generator matrix GNo generated by using the method b1 may be:
For an eBCH code with N=16, a generator matrix GNo generated by using the method 2 may be:
Elements in boldface in the examples of the foregoing matrices respectively correspond to row vectors corresponding to generator polynomials g1, g2, g3, and g4 of the exemplary BCH code.
Specifically, after the generator matrix GN is generated, any (N, k) or any (N0, k) code may be coded. A specific method is: selecting k rows near the bottom of the generator matrix GN or GNo as the generator matrix GN,k or GNo,k of the (N, k) or (N0, k) code. The encoding method is the same as that of existing linear block codes, that is, c=u*GN,k, where u is a vector of k long information bits, and c is a vector of N long codewords bits.
In an optional implementation, in the foregoing method a1, a specific method for determining, by the encoding apparatus, the first encoding parameter based on the generator matrix of the first BCH code and a puncturing sequence may be: selecting, by the encoding apparatus, the last k rows of the generator matrix of the first BCH code to obtain a first matrix; and then sequentially puncturing, by the encoding apparatus according to the puncturing sequence, locations corresponding to elements in the puncturing sequence in the first matrix to obtain the first encoding parameter, where the first encoding parameter is a matrix including k rows and n columns.
Specifically, the encoding apparatus sequentially punctures, according to the puncturing sequence, locations corresponding to elements in the puncturing sequence in the first matrix to obtain the first encoding parameter, that is, punctures bits (or (N0−n) bits) of the first (N−n) columns corresponding to the puncturing sequence, and bits of n columns remain.
For example, the foregoing puncturing process may be shown in the schematic diagram of puncturing described in (a) in
In an optional implementation, in the foregoing method a1, a specific method for determining, by the encoding apparatus, the first encoding parameter based on the generator matrix of the first BCH code and a shortening sequence may be: sequentially setting, by the encoding apparatus according to the shortening sequence, locations corresponding to elements in the shortening sequence to zero to obtain a second matrix; and performing selection starting from the last row of the second matrix, and skipping a row in which 1 exists at a location corresponding to an element in the shortening sequence until k rows are selected to obtain the first encoding parameter, where the first encoding parameter is a matrix including k rows and n columns.
For example, the foregoing shortening process may be shown in the schematic diagram of shortening described in (b) in
Specifically, the foregoing puncturing or shortening process is implemented by using a puncturing sequence or a shortening sequence with a length of N0/2. Because a code with a length of N0 or N needs to store a maximum of a puncturing sequence or a shortening sequence with a length of N0/2 (because if a quantity of punctured or shortened bits is greater than N0/2, a BCH code with a mother code length of N0/2 or N0/2−1 should be directly used). Therefore, to support all BCH codes with a maximum mother code length Nmax, only one puncturing sequence with a length of Nmax needs to be stored, or one shortening sequence with a length of Nmax needs to be stored.
A specific storage manner may be as follows: first, a puncturing sequence or a shortening sequence (a length of Nmin/2) corresponding to a minimum mother code length Nmin is stored, and then a puncturing sequence or a shortening sequence (a length of Nmin) corresponding to a second minimum mother code length 2*Nmin is stored. By analogy, Nmax/4 and Nmax/2 are sequentially stored. In this way, a total length of the puncturing/shortening sequence does not exceed Nmax. For example, storage of a puncturing sequence and a shortening (Shorten) sequence may be shown in
Optionally, when a target code rate is less than or equal to a code rate threshold, the foregoing method a1 may be selected. When the target code rate is greater than or equal to the code rate threshold, the foregoing method a2 may be selected. The target code rate is a code rate k/n of the first code. The code rate threshold (Rthr) may be 1/4, 1/2, 3/4, 1/3, 2/3, 1/8, 3/8, 5/8, 7/8, 1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16, 15/16, or the like.
In another optional implementation, when the first encoding parameter is the first code, a specific method for determining, by the encoding apparatus, a first encoding parameter based on a first BCH code may be: determining, by the encoding apparatus, a target polynomial gi in a generator polynomial group of the first BCH code; determining a second code based on gi, where the second code has a code length of N and an information bit length of ki, N is a mother code length of the first BCH code, and ki is an information bit length corresponding to gi; and determining the first code based on the second code.
Specifically, a specific method for determining, by the encoding apparatus, the first code based on the second code may be: shortening, by the encoding apparatus, the second code to obtain a third code; when a code rate of the third code is less than k/n, puncturing, by the encoding apparatus, the third code to obtain the first code; and when the code rate of the third code is greater than k/n, adding, by the encoding apparatus, redundant bits to the third code to obtain the first code, where an information bit length of the third code is k. In this way, a code distance characteristic of an original BCH code may be retained to a maximum extent in an obtained first code through puncturing and shortening.
In an optional implementation, a specific method for shortening, by the encoding apparatus, the second code to obtain a third code may be: shortening, by the encoding apparatus, the second code by ki−k bits to obtain the third code, where a code length of the third code may be N+k−ki.
For example, a specific method for shortening, by the encoding apparatus, the second code by ki−k bits may be: when the first BCH code is a non-systematic code, shortening, by the encoding apparatus, the first ki−k bits of the second code; or shortening, by the encoding apparatus, the last ki−k bits of the second code; or shortening, by the encoding apparatus, the ki−k bits of the second code according to a preset shortening sequence; and when the first BCH code is a systematic code, shortening, by the encoding apparatus, the first ki−k bits in systematic bits of the second code; or shortening, by the encoding apparatus, the last ki−k bits in systematic bits of the second code; or shortening, by the encoding apparatus, the ki−k bits in systematic bits of the second code according to the shortening sequence.
In an optional implementation, when ki corresponding to gi is a first information bit length in information bit lengths corresponding to the polynomials included in the polynomial group, the code rate of the third code is less than k/n. In this case, a specific method for puncturing, by the encoding apparatus, the third code to obtain the first code may be: puncturing, by the encoding apparatus, the third code to n bits to obtain the first code.
Specifically, a specific method for puncturing, by the encoding apparatus, the third code to n bits to obtain the first code may be: puncturing, by the encoding apparatus, N+k−ki−n bits of the third code to obtain the first code.
Further, a specific method for puncturing, by the encoding apparatus, N+k−ki−n bits of the third code may be: when the first BCH code is a non-systematic code, puncturing, by the encoding apparatus, the first N+k−ki−n bits of the third code; or puncturing, by the encoding apparatus, the last N+k−ki−n bits of the third code; or puncturing, by the encoding apparatus, the N+k−ki−n bits of the third code according to a preset puncturing sequence; and when the first BCH code is a systematic code, puncturing, by the encoding apparatus, the first N+k−ki−n bits in non-systematic bits of the third code; or puncturing, by the encoding apparatus, the last N+k−ki−n bits in non-systematic bits of the third code; or puncturing, by the encoding apparatus, the first N+k−ki−n bits in systematic bits of the third code; or puncturing, by the encoding apparatus, the last N+k−ki−n bits in systematic bits of the third code; puncturing, by the encoding apparatus, N+k−ki−n bits in non-systematic bits of the third code according to the preset puncturing sequence; or puncturing, by the encoding apparatus, N+k−ki−n bits in systematic bits of the third code according to the puncturing sequence; or puncturing, by the encoding apparatus, the N+k−ki−n bits of the third code according to the puncturing sequence.
In a specific example, when the first BCH code is an eBCH code, the encoding apparatus may first puncture extension bits of the eBCH code, where the extension bits are parity bits of information bits; and then performing puncturing according to the foregoing puncturing method.
In another optional implementation, when ki corresponding to gi is a second information bit length in information bit lengths corresponding to the polynomials included in the polynomial group, the code rate of the third code is greater than k/n. In this case, a specific method for adding, by the encoding apparatus, redundant bits to the third code to obtain the first code may be: adding, by the encoding apparatus, the redundant bits to the third code to n bits to obtain the first code.
Specifically, a specific method for adding, by the encoding apparatus, the redundant bits to the third code to n bits to obtain the first code may be: adding, by the encoding apparatus, n−N+k+ki redundant bits to the third code to obtain the first code.
Further, a specific method for adding, by the encoding apparatus, n−N−k+ki redundant bits to the third code may be: adding, by the encoding apparatus, n−N−k+ki parity bits to the third code; adding, by the encoding apparatus, repeated bits of n−N−k+ki bits of the third code; and adding, by the encoding apparatus, A parity bits and B repeated bits to the third code, where A+B=n−N−k+ki.
In an example, a specific method for adding, by the encoding apparatus, n−N−k+ki parity bits to the third code may be: generating, by the encoding apparatus, a parity check sum for k information bits of the third code to obtain one parity bit; and generating a parity check sum for k−d information bits in the k information bits to obtain one parity bit until the n−N−k+ki parity bits are obtained, where d is 1, 2, . . . , and k−1; or performing, by the encoding apparatus, simplex encoding on the k information bits of the third code to obtain the n−N−k+ki parity bits.
For example, all k information bits selected by the encoding apparatus generate parity check sums (that is, single parity check codes (SPC) encoding) of the information bits. If a total quantity of bits is less than n, k−1 information bits are selected from the k information bits, and a parity check sum of the k−1 information bits is generated. Because there are a maximum of nchoosk(k, k−1) cases for selecting k−1 information bits from the k information bits, a maximum of nchoosk(k, k−1) such parity bits may be generated, and this method is used until n codeword bits are fully transmitted. If n bits are still not obtained through padding, k−2 information bits are selected from the k information bits, and a parity check sum of the k−2 information bits is generated. Because there are a maximum of nchoosk(k, k−2) cases for selecting k−2 information bits from the k information bits, a maximum of nchoosk(k, k−2) such parity bits may be generated, and this method is used until n codeword bits are fully transmitted. By analogy, sequentially, a checksum of k−3 information bits is generated, . . . , a checksum of two information bits is generated, and a checksum of one bit (that is, the bit itself) is generated. In this way, n−N−k+ki parity bits are obtained.
In an example, when the first BCH code is a non-systematic code, a specific method for adding, by the encoding apparatus, repeated bits of n−N−k+ki bits of the third code may be: adding, by the encoding apparatus, repeated bits of the first n−N−k+ki bits of the third code to the third code; adding, by the encoding apparatus, repeated bits of the last n−N−k+ki bits of the third code to the third code; and adding, by the encoding apparatus to the third code according to a preset sequence, repeated bits of n−N−k+ki bits of the third code that are corresponding to the preset sequence.
In another example, when the first BCH code is a systematic code, a specific method for adding, by the encoding apparatus, repeated bits of n−N−k+ki bits of the third code may be: adding, by the encoding apparatus, repeated bits of the first n−N−k+ki systematic bits of the third code to the third code; adding, by the encoding apparatus, repeated bits of the last n−N−k+ki systematic bits of the third code to the third code; and adding, by the encoding apparatus to the third code according to a preset sequence, repeated bits of n−N−k+ki systematic bits of the third code corresponding to the preset sequence.
In an example, a specific method for adding, by the encoding apparatus, A parity bits and B repeated bits to the third code may be: adding, by the encoding apparatus, the B repeated bits after the A parity bits are added to the third code; or adding, by the encoding apparatus, the A parity bits after the B repeated bits are added to the third code, where in the A parity bits and the B repeated bits that are added by the encoding apparatus to the third code, a bit adjacent to any parity bit is a repeated bit, and an adjacent bit of any repeated bit is a parity bit.
In a specific case, if the first BCH code is an eBCH code, because the codeword bits already include a parity check sum of all the k information bits, there is no need to add a parity bit, and only another redundant bit needs to be added according to the foregoing method.
For example, by using the foregoing method, a code whose n=10 and k=8 is constructed based on a BCH code whose N=15. If the code is represented by using a generator matrix, a procedure may be shown in
In another example, by using the foregoing method, a code whose n=10 and k=8 is constructed based on an eBCH code whose N=16, and a procedure may be shown in
The foregoing process of obtaining the first encoding parameter is a rate matching process.
After the first encoding parameter is obtained, BCH encoding may be performed by using an existing encoding method, for example, an encoding method for linear block codes.
According to the encoding method provided in embodiments of this application, a code length and a code rate of an obtained BCH code are flexible, to satisfy a requirement of flexible channel encoding in wireless communication.
Based on the foregoing embodiments, the generator matrix of the BCH code or the eBCH code in the encoding method provided in embodiments of this application varies with the mother code length. For example, the following lists generator matrices that are of a BCH code and an eBCH code whose mother code length is 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 127, 128, 255, or 256 and that are applicable to this application.
A form of a generator matrix of a 4×4 eBCH code may be:
A form of a generator matrix of a BCH code corresponding to the eBCH code may be a submatrix including the second to fourth rows and the second to fourth columns of the foregoing matrix.
A form of a generator matrix of an 8×8 eBCH code may be:
or,
A form of a generator matrix of a BCH code corresponding to the eBCH code may be a submatrix including the second to eighth rows and the second to eighth columns of any one of the foregoing matrices.
A form of a generator matrix of a 16×16 eBCH code may be:
or,
A form of a generator matrix of a BCH code corresponding to the eBCH code may be a submatrix including the second to 16th rows and the second to 16th columns of any one of the foregoing matrices.
A form of a generator matrix of a 32×32 eBCH code may be:
or,
A form of a generator matrix of a BCH code corresponding to the eBCH code may be a submatrix including the second to 32nd rows and the second to 32nd columns of any one of the foregoing matrices.
A form of a generator matrix of a 64×64 eBCH code may be:
or,
A form of a generator matrix of a BCH code corresponding to the eBCH code may be a submatrix including the second to 64th rows and the second to 64th columns of any one of the foregoing matrices.
A form of a generator matrix of a 128×128 eBCH code may be:
or,
A form of a generator matrix of a BCH code corresponding to the eBCH code may be a submatrix including the second to 128th rows and the second to 128th columns of any one of the foregoing matrices.
A form of a generator matrix of a 256×256 eBCH code may be:
or,
A form of a generator matrix of a BCH code corresponding to the eBCH code may be a submatrix including the second to 256th rows and the second to 256th columns of any one of the foregoing matrices.
Based on the foregoing embodiments, the puncturing sequence and the shortening (shorten) sequence in the encoding method provided in embodiments of this application are used. The puncturing sequence and the shortening sequence may be used for rate matching of a generator matrix-based BCH generation method or a generator polynomial-based BCH generation method. For example, the following lists puncturing sequences and shortening sequences that are applicable to this application.
For a puncturing sequence:
If the mother code length N is 2, 3, 4, 7, or 8, a sequential sequence, that is, 1, 2, 3, . . . , N, may be used for the puncturing sequence.
If the mother code length is 16, the puncturing sequence may be the following possible sequences:
If the mother code length is 15, the puncturing sequence may be a sequence obtained by subtracting 1 from elements in any puncturing sequence other than P16=1; 2; 3; 4; 5; 6; 7; 8 in P16. For example, P15={1; 2; 3; 4; 8; 9; 10; 14}−1=1; 2; 3; 7; 8; 9; 13.
If the mother code length is 32, the puncturing sequence may be the following possible sequences:
If the mother code length is 31, the puncturing sequence may be a sequence obtained by subtracting 1 from elements in any puncturing sequence other than P32=1; 2; 3; . . . ; 16 in P32. For example, P31={1; 26; 4; 11; 24; 25; 29; 12; 30; 9; 27; 18; 19; 16; 17; 3}−1=25; 3; 10; 23; 24; 28; 11; 29; 8; 26; 17; 18; 15; 16; 2.
If the mother code length is 64, the puncturing sequence may be the following possible sequences:
If the mother code length is 63, the puncturing sequence may be a sequence obtained by subtracting 1 from elements in any puncturing sequence other than P64=1; 2; 3; . . . ; 32 in P64. For example, P63={1; 2; 45; 38; 47; 59; 55; 46; 7; 37; 63; 20; 12; 22; 36; 34; 23; 54; 50; 14; 16; 9; 28; 60; 56; 21; 44; 3; 57; 11; 32; 10}−1=1; 44; 37; 46; 58; 54; 45; 6; 36; 62; 19; 11; 21; 35; 33; 22; 53; 49; 13; 15; 8; 27; 59; 55; 20; 43; 2; 56; 10; 31; 9.
If the mother code length is 128, the puncturing sequence may be:
If the mother code length is 127, the puncturing sequence may be a sequence obtained by subtracting 1 from elements in any puncturing sequence other than P128=1, 2, 3, . . . , 64 in P128. For example, P127={1; 9; 35; 37; 15; 43; 22; 126; 95; 38; 101; 69; 44; 24; 63; 110; 60; 117; 2; 120; 17; 84; 118; 4; 127; 31; 123; 82; 112; 34; 99; 29; 51; 116; 108; 125; 111; 104; 114; 77; 83; 85; 105; 79; 113; 28; 86; 33; 90; 73; 78; 80; 70; 124; 75; 71; 72; 68; 59; 21; 67; 93; 62; 58}−1=8; 34; 36; 14; 42; 21; 125; 94; 37; 100; 68; 43; 23; 62; 109; 59; 116; 1; 119; 16; 83; 117; 3; 126; 30; 122; 81; 111; 33; 98; 28; 50; 115; 107; 124; 110; 103; 113; 76; 82; 84; 104; 78; 112; 27; 85; 32; 89; 72; 77; 79; 69; 123; 74; 70; 71; 67; 58; 20; 66; 92; 61; 57.
For a shortening (shorten) sequence:
If the mother code length N is 2, 3, 4, 7, or 8, a reverse-order sequence may be used, that is, N, N−1, . . . , 3, 2, or 1.
If the mother code length is 16, the shortening sequence may be the following possible sequences:
If the mother code length is 15, the shortening sequence may be S16-1, that is, a sequence obtained by subtracting 1 from elements in any one of the foregoing S16. For example, S15={16; 15; 14; 12; 13; 11; 10; 9}−1=15; 14; 13; 11; 12; 10; 9; 8.
If the mother code length is 32, the shortening sequence may be the following possible sequences:
If the mother code length is 31, the shortening sequence may be S32-1, that is, a sequence obtained by subtracting 1 from elements in any one of the foregoing S32. For example, S31={32; 31; 30; 29; 28; 25; 27; 26; 23; 24; 18; 21; 22; 19; 20; 17}−1=31; 30; 29; 28; 27; 24; 26; 25; 22; 23; 17; 20; 21; 18; 19; 16.
If the mother code length is 64, the shortening sequence may be:
If the mother code length is 63, the shortening sequence may be S64-1, that is, a sequence obtained by subtracting 1 from elements in any one of the foregoing S64. For example, S63={64; 62; 60; 58; 63; 56; 61; 59; 55; 57; 54; 53; 52; 51; 47; 50; 49; 48; 46; 45; 44; 43; 42; 41; 40; 39; 38; 37; 36; 35; 32; 34}−1=63; 61; 59; 57; 62; 55; 60; 58; 54; 56; 53; 52; 51; 50; 46; 49; 48; 47; 45; 44; 43; 42; 41; 40; 39; 38; 37; 36; 35; 34; 31; 33.
If the mother code length is 128, the shortening sequence may be: S64=128; 127; . . . ; 66; 65 (reverse-order sequence).
If the mother code length is 127, the shortening sequence may be S128-1, that is, a sequence obtained by subtracting 1 from elements in any 532. For example, S127={128; 127; . . . ; 66; 65}−1=127; 126; . . . ; 65; 64.
Currently, code length and code rate flexibility are important or necessary requirements for channel encoding in wireless communication, and cannot be satisfied in existing solutions. According to the encoding method in this application, a code length and a code rate of an obtained BCH code may be flexible, and satisfy a requirement of channel encoding of a wireless channel. The generator polynomial-based manner and the generator matrix-based manner have low implementation complexity. In this application, code distance maximization is considered in a rate matching process, thereby improving maximum likelihood decoding performance. A code distance difference between a code generated by using an embodiment of the encoding method provided in this application (rate matching on which a code rate depends, and a code rate threshold Rthr=1/3) and a code with a known optimal code distance. For example, as shown in a schematic diagram of code distance performance shown in
Further, in OSD decoding or BMA decoding, performance of a BCH code obtained by using the encoding method in this application is better than that of an existing polar code. For example, as shown in
Based on the foregoing embodiments, an embodiment of this application provides an encoding apparatus. Refer to
In an optional implementation, when determining the first encoding parameter based on the first BCH code, the first processing unit 1101 is specifically configured to: determine a generator matrix of the first BCH code; and determine the first encoding parameter based on the generator matrix of the first BCH code and a puncturing sequence, where an element included in the puncturing sequence is a column index in the generator matrix of the first BCH code.
In an optional implementation, when determining the first encoding parameter based on the generator matrix of the first BCH code and the puncturing sequence, the first processing unit 1101 is specifically configured to: select the last k rows of the generator matrix of the first BCH code to obtain a first matrix; and sequentially puncture, according to the puncturing sequence, locations corresponding to elements in the puncturing sequence in the first matrix to obtain the first encoding parameter, where the first encoding parameter is a matrix including k rows and n columns.
In an optional implementation, a code rate k/n of the first code is less than or equal to a code rate threshold.
In an optional implementation, when determining the first encoding parameter based on the first BCH code, the first processing unit 1101 is specifically configured to: determine a generator matrix of the first BCH code; and determine the first encoding parameter based on the generator matrix of the first BCH code and a shortening sequence, where an element included in the shortening sequence is a column index in the generator matrix of the first BCH code.
In an optional implementation, when determining the first encoding parameter based on the generator matrix of the first BCH code and the shortening sequence, the first processing unit 1101 is specifically configured to: sequentially set, according to the shortening sequence, locations corresponding to elements in the shortening sequence to zero in the generator matrix to obtain a second matrix; and perform selection starting from the last row of the second matrix, and skip a row in which 1 exists at a location corresponding to an element in the shortening sequence until k rows are selected to obtain the first encoding parameter, where the first encoding parameter is a matrix including k rows and n columns.
In an optional implementation, a code rate k/n of the first code is greater than or equal to a code rate threshold.
In an optional implementation, the code rate threshold is any one of 1/4, 1/2, 3/4, 1/3, 2/3, 1/8, 3/8, 5/8, 7/8, 1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16, or 15/16.
Specifically, when determining the generator matrix of the first BCH code, the first processing unit 1101 is specifically configured to: determine the generator matrix of the first BCH code based on a generator polynomial group of the first BCH code, where the generator polynomial group of the first BCH code includes the following polynomials: g1, g2, g3, . . . , and gx, and x is an integer greater than or equal to 1.
For example, when determining the generator matrix of the first BCH code based on the generator polynomial group of the first BCH code, the first processing unit 1101 is specifically configured to: determine the generator matrix of the first BCH code based on a row vector corresponding to each polynomial in the generator polynomial group of the first BCH code and a row vector obtained by performing right shift on the row vector, where a length of a row vector corresponding to each row in the generator matrix of the first BCH code is equal to a mother code length of the first BCH code, and a quantity of rows is equal to the mother code length; the first row is a row vector corresponding to the polynomial g1, and the second row, . . . , and the (k1−k2)th row are row vectors obtained by shifting the row vector corresponding to the first row by one bit to the right, . . . , and k1−k2−1 bits to the right respectively; . . . ; the (N−ki+1)th row is a row vector corresponding to the polynomial gi, and the (N−ki+2)th row, . . . , and the (N−kj)th row are row vectors obtained by shifting the row vector corresponding to the (N−ki+1)th row by one bit to the right, . . . , and ki−kj−1 bits to the right; . . . ; and the (N−kx+1)th row is a row vector corresponding to the polynomial gx, and the (N−kx+2)th row is row vector obtained by shifting the row vector corresponding to the (N−kx+1)th row by one bit, . . . , and kx-1 bits to the right; and k1 is an information bit length corresponding to g1, k2 is an information bit length corresponding to g2, ki is an information bit length corresponding to gi, kj is an information bit length corresponding to gj, kx is an information bit length corresponding to gx, j=i+1, and N is the mother code length.
In an example, when the first encoding parameter is the first code, and when determining the first encoding parameter based on the first BCH code, the first processing unit 1101 is specifically configured to: determine a target polynomial gi in a generator polynomial group of the first BCH code; determine a second code based on gi, where the second code has a code length of N and an information bit length of ki, N is a mother code length of the first BCH code, and ki is an information bit length corresponding to gi; and determine the first code based on the second code, where gi is one of polynomials g1, g2, g3, . . . , and gx included in the generator polynomial group, and x is an integer greater than or equal to 1.
Specifically, when determining the first code based on the second code, the first processing unit 1101 is specifically configured to: shorten the second code to obtain a third code; when a code rate of the third code is less than k/n, puncture the third code to obtain the first code; and when the code rate of the third code is greater than k/n, add redundant bits to the third code to obtain the first code, where an information bit length of the third code is k.
For example, when shortening the second code to obtain the third code, the first processing unit 1101 is specifically configured to: shorten the second code by ki−k bits to obtain the third code, where a code length of the third code is N+k−ki.
In a possible implementation, ki corresponding to gi is a first information bit length in information bit lengths corresponding to the polynomials included in the polynomial group, and the first information bit length is a maximum value less than N+k−n; and when puncturing the third code to obtain the first code, the first processing unit 1101 is specifically configured to: puncture the third code to n bits to obtain the first code.
Specifically, when puncturing the third code to n bits to obtain the first code, the first processing unit 1101 is specifically configured to: puncture N+k−ki−n bits of the third code to obtain the first code.
For example, when puncturing the N+k−ki−n bits of the third code, the first processing unit 1101 is specifically configured to: when the first BCH code is a non-systematic code, puncture the first N+k−ki−n bits of the third code; or puncture the last N+k−ki−n bits of the third code; or puncture the N+k−ki−n bits of the third code according to a preset puncturing sequence; and when the first BCH code is a systematic code, puncture the first N+k−ki−n bits in non-systematic bits of the third code; or puncture the last N+k−ki−n bits in non-systematic bits of the third code; or puncture the first N+k−ki−n bits in systematic bits of the third code; or puncture the last N+k−ki−n bits in systematic bits of the third code; puncture N+k−ki−n bits in non-systematic bits of the third code according to the preset puncturing sequence; or puncture N+k−ki−n bits in systematic bits of the third code according to the puncturing sequence; or puncture the N+k−ki−n bits of the third code according to the puncturing sequence.
Optionally, when the first BCH code is an extended BCH eBCH code, the first processing unit 1101 is further configured to puncture extension bits of the eBCH code, where the extension bits are parity bits of information bits.
In another implementation, ki corresponding to gi is a second information bit length in information bit lengths corresponding to the polynomials included in the polynomial group, and the second information bit length is a minimum value greater than N+k−n; and when adding the redundant bits to the third code to obtain the first code, the first processing unit 1101 is specifically configured to: add the redundant bits to the third code to n bits to obtain the first code.
In an example, when adding the redundant bits to the third code to n bits to obtain the first code, the first processing unit 1101 is specifically configured to: add n−N+k+ki redundant bits to the third code to obtain the first code.
Specifically, when adding the n−N−k+ki redundant bits to the third code, the first processing unit 1101 is specifically configured to: add n−N−k+ki parity bits to the third code; add repeated bits of n−N−k+ki bits of the third code; and add A parity bits and B repeated bits to the third code, where A+B=n−N−k+ki.
For example, when adding the n−N−k+ki parity bits to the third code, the first processing unit 1101 is specifically configured to: generate a parity check sum for k information bits of the third code to obtain one parity bit; and generate a parity check sum for k−d information bits in the k information bits to obtain one parity bit until the n−N−k+ki parity bits are obtained, where d is 1, 2, . . . , and k−1; or perform simplex encoding on the k information bits of the third code to obtain the n−N−k+ki parity bits.
For example, when the first BCH code is a non-systematic code, and when adding the repeated bits of n−N−k+ki bits of the third code, the first processing unit 1101 is specifically configured to: add repeated bits of the first n−N−k+ki bits of the third code to the third code; add repeated bits of the last n−N−k+ki bits of the third code to the third code; and add, to the third code according to a preset sequence, repeated bits of n−N−k+ki bits of the third code that are corresponding to the preset sequence.
For example, when the first BCH code is a systematic code, and when adding repeated bits of n−N−k+ki bits of the third code, the first processing unit 1101 is specifically configured to: add repeated bits of the first n−N−k+ki systematic bits of the third code to the third code; add repeated bits of the last n−N−k+ki systematic bits of the third code to the third code; and add, to the third code according to a preset sequence, repeated bits of n−N−k+ki systematic bits of the third code corresponding to the preset sequence.
For example, when adding the A parity bis and the B repeated bits to the third code, the first processing unit 1101 is specifically configured to: add the B repeated bits after the A parity bis are added to the third code; or add the A parity bis after the B repeated bits are added to the third code, where in the A parity bits and the B repeated bits that are added to the third code, a bit adjacent to any parity bit is a repeated bit, and an adjacent bit of any repeated bit is a parity bit.
In an optional implementation, when shortening the second code by the ki−k bits, the first processing unit 1101 is specifically configured to: when the first BCH code is a non-systematic code, shorten the first ki−k bits of the second code; or shorten the last ki−k bits of the second code; or shorten the ki−k bits of the second code according to a preset shortening sequence; and when the first BCH code is a systematic code, shorten the first ki−k bits in systematic bits of the second code; or shorten the last ki−k bits in systematic bits of the second code; or shorten the ki−k bits in systematic bits of the second code according to the shortening sequence.
It should be noted that, in embodiments of this application, division into the units is an example, and is merely logical function division. During actual implementation, another division manner may be used. Functional units in embodiments of this application may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units may be integrated into one unit. The integrated unit may be implemented in a form of hardware, or may be implemented in a form of a software function unit.
When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of this application essentially, or the part contributing to the conventional technology, or all or a part of the technical solutions may be implemented in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) or a processor to perform all or a part of the steps of the methods in embodiments of this application. The foregoing storage medium includes any medium that can store program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc.
Based on the foregoing embodiments, for the encoding apparatus provided in embodiments of this application, further refer to
Specifically, the processor 1202 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP. The processor 1202 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field programmable logic gate array (FPGA), a generic array logic (GAL), or any combination thereof.
The transceiver 1201, the processor 1202, and the memory 1203 are connected to each other. Optionally, the transceiver 1201, the processor 1202, and the memory 1203 are connected to each other by using the bus 1204. The bus 1204 may be a peripheral component interconnect standard (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus may include an address bus, a data bus, a control bus, and the like. For ease of representation, the bus is only represented by one thick line in
In an optional implementation, the memory 1203 is configured to store a program and the like. Specifically, the program may include program code, and the program code includes computer operation instructions. The memory 1203 may include a RAM, and may further include a non-volatile memory, for example, one or more magnetic disk memories. The processor 1202 executes the application program stored in the memory 1203, to implement the foregoing functions, to implement functions of the encoding apparatus 1200.
Specifically, the encoding apparatus 1200 may implement the functions of the encoding apparatus in the embodiment shown in
In an optional implementation, the processor 1202 may include a constructor, a coder, a decoder, and the like. The constructor, the coder, the decoder, and the like jointly implement the functions of the processor.
In an optional implementation, the transceiver 1201 may send coded bits, or may receive information, data, or the like from another device.
Based on the foregoing embodiments, an embodiment of this application provides a communication system. The communication system may include the encoding apparatus and the like in the foregoing embodiments.
An embodiment of this application further provides a computer-readable storage medium. The computer-readable storage medium is configured to store a computer program. When the computer program is executed by a computer, the computer may implement the encoding method provided in the foregoing method embodiments.
An embodiment of this application further provides a computer program product. The computer program product is configured to store a computer program. When the computer program is executed by a computer, the computer may implement the encoding method provided in the foregoing method embodiments.
An embodiment of this application further provides a chip. The chip is coupled to a memory, and the chip is configured to implement the encoding method provided in the foregoing method embodiments.
An embodiment of this application further provides a chip system. The chip system includes a processor, configured to support the foregoing encoding apparatus in implementing the foregoing functions. In a possible design, the chip system further includes a memory. The memory is configured to store program instructions and data that are necessary for the encoding apparatus. The chip system may include a chip, or may include a chip and another discrete component.
A person skilled in the art should understand that embodiments of this application may be provided as a method, a system, or a computer program product. Therefore, this application may use a form of hardware only embodiments, software only embodiments, or embodiments with a combination of software and hardware. In addition, this application may use a form of a computer program product that is implemented on one or more computer-usable storage media (including but not limited to a disk memory, a CD-ROM, an optical memory, and the like) that include computer-usable program code.
This application is described with reference to the flowcharts and/or block diagrams of the method, the device (system), and the computer program product according to this application. It should be understood that computer program instructions may be used to implement each process and/or each block in the flowcharts and/or the block diagrams and a combination of a process and/or a block in the flowcharts and/or the block diagrams. The computer program instructions may be provided for a general-purpose computer, a dedicated computer, an embedded processor, or a processor of another programmable data processing device to generate a machine, so that the instructions executed by the computer or the processor of the another programmable data processing device generate an apparatus for implementing a specific function in one or more procedures in the flowcharts and/or in one or more blocks in the block diagrams.
These computer program instructions may be stored in a computer-readable memory that can instruct the computer or any other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate an artifact that includes an instruction apparatus. The apparatus device implements a specific function in one or more processes in the flowcharts and/or in one or more blocks in the block diagrams.
The computer program instructions may alternatively be loaded onto a computer or another programmable data processing device, so that a series of operations and steps are performed on the computer or the another programmable device, so that computer-implemented processing is generated. Therefore, the instructions executed on the computer or the another programmable device provide steps for implementing a specific function in one or more procedures in the flowcharts and/or in one or more blocks in the block diagrams.
It is clear that a person skilled in the art can make various modifications and variations to this application without departing from the scope of this application. This application is intended to cover these modifications and variations of this application provided that they fall within the scope of protection defined by the following claims and their equivalent technologies.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202010903282.1 | Sep 2020 | CN | national |
This application is a continuation of International Application No. PCT/CN2021/112747, filed on Aug. 16, 2021, which claims priority to Chinese Patent Application No. 202010903282.1, filed on Sep. 1, 2020. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties.
| Number | Name | Date | Kind |
|---|---|---|---|
| 9203434 | Garani | Dec 2015 | B1 |
| 20080040644 | Spencer | Feb 2008 | A1 |
| 20140068391 | Goel | Mar 2014 | A1 |
| Number | Date | Country |
|---|---|---|
| 105429646 | Mar 2016 | CN |
| 106603085 | Apr 2017 | CN |
| WO-2012074334 | Jun 2012 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20230308117 A1 | Sep 2023 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2021/112747 | Aug 2021 | WO |
| Child | 18176217 | US |
