Patent Application
20100232597
This application claims the priority of a Chinese Patent Application No. 200610041863.9, entitled “METHOD FOR ENCRYPTION AND DECRYPTION PROCESSING IN SMS4 CRYPTOGRAPHIC ALGORITHM” and filed with the Chinese Patent Office on Mar. 2, 2006, the entirety of which is incorporated herein by reference.
The present invention relates to the field of information technologies, and in particular, to a method and system for encryption and decryption processing in SMS4 cryptographic algorithm.
The critical components in implementing SMS4 cryptographic algorithm are a key expansion unit and an encryption and decryption unit, the internal structures and processing processes of which are basically the same. The encryption and decryption unit mainly consists of three parts, i.e. a data registering unit, a constant array storing unit and a data converting unit.
The data registering unit consists of a general trigger for registering data. The data registered in the unit is unchanged within a clock period. The general trigger is a data temporary storage component where the data of a data input end is sent to an output end of the trigger at a rising clock edge or a falling clock edge, while the data of the trigger output end is unchanged at other time.
The constant array storing unit is a storing unit for storing a constant array. The constant array in the prior art is generally a data array with 32-bit width and 32-bit depth prepared before encryption and decryption processing. The data in the constant array storing unit are arranged in a descending sequence of addresses, and named as rk0, rk1 . . . rk31.
The data converting unit is a unit for data processing according to the cryptographic algorithm. For example, in the data processing according to the National SMS4 cryptographic algorithm, the operation performed by the data converting unit only includes one conversion specified in the cryptographic algorithm.
Conventionally, the encryption and decryption data processing method according to SMS4 cryptographic algorithm is as follows,
1) inputting external data into the data registering unit; in particular, data are outputted from the output end of the data registering unit after the external data are inputted into the data registering unit; for example, the external data of 128 bits may be divided into four data blocks with each including 32 bits, and named as A0, A1, A2 and A3, respectively; the data outputted from the output end of the data registering unit are still in 128 bits, which may be divided into four data blocks with each including 32 bits, and named as a0, a1, a2 and a3, respectively;
2) making a data conversion processing;
the data from the output end of the data registering unit is inputted into the data converting unit for data conversion processing; for example, the data a0, a1, a2 and a3 from the output end of the data registering unit are converted into 128-bit data C0, C1, C2 and C3 via the data converting unit;
3) making a second data conversion processing;
the data after the previous data conversion processing are stored into the data registering unit again, then the data from the output end of the data registering unit is inputted the data converting unit again for a second data conversion processing;
4) repeating the second data conversion processing for obtaining the final data processing result.
For external data with 128 bits, the second data conversion processing shall be repeated 30 times, i.e. the data conversion processing shall be made 32 times in all for obtaining the final data processing result.
In the prior art stated above, a constant array with 32-bit width and 32-bit depth is prepared before the encryption and decryption processing, and the data converting unit performs only one conversion operation specified in the cryptographic algorithm, as a result, the data conversion processing shall be repeated many times. For example, in order to encrypt 128-bit data, the data conversion processing has to be repeated 32 times for obtaining the final data processing result.
Furthermore, the encryption and decryption efficiency is low in the prior art stated above. The encryption efficiency is the data amount encrypted in unit time. For example, the data conversion processing is repeated 32 times for encrypting 128-bit data. Due to the generally low clock frequency in current practical applications, the amount of data encrypted in unit time is less, and the efficiency is low. If the encryption efficiency is specified, the clock frequency should be increased. However, in the practical applications, the clock frequency is hard to increase; therefore, the actual encryption efficiency is still low. The increasing of the clock frequency further causes difficulties in design and implementation of the integrated circuit, and poor signal integrity and a higher design cost. Furthermore, the integrated circuit designed according to the method in the prior art, when applied in a system, may also result in the increasing of cost of a Printed Circuit Board (PCB), and the difficulties in designing the PCB and product implementation; additionally, great interferences may be present in the system, which impacts on the normal and high-efficiency work of other equipments and devices.
An embodiment of the present invention provides a method for encryption and decryption processing in SMS4 cryptographic algorithm and a system thereof, which reduces repeating times of data conversion processing and improves encryption efficiency.
The technical solutions of the invention are as follows.
A method for encryption and decryption processing in SMS4 cryptographic algorithm includes the step of repeating encryption and decryption data processing, in particular, the method includes:
arranging data width and depth of a first constant array, forming data with a same depth as one row, and storing the first constant array;
outputting registered external data at the rising edge or falling edge of a first clock period;
making a data conversion processing for a first data in a first row of the stored first constant array with the registered external data in the first clock period to obtain a first conversion data of the first clock period;
making a data conversion processing for a second data in the first row of the stored first constant array with the first conversion data of the first clock period to obtain a second conversion data of the first clock period;
by analogy, making a data conversion processing for all the rest data in the first row of the stored first constant array in sequence to obtain conversion-processing data of the first clock period;
registering the conversion-processing data of the first clock period at the rising edge or falling edge of a second clock period;
making a data conversion processing for a first data in a second row of the stored first constant array with the registered conversion-processing data of the first clock period in the second clock period to obtain a first conversion data of the second clock period;
making a data conversion processing for a second data in the second row of the stored first constant array with the first conversion data of the second clock period to obtain a second conversion data of the second clock period;
by analogy, making a data conversion processing for all the rest data in the second row of the stored first constant array in sequence to obtain conversion-processing data of the second clock period; and
repeating the data conversion processing process until completing the data conversion processing processes, the number of which equals the value of the depth, thereby obtaining a final result of the repeating encryption and decryption processing.
Preferably, the first constant array meets the following requirements,
data are arranged in a descending sequence of addresses and stored;
width and depth of data of the first constant array are arranged based on the number of the data conversion processings, and the product of the width and the depth is 1024; and data with a same depth are formed as one row.
Preferably, before the step of the repeating encryption and decryption data processing, a step of a first additional encryption and decryption data processing is included, the first additional encryption and decryption data processing includes,
arranging the data width of a second constant array according to the number of the data conversion processings in the step of the first additional encryption and decryption data processing, the data depth of the second constant array being 1, forming the data with a same depth as one row, and storing the second constant array;
outputting the registered external data at a rising edge or falling edge of the clock period;
making a data conversion processing for a first data in the stored second constant array with the registered external data in this clock period to obtain a first conversion data;
making a data conversion processing for a second data in the stored second constant array with the first conversion data to obtain a second conversion data; and
by analogy, making a data conversion processing for all the rest data in the stored second constant array in sequence in the step of the first additional encryption and decryption data processing to obtain a result of the first additional encryption and decryption data processing, which serves as the external data in the repeating encryption and decryption data processing.
Preferably, the first constant array and the second constant array meet the following conditions,
the data width of the second constant array equals the product of the number of data conversions in the step of the first additional encryption and decryption data processing and 32; the data depth of the second constant array is 1; and the product of the data width and depth of the second constant array is determined; and
the sum of the product of the data width and depth of the second constant array and the product of the data width and depth of the first constant array is 1024.
Preferably, after the step of the repeating encryption and decryption data processing, a step of a second additional encryption and decryption data processing is further included, which includes:
arranging the data width of a third constant array according to the number of the data conversion processings in the step of the second additional encryption and decryption data processing, the data depth of the third constant array being 1, forming the data with a same depth as one row, and storing the third constant array;
registering the result of the repeating encryption and decryption data processing, and output the registered data at the rising edge or falling edge of a clock period;
making a data conversion processing for a first data in the stored third constant array with the registered external data in this clock period to obtain a first conversion data;
making a data conversion processing for a second data in the stored third constant array with the first conversion data to obtain a second conversion data; and
by analogy, making a data conversion processing for all the rest data in the stored third constant array in sequence in the step of the second additional encryption and decryption data processing to obtain a result of the second additional encryption and decryption data processing which serves as a final encryption and decryption data processing result.
Preferably, the first constant array, the second constant array and the third constant array meet the following conditions.
the data width of the second constant array equals the product of the number of data conversions in the step of the first additional encryption and decryption data processing and 32; the data depth of the second constant array is 1; and the product of the data width and depth of the second constant array is determined;
the data width of the third constant array equals the product of the number of data conversions in the step of the second additional encryption and decryption data processing and 32; the data depth of the third constant array is 1; and the product of the data width and depth of the third constant array is determined; and
the sum of the product of the data width and depth of the second constant array, the product of the data width and depth of the third constant array, and the product of the data width and depth of the first constant array is 1024.
Preferably, after the step of the repeating encryption and decryption data processing, a step of a second additional encryption and decryption data processing is further included, which includes:
arranging the data width of a third constant array according to the number of the data conversion processings in the step of the second additional encryption and decryption data processing, where the data depth of the third constant array is 1 and the data with a same depth are formed as one row, and storing the third constant array;
registering the result of the repeating encryption and decryption data processing, and output the registered data at the rising edge or falling edge of a clock period;
making a data conversion processing for a first data in the stored third constant array with the registered external data in this clock period to obtain a first conversion data;
making a data conversion processing for a second data in the stored third constant array with the first conversion data to obtain a second conversion data; and
by analogy, making a data conversion processing for all the rest data in the stored third constant array in sequence in the step of the second additional encryption and decryption data processing to obtain a result of the second additional encryption and decryption data processing which serves as a final encryption and decryption data processing result.
Preferably, the first constant array and the third constant array meet the following conditions.
the data width of the third constant array equals the product of the number of data conversions in the step of the second additional encryption and decryption data processing and 32; the data depth of the third constant array is 1; and the product of the data width and depth of the third constant array is determined; and
the sum of the product of the data width and depth of the third constant array, and the product of the data width and depth of the first constant array is 1024.
A system for encryption and decryption processing in SMS4 cryptographic algorithm includes a repeating encryption and decryption data processing device which includes a first constant array storing unit, a first data registering unit and a first data converting unit, where the first data converting unit includes a plurality of N data converting sub-units. In particular,
the first constant array storing unit is adapted to store a first constant array, and send respectively each row of data in the first constant array in sequence to the plurality of N data converting sub-units of the first data converting unit in each clock period;
the first data registering unit is adapted to register data, delivery the registered data from an input end to an output end at the rising edge or falling edge of each clock period, and output the data to a first data converting sub-unit in each clock period; and
the plurality of N data converting sub-units are adapted to make a data conversion processing in sequence in each clock period, and output the obtained conversion data to a next data converting sub-unit for subsequent processing, until completing the data conversion processing processes, the number of which equals the value of the depth, thereby obtaining a result of the repeating encryption and decryption data processing.
Preferably, the first constant array meets the following conditions.
The width and depth of data are arranged based on the number of the data converting sub-units, N, and the product of the width and the depth is 1024; data with a same depth are formed as one row and data are arranged in a descending sequence of addresses.
Preferably, a first additional encryption and decryption data processing device is further included. The device includes a second constant array storing unit, a second data registering unit and a second data converting unit, where the second data converting unit includes a plurality of M data converting sub-units. In particular,
the second constant array storing unit is adapted to store a second constant array, and output respectively each row of data in the second constant array in sequence to the plurality of M data converting sub-units of the second data converting unit in each clock period;
the second data registering unit is adapted to register data, delivery the registered data from an input end to an output end at the rising edge or falling edge of each clock period, and output the data to a second data converting sub-unit in each clock period; and
the plurality of M data converting sub-units are adapted to make a data conversion processing in sequence in each clock period, and output the obtained conversion data to a next data converting sub-unit for subsequent processing, until completing the data conversion processing processes, the number of which equals the value of the depth, thereby obtaining a result of a first additional encryption and decryption data processing, which serves as the registered data in the repeating encryption and decryption data processing.
Preferably, the first constant array and the second constant array meet the following conditions.
The data width and depth of the second constant array are arranged based on the number of the data converting sub-units, M, in the first additional encryption and decryption data processing device, and data with a same depth are formed as one row; the data width of the second constant array equals the product of the number of the data converting sub-units, M, in the first additional encryption and decryption data processing device and 32; the data depth of the second constant array is 1; and the product of the data width and depth of the second constant array is M×32×1; and
The sum of the product of the data width and depth of the second constant array, M×32×1, and the product of the data width and depth of the first constant array is 1024.
Preferably, a second additional encryption and decryption data processing device is further included. The device includes a third constant array storing unit, a third data registering unit and a third data converting unit, where the third data converting unit includes a plurality of Q data converting sub-units. In particular,
the third constant array storing unit is adapted to store a third constant array, and output respectively each row of data in the third constant array in sequence to the plurality of Q data converting sub-units of the third data converting unit in each clock period; the data width and depth of the third constant array are arranged based on the number of the data converting sub-units, Q; the data depth of the third constant array is 1; and data with a same depth are formed as one row;
the third data registering unit is adapted to register data, delivery the registered data from an input end to an output end at the rising edge or falling edge of each clock period, and output the data to a third data converting sub-unit in each clock period; and
the plurality of Q data converting sub-units are adapted to make a data conversion processing in sequence in each clock period, and output the obtained conversion data to a next data converting sub-unit for subsequent processing, until completing the data conversion processing processes, the number of which equals the value of the depth, thereby obtaining a result of a second additional encryption and decryption data processing, which serves as the final result of the encryption and decryption data processing.
Preferably, the first constant array, the second constant array and the third constant array meet the following conditions,
the data width and depth of the second constant array are arranged based on the number of the data converting sub-units, M, in the first additional encryption and decryption data processing device, and data with a same depth are formed as one row; the data width of the second constant array equals the product of the number of the data converting sub-units, M, in the first additional encryption and decryption data processing device and 32; the data depth of the second constant array is 1; and the product of the data width and depth of the second constant array is M×32×1;
the data width and depth of the third constant array are arranged based on the number of the data converting sub-units, Q, in the second additional encryption and decryption data processing device, and data with a same depth are formed as one row; the data width of the third constant array equals the product of the number of the data converting sub-units, Q, in the second additional encryption and decryption data processing device and 32; the data depth of the third constant array is 1; and the product of the data width and depth of the third constant array is Q×32×1; and
the sum of the product of the data width and depth of the second constant array, M×32×1, the product of the data width and depth of the third constant array, Q×32×1, and the product of the data width and depth of the first constant array is 1024.
Preferably, a second additional encryption and decryption data processing device is further included. The device includes a third constant array storing unit, a third data registering unit and a third data converting unit, where the third data converting unit includes a plurality of Q data converting sub-units. In particular,
the third constant array storing unit is adapted to store a third constant array, and output respectively each row of data in the third constant array in sequence to the plurality of Q data converting sub-units of the third data converting unit in each clock period;
the third data registering unit is adapted to register data, delivery the registered data from an input end to an output end at the rising edge or falling edge of each clock period, and output the data to a third data converting sub-unit in each clock period; and
the plurality of Q data converting sub-units are adapted to make a data conversion processing in sequence in each clock period, and output the obtained conversion data to a next data converting sub-unit for subsequent processing, until completing the data conversion processing processes, the number of which equals the value of the depth, thereby obtaining a result of a second additional encryption and decryption data processing, which serves as the final result of the encryption and decryption data processing.
Preferably, the first constant array and the third constant array meet the following conditions,
the data width and depth of the third constant array are arranged based on the number of the data converting sub-units, Q, in the second additional encryption and decryption data processing device, and data with a same depth are formed as one row; the data width of the third constant array equals the product of the number of the data converting sub-units, Q, in the second additional encryption and decryption data processing device and 32; the data depth of the third constant array is 1; and the product of the data width and depth of the third constant array is Q×32×1; and
the sum of the product of the data width and depth of the third constant array, Q×32×1, and the product of the data width and depth of the first constant array is 1024.
In the method of the invention for encryption and decryption processing in SMS4 cryptographic algorithm, the repeating times of the data conversion processing is reduced by arranging a constant array and providing a corresponding data converting sub-unit. The efficiency of encryption is improved due to a large increase of data amount encrypted in unit time. For example, a final data processing result may be outputted by operating for only 8 clock periods if 4 data converting sub-units are employed for encrypting 128-bit data. Therefore, in the case of a same clock frequency, the efficiency of encryption is improved by four times.
In the system of the invention for encryption and decryption processing in SMS4 cryptographic algorithm, on the premise of meeting the required encryption efficiency, the clock frequency is only 1/n of the one in the prior art. For example, the clock frequency is only ¼ of the one in the prior art if 4 data converting sub-units are employed for encrypting 128-bit data.
Further, in the case of the same processing efficiency, the design and implementation of the integrated circuit in the solution of the invention is easier; the integrity of signals is largely optimized and the design cost is reduced. Furthermore, using the integrated circuit designed in the invention, the clock frequency may only be 1/n of the one in the prior art in the case of meeting the required encryption efficiency. With the same processing efficiency, the PCB cost may be reduced, and the PCB design and the product can be easily achieved; the interference in the system is reduced, and the impacts on other equipments and devices are also decreased largely.
The first data registering unit 1 is adapted to register external data and a result of last data conversion processing. The first data registering unit 1 may generally use a general trigger, such as a D trigger, a JK trigger and so on. A general trigger is a data temporary storage component where the data of a data input end is transmitted to an output end of the trigger at the rising clock edge or falling clock edge, while the data of the trigger output end is unchanged at other time. In other words, in a same data conversion processing period, the data registered by the first data registering unit 1 is unchanged.
The first data converting unit 2 is adapted to make data processing according to the cryptographic algorithm requirement. For example, if making data processing according to the National SMS4 cryptographic algorithm, the operation completed by the first data converting unit 2 may simply include one conversion specified in the cryptographic algorithm.
The constant array storing unit 3 is adapted to store constant array data. The constant array employed in the first embodiment of the invention is the resultant data obtained upon key expansion processing, which are arranged in a descending sequence of addresses; the width and depth of the constant array are arranged based on the number of the data converting sub-units included in the first data converting unit 2 in the cycling body, and the product of the width and depth is 1024. For example, if 4 data converting sub-units are used, the width of the constant array is 128 bits, and the depth is 8; if 8 data converting sub-units are used, the width of the constant array is 256 bits and the depth is 4.
Referring to
1. arranging the data width and depth of a first constant array base on the number of the data converting sub-units, where data with a same depth are formed as one row, and storing the first constant array;
2. outputting registered external data at the rising edge or falling edge of a first clock period;
3. making a data conversion processing for a first data in a first row of the stored first constant array with the registered external data in the first clock period to obtain a first conversion data of the first clock period;
making a data conversion processing for a second data in the first row of the stored first constant array with the first conversion data of the first clock period to obtain a second conversion data of the first clock period;
by analogy, making a data conversion processing for all the rest data in the first row of the stored first constant array in sequence to obtain conversion-processing data of the first clock period;
4. registering the conversion-processing data of the first clock period at the rising edge or falling edge of a second clock period;
making a data conversion processing for a first data in a second row of the stored first constant array with the registered first conversion-processing data in the second clock period to obtain a first conversion data of the second clock period;
making a data conversion processing for a second data in the second row of the stored first constant array with the first conversion data of the second clock period to obtain a second conversion data of the second clock period;
by analogy, making a data conversion processing for all the rest data in the second row of the stored first constant array in sequence to obtain conversion-processing data of the second clock period; and
5. repeating the above data conversion processing process until completing the data conversion processing processes, the number of which equals the value of the depth, thereby obtaining a result of the repeating encryption and decryption processing.
Referring to
1) preparing a constant array;
(1) arranging data of a first constant array obtained upon key expansion processing in a descending sequence of addresses, and storing into the constant array storing unit 3;
(2) arranging the width and depth based on the number of the data converting sub-units included in the data converting unit 2 in the data conversion processing, where the product of the width and depth is 1024; and
(3) forming the data with a same depth as one row in the first constant array.
2) inputting external data to the first data registering unit 1;
(1) inputting the external data to an input end of the first data registering unit 1;
(2) delivering the data from the input end of the first data registering unit 1 to its output end at the clock rising edge or clock falling edge;
3) making a first data conversion processing;
(1) outputting the data of a first row in the first constant array stored in the first constant array storing unit 3 respectively to the data converting sub-units 200-203 in the first data converting unit 2 in the clock period;
(2) in the same clock period, inputting the data of the output end of the first data registering unit 1 into the first data converting sub-unit 200 for data conversion processing; inputting the data outputted from the first data converting sub-unit 200 into the next data converting sub-unit 201 for data conversion processing; by analogy, until all the data converting sub-units 200-203 in the data converting unit 2 complete the data conversion processings in sequence;
4) making a second data conversion processing;
(1) storing the data of the previous data conversion processing into the first data registering unit 1 at the time of a next clock edge;
(2) inputting the data of the next row in the first constant array stored in the first constant array storing unit 3 respectively to the data converting sub-units 200-203 in the first data converting unit 2 in the clock period;
(3) in the same clock period, inputting the data of the output end of the first data registering unit 1 into the first data converting sub-unit 200 for data conversion processing; inputting the data outputted from the first data converting sub-unit 200 into the next data converting sub-unit 201 for data conversion processing; by analogy, until all the data converting sub-units 200-203 in the data converting unit 2 complete the data conversion processings in sequence;
5) repeating the second data conversion processing;
repeating the second data conversion processing until all the data conversion processing processes specified is completed, thus obtaining a result of the repeating encryption and decryption data processing.
The additional encryption and decryption data processing is used for complementarily implementing the data conversion processing which is not completed by the repeating encryption and decryption data processing, especially in the case that the number of the data converting sub-units included in the first data converting unit 2 is not the divisor of 32, the repeating encryption and decryption data processing and the additional encryption and decryption data processing may be combined for implementing the data conversion processing. Hereinafter, the third to fifth embodiments are illustrated particularly for explaining this.
Referring to
1) preparing a constant array;
(1) arranging data of a second constant array obtained upon key expansion processing in a descending sequence of addresses, and storing into the second constant array storing unit 301;
(2) i) determining the width and depth of the first constant array in the repeating encryption and decryption data processing;
arranging the width and depth based on the number of the data converting sub-units, N, included in the first data converting unit 2 in the repeating encryption and decryption data processing, thereby obtaining the product of the data width and depth of the first constant array in the repeating encryption and decryption data processing;
ii) determining the width and depth of the second constant array in the additional encryption and decryption data processing;
arranging the width and depth based on the number of the data converting sub-units included in the second data converting unit 21 in the additional encryption and decryption data processing, where the data width of the second constant array equals the product of the number of the data converting sub-units, M, in the additional encryption and decryption data processing and 32, and the data depth of the constant array in the additional encryption and decryption data processing is 1;
determining the product of the data width and depth of the second constant array in the additional encryption and decryption data processing as the number of the data converting sub-units in the additional encryption and decryption data processing M×32×1;
iii) the data of the second constant array in the additional encryption and decryption data processing should meet the conditions that,
the sum of the product of the data width and depth of the first constant array in the repeating encryption and decryption data processing and the product of the data width and depth of the second constant array, M×32×1, in the additional encryption and decryption data processing is 1024;
(3) forming the data with a same depth in the first and second constant array as one row;
2) inputting external data into the second data registering unit 101;
(1) inputting the external data to an input end of the second data registering unit 101;
(2) delivering the data from the input end of the second data registering unit 101 to its output end at the clock rising edge or clock falling edge;
3) making an additional data conversion processing;
(1) outputting the data of the second constant array stored in the second constant array storing unit 301 respectively to the data converting sub-units 210, 211 and the like in the second data converting unit 21 in the clock period;
(2) in the same clock period, inputting the data of the output end of the second data registering unit 101 into the first data converting sub-unit 210 for data conversion processing; inputting the data outputted from the first data converting sub-unit 210 into the next data converting sub-unit 211 for data conversion processing; by analogy, until all the data converting sub-units 210, 211 and the like in the second data converting unit 21 complete the data conversion processing in sequence, thereby obtaining the data processing result of the first additional encryption and decryption data processing device 501.
4) using the data processing result from the first additional encryption and decryption data processing device 501 as the external data in the repeating encryption and decryption data processing device 4, thereby completing the repeating encryption and decryption data processing.
Referring to
1) preparing a constant array;
(1) arranging data of a first constant array obtained upon the repeating encryption and decryption data processing in a descending sequence of addresses, and storing into the first constant array storing unit 3;
(2) i) determining the width and depth of the first constant array in the repeating encryption and decryption data processing;
arranging the width and depth based on the number of the data converting sub-units, N, included in the data converting unit 2 in the repeating encryption and decryption data processing, thereby obtaining the product of the data width and depth of the first constant array in the repeating encryption and decryption data processing;
ii) determining the data width and depth of the third constant array in the additional encryption and decryption data processing;
based upon that the data width of the third constant array in the additional encryption and decryption data processing equals the product of the number of the data converting sub-units, Q, in the additional encryption and decryption data processing and 32, and the data depth of the third constant array in the additional encryption and decryption data processing is 1,
determining the product of the data width and depth of the third constant array in the additional encryption and decryption data processing to be Q×32×1;
iii) the data of the third constant array in the additional encryption and decryption data processing should meet the conditions that,
the sum of the product of the data width and depth of the first constant array in the repeating encryption and decryption data processing and the product of the data width and depth of the third constant array, Q×32×1, in the additional encryption and decryption data processing is 1024;
(3) forming the data with a same depth in the constant array as one row;
inputting data obtained from the repeating encryption and decryption data processing device 4 into the third data registering unit 102;
(1) inputting the data obtained from the repeating encryption and decryption data processing device 4 to an input end of the third data registering unit 102;
(2) delivering the data from the input end of the third data registering unit 102 to its output end at the clock rising edge or clock falling edge;
3) making an additional data conversion processing;
(1) outputting the data of the third constant array stored in the third constant array storing unit 302 respectively to the data converting sub-units 222, 221 and the like in the third data converting unit 22 in the clock period;
(2) in the same clock period, inputting the data of the output end of the third data registering unit 102 into the first data converting sub-unit 220 for data conversion processing; inputting the data outputted from the first data converting sub-unit 220 into the next data converting sub-unit 221 for data conversion processing; by analogy, until all the data converting sub-units 220, 221 and the like in the third data converting unit 22 complete the data conversion processing in sequence, thereby obtaining the data processing result of the second additional encryption and decryption data processing device 502.
4) using the data processing result of the second additional encryption and decryption data processing device 502 as the final encryption and decryption data processing result.
The additional encryption and decryption data processing may be performed before or after the repeating encryption and decryption data processing or both.
Referring to
1) preparing a first constant array;
(1) storing the first constant array into a first constant array storing unit 3;
(2) the width of the first constant array being 128 bits, and the depth being 8 since four data converting sub-units are included in the data conversion processing;
(3) dividing the data of the first constant array with the width of 128-bit into 8 rows by the depth of 8 where each row is respectively named as rk0, rk1, rk7; dividing each row of 128-bit data in the first constant array into four data blocks with each being 32-bit, i.e. rk0 being divided into rk0a, rk0b, rk0c and rkod; rk1 being divided into rk1a, rk1b, rk1c and rk1d, and so on.
2) inputting external data to the first data registering unit 1;
(1) inputting the external data to an input end of the first data registering unit 1, where the external data is data of 128 bits, which is divided into 4 data blocks with each including 32 bits and named respectively as A0, A1, A2 and A3;
(2) delivering the data from the input end of the first data registering unit 1 to its output end at the clock rising edge or clock falling edge, where the first data registering unit 1 outputs the 128-bit data which is divided into 4 data blocks with each including 32 bits and named respectively as a0, a1, a2 and a3;
3) making a first data conversion processing;
(1) outputting the data of a first row in the first constant array stored in the first constant array storing unit 3 respectively to the data converting sub-units 200-203 in the clock period;
(2) in the same clock period, inputting the data of the output end of the first data registering unit 1 into the first data converting sub-unit 200 for data conversion processing; inputting the data outputted from the first data converting sub-unit 200 into the next data converting sub-unit 201 for data conversion processing; by analogy, until all the data converting sub-units, i.e. the data converting sub-units 200-203 complete the data conversion processing in sequence; for example, sending the data a0, a1, a2 and a3 from the output end of the first data register unit 1, and the data, rk0a, outputted from the first constant array storing unit 3 to the first data converting sub-unit 200 for data conversion processing, and the data upon the conversion processing are still 128 bits and named respectively as B0, B1, B2 and B3;
sending the data B0, B1, B2 and B3 outputted from the first data converting sub-unit 200, and the data, rk0b, outputted from the first constant array storing unit 3 to the second data converting sub-unit 201 for data conversion processing, and the data upon the conversion processing are still 128 bits and named respectively as C0, C1, C2 and C3;
sending the data C0, C1, C2 and C3 outputted from the second data converting sub-unit 201, and the data, rk0c, outputted from the first constant array storing unit 3 to the third data converting sub-unit 202 for data conversion processing, and the data upon the conversion processing are still 128 bits and named respectively as D0, D1, D2 and D3;
sending the data D0, D1, D2 and D3 outputted from the third data converting sub-unit 202, and the data, rk0d, outputted from the first constant array storing unit 3 to the fourth data converting sub-unit 203 for data conversion processing, and the data upon the conversion processing are still 128 bits and named respectively as E0, E1, E2 and E3;
i.e. E0, E1, E2 and E3 are the resultant data of data conversion processing of the first time;
4) making a second data conversion processing;
(1) storing the data of the previous data conversion processing E0, E1, E2 and E3 into the first data registering unit 1, and inputting the data e0, e1, e2 and e3 from the output end of the first data registering unit 1 to the data converting sub-units 200-203 in sequence at the time of a clock edge;
(2) inputting the data rk1a, rk1b, rk1c and rk1d of the next row in the first constant array stored in the first constant array storing unit 3 respectively to the data converting sub-units 200-203;
(3) making the second conversion processing;
5) repeating the second data conversion processing, thus obtaining the encryption and decryption data processing result.
One data conversion processing period is completed every time the second data conversion processing is made. If the second data conversion processing is repeated for six times, i.e. the data conversion processing is made for 8 times in all, the data outputted upon last data conversion processing is the final data processing result.
If the data conversion data 2 includes 2 data converting sub-units, the repeating encryption and decryption data processing is made for 16 clock periods to complete one encryption and decryption processing; if the data conversion data 2 includes 8 data converting sub-units, the repeating encryption and decryption data processing is made for 4 clock periods to complete one encryption and decryption processing; if the data conversion data 2 includes 16 data converting sub-units, the repeating encryption and decryption data processing is made for 2 clock periods to complete one encryption and decryption processing.
In the method for encryption and decryption processing in SMS4 cryptographic algorithm according to the embodiments of the invention, the repeating times of the data conversion processing is reduced by arranging a constant array and providing a corresponding data converting sub-unit. The efficiency of encryption is improved due to a large increasing of data amount encrypted in unit time. For example, a final data processing result may be outputted by operating for 8 clock periods if 4 data converting sub-units are employed for encrypting 128-bit data. Therefore, in the case of a same clock frequency, the efficiency of encryption is improved by four times.
In the system for encryption and decryption processing in SMS4 cryptographic algorithm according to the embodiments of the invention, on the premise of meeting the required encryption efficiency, the clock frequency is only 1/n of the one in the prior art. For example, the clock frequency in only ¼ of the one in the prior art if 4 data converting sub-units are employed for encrypting 128-bit data.
Further, in the case of the same processing efficiency, the design and implementation of the integrated circuit in the solution of the invention is easier; the integrity of signals is largely optimized and the design cost is reduced. Furthermore, using the integrated circuit designed in the invention, the clock frequency is only 1/n of the one in the prior art in the case of meeting the required encryption efficiency. With the same processing efficiency, the PCB cost may be reduced, and the PCB design and the product are easily achieved; the interference in the system is reduced, and the impacts on other equipments and devices are also decreased largely.
| Number | Date | Country | Kind |
|---|---|---|---|
| 200610041863.9 | Mar 2006 | CN | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/CN07/00617 | 2/27/2007 | WO | 00 | 8/28/2008 |
