Claims
- 1. A computer system comprising:a processor; a main memory coupled to the processor via a host bridge device; a plurality of data drives configured to operate in a fault tolerant mode; and an array controller coupled to said processor and said plurality of data drives, wherein said array controller uses greater than four bit encryption keys to perform encrypted resultant multiplication to calculate data error recovery information written to at least one of the plurality of data drives.
- 2. The computer system as defined in claim 1 wherein said array controller further comprises:a bridge device; an array controller processor coupled to an array controller main memory; an interface circuit coupled to said bridge device by way of an array controller bus, said interface circuit couples to storage devices; an application specific integrated circuit (“ASIC”) coupled to the array controller bus, said ASIC configured to calculate the data error recovery information.
- 3. The computer system as defined in claim 2 wherein said ASIC uses eight bit encryption keys to perform encrypted resultant multiplication to calculate data error recovery information written to at least one of the plurality of data drives.
- 4. The computer system as defined in claim 3 wherein said ASIC uses said eight bit encryption key being at least one key selected from the group consisting of:0x11b0x1630x18d0x1cf0x11d0x1650x19f0x1d70x12b0x1690x1a30x1dd0x12d0x1710x1a90x1e70x1390x1770x1b10x1f30x13f0x17b0x1bd0x1f50x14d0x1870x1c30x1f90x15f0x18b.
- 5. A method comprising:operating a plurality of storage devices implementing multiple device fault tolerance; and calculating error correction information to implement the multiple device fault tolerance using greater than four bit encryption keys.
- 6. The method as defined in claim 5 further comprising calculating error correction information using eight bit encryption keys.
- 7. The method as defined in claim 6 further comprising calculating error correction information using at least one encryption key selected from the group consisting of:0x11b0x1630x18d0x1cf0x11d0x1650x19f0x1d70x12b0x1690x1a30x1dd0x12d0x1710x1a90x1e70x1390x1770x1b10x1f30x13f0x17b0x1bd0x1f50x14d0x1870x1c30x1f90x15f0x18b.
- 8. An array controller comprising:a processor; a main memory coupled to said processor; a bridge device coupled to said processor by way of an array controller bus, said bridge device configured to couple the array controller to a processor of a host computer system; an interface circuit, coupled to a plurality of storage devices; and said array controller implements multiple device fault tolerance using parity information calculated using encryption keys having greater than four bits.
- 9. The array controller as defined in claims 8 further comprising:an application specific integrated circuit (ASIC) coupled to said array controller bus, said ASIC generates the parity information using encryption keys having greater than four bits.
- 10. The array controller as defined in claim 9 wherein said ASIC further generates the parity information using eight bit encryption keys.
- 11. The array controller as defined in claim 10 wherein said ASIC is further uses at least one eight bit encryption key selected from the group consisting of:0x11b0x1630x18d0x1cf0x11d0x1650x19f0x1d70x12b0x1690x1a30x1dd0x12d0x1710x1a90x1e70x1390x1770x1b10x1f30x13f0x17b0x1bd0x1f50x14d0x1870x1c30x1f90x15f0x18b.
- 12. In a computer system having an array of storage devices coupled to an array controller capable of multiple device fault recovery, a method of operating the computer system comprising:writing data from said computer system to said array controller; dividing said data into a plurality of data subsets; calculating error correction information using encryption keys having greater than four bits; and writing said data subsets and error correction information in a striped fashion across an array of storage devices.
- 13. The method as defined in claim 12 further comprising calculating said error correction information in an Application Specific Integrated Circuit (ASIC), said ASIC designed to perform error correction information calculation using encryption keys having greater that four bits.
- 14. The method as defined in claim 13 further comprising calculating error correction information using eight bit encryption keys.
- 15. The method as defined in claim 14 further comprising calculating error correction information using an encryption key selected from the group consisting of:0x11b0x1630x18d0x1cf0x11d0x1650x19f0x1d70x12b0x1690x1a30x1dd0x12d0x1710x1a90x1e70x1390x1770x1b10x1f30x13f0x17b0x1bd0x1f50x14d0x1870x1c30x1f90x15f0x18b.
CROSS-REFERENCE TO RELATED APPLICATIONS
Reference is hereby made to two related disclosures: 1) application Ser. No. 09/576,665 titled “Multiple Drive Failure Recover For A Computer System Having An Array of Storage Drives” now U.S. Pat. No. 6,694,479; and 2) application Ser. No. 09/576,666 titled “Computer System With Greater Than Fifteen Drive Fault Tolerance” now U.S. Pat. No. 6,643,822. Those disclosures are incorporated by reference herein as if reproduced in full below.
US Referenced Citations (10)
Non-Patent Literature Citations (3)
Entry |
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