Patent Application
20140351603
The present invention relates to a block encryption process executed by a microcircuit and protected against side channel attacks, to transform a message into an encrypted message using a secret key.
In particular, the present invention relates to integrated circuit chipcards or the material cryptographic components integrated on computer motherboards or other general public electronic and computing equipment requiring security means (USB keys, television channel decoders, game consoles, etc.), known as “TPM” (Trusted Platform Module).
Such microcircuits are equipped with a CPU (central processing unit) that generally comprises an 8-bit CISC core or an 8, 16, or 32 bit RISC core. Certain microcircuits are equipped with a coprocessor dedicated to cryptographic calculations, for example a DES (Data Encryption Standard) or AES (Advanced Encryption Standard) coprocessor. They comprise thousands of logic gates that switch differently depending on the operations executed. These switchings create measurable short duration, for example only several nanoseconds, current consumption variations. In particular, CMOS technology circuits comprise logic gates that consume current only during their switching, corresponding to being a logic node being set to a 0 or a 1. Thus, the current consumption depends on the data processed by the CPU and by its various peripherals: memory, data traveling on the data or address bus, cryptographic coprocessor, etc.
Such microcircuits are subjected to attacks called side channel attacks, based on a monitoring of their current consumption, their magnetic emissions, or electromagnetic emissions. Such attacks aim to discover the secret data used, in particular the cryptographic keys. The most widely used side channel attacks implement statistical analysis methods such as DPA (“Differential Power Analysis”) or CPA (“Correlation Power Analysis”). DPA allows the key of a cryptographic algorithm to be found thanks to the acquisition of numerous circuit consumption curves. CPA is based on a linear current consumption model and consists of calculating a correlation coefficient between, on one hand, the consumption points measured which form the captured consumption curves, and on the other hand, an estimated consumption value, calculation from the linear consumption model and a hypothesis about the operation executed by the microcircuit and the cryptographic key value.
Countermeasures are generally provided in order to protect such microcircuits and the encryption methods that they perform against such side channel attacks. Masking and multiple-execution are the most commonly implemented countermeasures. A masking countermeasure uses a random mask (binary number) combined with the key and/or the message during the execution of the encryption process. This type of countermeasure is efficient but requires, in the case of execution by a coprocessor, that the coprocessor specially be provided for its implementation, or, in the case of execution by the microcircuit CPU, a more complex program.
A multiple-execution countermeasure may, on the contrary, be implemented with a conventional coprocessor not comprising countermeasure means. It comprises simply executing the encryption process several times with false keys. To this end, a countermeasure program is provided for example. The program controls the encryption program or the coprocessor, and makes it execute the encryption process several times with the false keys, such that the execution of the encryption process with the true key (i.e. the authentic key) is “lost” in a sea of misleading executions.
The present invention relates particularly to multiple-execution countermeasures applied to symmetric type block encryption methods, such as the DES, TDES, and AES processes. These conventional countermeasures will be better understood after a review of the structures of these encryption methods.
Each round RDi (i being considered here as an index from 1 to Nr) generally uses a sub-key SKi derived from the key K or derived from the sub-key used by the preceding round. Each round supplies to the following round an intermediary secret result that is not accessible to an attacker, this result being for example temporarily stored in a protected memory. Thus, the first round RD1 receives the message M or a data issued by the transformation of the message by the initial operation IO as input data, and supplies a first secret intermediary result to the next round RD2. Each intermediary round RDi receives the secret intermediary result supplied by the preceding round as input data, and supplies a secret intermediary result to the next round. The last round receives the secret intermediary result supplied by the next-to-last last round RDNr-1 as input data, and supplies a final result forming the encrypted message C or forming the encrypted message after transformation by the final operation FO.
The number of rounds is predetermined by standards, and is for example equal to 16 in the case of the DES process, 48 in the case of the TDES process, 10 in the case of the AES 128 process, 12 in the case of the AES 192 process, and 14 in the case of the AES 256 process. Similarly, the standards define the structure of the rounds, that is to say, the encryption operations that they comprise. As schematically shown in
As another example,
This solution nevertheless has the inconvenience of penalizing the execution time of the encryption process. The multiple executions of the encryption process CP1 greatly slow down the time to supply the result, even when a rapid processor or coprocessor is provided. Thus, for example when N1=8, the countermeasure requires the execution of 128 rounds for a DES process and 384 rounds for a TDES process. If N1=32, the countermeasure requires the execution of 512 rounds for a DES process and 1536 rounds for a TDES process.
It may therefore be desired to provide an encryption process including a multiple-execution countermeasure that requires less calculation time all while offering a good protection against side channel attacks.
More particularly, embodiments of the invention relate to a symmetric encryption process executed by a microcircuit to transform a message into an encrypted message from a secret key, comprising a first round, intermediary rounds, and a last round, the process further comprising several executions of the first round and of the last round, respectively from the secret key and from a first set of false keys, and a number of executions, of at least one intermediary round less than the number of executions of the first and last rounds, respectively from the secret key and from a set of false keys included in the first set of false keys.
According to one embodiment, the process comprises a second round, a next-to-last round, and several intermediary rounds, wherein the first two rounds are executed a greater number of times than the intermediary rounds, and the last two rounds are executed a greater number of times than the intermediary rounds.
According to one embodiment, the process comprises only one execution of the at least one intermediary round.
According to one embodiment, the process comprises for a determined number of rounds successive from the first, a number of round executions of decreasing according to a decreasing rule that is a function of the rank of rounds considered relative to the first round, then for a determined number of successive rounds until the last, a number of round executions increasing according to an increasing rule that is a function of the rank of rounds considered relative to the last round.
According to one embodiment, the decreasing rule is of 1/(2n), n being a parameter of function of rank of rounds considered relative to the first or to the last round.
According to one embodiment, each round comprises sub-rounds, and wherein the multiple execution of each round comprises the multiple execution of each sub-round of the round.
According to one embodiment, each round comprises sub-rounds, and wherein the multiple execution of a round comprises the multiple execution of at least one sub-round, and a single execution of at least one other sub-round.
According to one embodiment, the single execution of the sub-round is a single or higher order masked execution.
According to one embodiment, the multiple execution of the sub-round is a single order masked execution.
According to one embodiment, the process is in conformance with the DES, triple DES, or AES specifications.
Embodiments of the invention also relate to a microcircuit configured to execute a symmetric encryption process to transform a message into an encrypted message from a secret key, the process comprising a first round, intermediary rounds, and a last round, and the microcircuit is configured to execute several times the first round and the last round, respectively from the secret key and from a first set of false keys, and to execute at least one intermediary round a number of times less than the number of executions of the first and last rounds, respectively from the secret key and from a set of false keys included in the first set of false keys.
According to one embodiment, the microcircuit is configured to execute the at least one intermediary round only once.
According to one embodiment, the microcircuit is configured to execute rounds comprising sub-rounds, and to execute, during a multiple execution of a round, all the sub-rounds of the round the same number of times.
According to one embodiment, the microcircuit is configured to execute rounds comprising sub-rounds, and to execute, during a multiple execution of a round, at least one sub-round only once and to execute another sub-round several times.
According to one embodiment, the microcircuit comprises a modular coprocessor configured to execute individually encryption operations comprised in sub-rounds.
Embodiments of encryption methods and of a microcircuit according to the invention will be described in the following in non-limiting reference to the appended drawings, among which:
Embodiments of the invention are based on the observation that not all rounds of a symmetric encryption process require the same level of protection against side channel attacks. The first and last rounds are the most exposed (i.e. the most vulnerable) to this type of attack, and notably to DPA or CPA attacks. Indeed, DPA or CPA can only be carried out against a round if input or output data of the round is known to the attacker, the key being the object of the attack.
And yet, in reference to
Embodiments of the invention thus relate to an encryption process in which the number of intermediary round RDi (RD2, RD3 . . . RDi, RDNr-1) executions is less than the number of the first round and last round executions, in order to reduce the total number of round executions and to reduce the total execution time of the encryption process. In some embodiments, the second and the next-to-last rounds RD2, RDNr-1 are considered as more exposed to attacks than other intermediary rounds, and are executed a greater number of times than the other intermediary rounds. In yet other embodiments, “central” intermediary rounds (i.e. those that are the farthest from the first and last rounds) are only executed once.
By way of example,
According to the invention, the process CP3 comprises the following steps:
The relation between the number of executions of each round RDi is controlled by a first countermeasure rule, which may be formalized in the following manner, reference being made to rounds RD1, RD2, RD3, RD4 . . . RDi . . . RDNr-3, RDNr-2, RDNr-1, RDNr of which certain are not shown in
In certain embodiments, the distribution of the number of executions may be different for the first and last rounds, for example:
According to an optional second countermeasure rule defining a sort of process “symmetry” with respect to the central rounds, the number of executions of the last round is equal to the number of executions of the first round, the number of executions of the second round is equal to the number of executions of the next to last round, and so forth until a certain “distance” from the first and last rounds. This rule may be formalized in the following manner.
If i<ls, then Ni=NNr-i+1,
ls being a threshold defining the “distance” of a round relative to the first and last rounds.
The threshold ls may be chosen to be greater than the number of rounds to obtain a total symmetry of the process as far as the number of round executions relative to the central rounds is concerned.
According to an optional third countermeasure rule “rule 3”, the execution of certain intermediary rounds is not repeated, in particular for the central rounds. For the implementation of this rule, a number of rounds to protect “NRtoP” is defined, relative to the first and to the last round. The number of rounds to protect represents the number of rounds that need to be executed several times. The rounds that do not belong to the group of rounds to protect are considered as “central” rounds and are only executed once, with the true key K0 (i.e. the authentic key). Rule 3 may be formalized as follows.
Numerical example in the case of an encryption process comprising 16 rounds RD1 to RD16 (Nr=16)
In this case, the rounds RD4, RD5, RD6, RD7, RD5, RD9, RD10, RD11, RD12, RD13 are only executed once.
In certain embodiments, the number of executions Ni of each round RDi (for i from 1 to Nr) may be determined by means of a relation which is a function of the rank i of the considered round. Rule 4 below is an example of a relation 1/(2n), n being a variable function of i. Rule 4 includes rule 2 as far as the rounds to protect are considered and includes rule 3 as far as the rounds not to protect are considered.
Rule 4 may be formulated more simply by means of the minimum operator “min”:
Reference is now made to Annex 1, an integral part of the description. Table 1 of Annex 1 describes a numerical application example of rule 4, with Nr=16 and NRtoP=3. If N1=8, it follows that: N2=4, N3=2, N4 to N13=1, N14=2, N15=4 and N16=8. If N1=16, it follows that N2=8, N3=4, N4 to N13=1, N14=4, N15=8 and N16=16.
Table 2 of Annex 1 describes embodiments CP31, CP32, CP33, CP34, CP35, CP36 of the encryption process CP3 implementing rules 1 and 2. These embodiments relate to an encryption process comprising 16 rounds (Nr=16), for example the DES process. The maximum execution number N1 is equal to 8 for the embodiments CP31 to CP34, CP36, and is equal to 12 for the embodiment CP35. The embodiment designated by the reference CP30 does not implement rule 1 and is not considered as comprised in the invention because it does not provide any advantages as far as calculation time is considered. It represents the number of round executions that a conventional countermeasure would need comprising 8 successive executions of the encryption process, which would require 8*16, that is 128 round executions.
In table 2, column T provides the total number of round executions, column CT gives the calculation time for each embodiment CP31 to CP36 as a percentage of the calculation time of embodiment CP30, that is, relative calculation time. This relative calculation time CT is equal to the total number of execution of rounds divided by the total number of executions of rounds in the case embodiment CP30, that is (T/128)*100. Column G or “Time gained” is the 100 complement of the relative calculation time CT, that is, G=100−CT.
Embodiments CP34, CP35, CP36 also implement rule 3 (no multiple execution of certain central rounds) and embodiment CP36 also implements rule 4 with NRtoP=3 and Nr=8. These examples show that the time gain depends on both the distribution of the number of intermediary rounds executions and on the maximum number of executions of the first and of the last round. For example, embodiment CP35 in which N1=12 offers a time gain of 55% greater than the time gain of 44% offered by the embodiment CP33 in which N1=8, because rounds 6 to 11 are only executed once.
In an implementation variation, rule 3 is modified such that the number of executions of “central” rounds is fixed but greater than 1, which corresponds for example to embodiments CP31 and CP32 where the central rounds are executed twice.
As another example, table 3 on page 1 of Annex 1 describes the total T number of rounds executions as a function of the number of rounds Nr as well as the relative calculation time CT (relative to embodiment CP30) when rule 4 is used to determine the number of executions, and when the number of rounds to protect NRtoP is equal to 4.
Still to illustrate the advantages of a countermeasure process according to the invention,
Reference is now made to Annex 2, an integral part of the description, which describes, in the form of executable algorithms, implementation examples of encryption methods protected according to the invention. The sub-round operations that each encryption process executes are set forth in tables 4 and 5 of Annex 1.
The encryption process is executed by means of a “Protected DES” algorithm PDES1 and of a “Protected Round DES” algorithm PRDES1 or round algorithm. The round algorithm PRDES1 is a sub-function of the algorithm PDES1, and is called by algorithm PDES1 at each new iteration of the variable i, which forms a round number.
In the PDES1 algorithm, the permutation operations IP, inverse permutation operations IPinverse, and dividing the message in two 32-bit blocks bits executed at steps 3, 4, 8 are known to the skilled person and will not described in detail here. A first pair of values (L0, R0) is calculated at step 4 from the message M after its permutation at step 3. The values are for the execution of the first round by the algorithm PRDES1. Then, steps 5, 6, 6.1, 6.2, 7, and 7.1 implement rule 4 described above, and thus determine the number of executions of a round as a function of its rank and of the parameter NRtoP. Steps 6.3 and 7.2 are calls to the round function executed by the algorithm PRDES1.
In the algorithm PRDES1, the cryptographic tables C, D, E, F (in practice, binary chains), the random permutation operations, the generation of sub-keys, the concatenation operator “I”, as well as the sub-round operations described in table 4 of Annex 1 (expansive permutation, substitution, XOR, permutation) are also known to the skilled person. The sub-rounds 1 to 4 are included in the loop 13 and are thus each repeated as many times as the number of iterations of the variable j. Variable j has N1 values determined by the algorithm PDES1. When algorithm PRDES1 has been called by the algorithm PDES1 with N1=1 (steps 7.1 and 7.2), the loop 13 only comprises one value of j. The sub-rounds are therefore only executed once with the sub-key corresponding to the true key K0.
The random permutation executed at step 12 allows the selection of the Ni first sub-keys of the set of sub-keys SKi,0 to SKi,N1-1 to form a set of sub-keys SKi,p0 to SKi,pj for j from 0 to Ni−1, pj being an element of rank j in the random permutation P. When Ni=N1, all the sub-keys are used. When Ni=1, only the true sub-key SKi,0 is used (i.e. the sub-key corresponding to the true key K0). This random permutation also allows the sub-keys to be classed in a random order for the execution of the loop 13. Thus, the first sub-key used for the first iteration (j=0) of the loop 13 is not necessarily the sub-key SKi,0. At each new execution of algorithm PRDES1, the usage order of the sub-keys is random.
Once the round has been repeated Ni times, algorithm PRDES1 sends back the pair of values (Li, Ri) which are a function of the pair of values initially received on input (Li-1, Ri-1), the number i of the round (which determines the values of the sub-keys), and the execution number Ni of the round.
In the algorithm PRDES1, the generation of sub-keys, from keys K0 to KNi-1 or from sub-keys of a preceding round, required for the execution of each round may be done in several ways:
The second solution presented has been retained here and appears at step 11. In step 11, N1 sub-keys are generated for each round from N1 keys or N1 sub-keys generated during the execution of the preceding round. The number of sub-keys generated is independent of the number of executions of the considered round and is thus the number of sub-keys actually required by the algorithm PRDES1 for the execution of the round.
It will be noted that in the case of the DES process, known methods of generating fake keys allow the generation of sub-keys for all the fake keys from sub-keys of the authentic key. Thus, instead of generating the sub-keys of a fake key from preceding sub-keys of the same false key, the sub-keys of the false key may also be generated from sub-keys of the authentic key. In the case of the AES process, the sub-keys of a false key must however be generated from precedent sub-keys of the false key.
It will clearly appear to the skilled person that various other algorithms implementing the principles of the invention may be provided to execute the DES process, since algorithms PDES1 and PRDES1 are only examples.
The encryption process according to the invention is here executed by means of a PTDES (“Protected TDES”) algorithm appearing in Annex 2 and algorithms PDES1 and PRDES1 described above.
The TDES encryption conventionally comprises a first step of DES encryption of the message with a first key K, i.e. DES(M,K). A step of DES−1 inverted encryption of the result of the first step with a second key K′ is then performed, i.e. DES−1(DES(M,K),K′). Finally, a DES encryption step is performed of the result of the second step with the first key K, as follows:
In the PTDES algorithm, the first DES encryption step (step 20) is executed by calling algorithm PDES1, which then calls algorithm PRDES1, after having defined the maximum number N1 of rounds executions and the number of rounds to protect NRtoP.
The second DES−1 encryption step may be executed by means of a conventional DES−1 process unprotected from side channel attacks (step 21a), or by means of the algorithm PDES1−1, the inverse PDES1 algorithm described in Annex 2 (step 21b). Algorithm PDES1−1 is not described in Annex 2 but may be derived from the PDES1 algorithm by replacing the operation IP of step 3 by the operation IPinverse, and by replacing the operation IPinverse of step 8 by the operation IP, and by inverting the usage order of the sub-keys (that is, from SK16 to SK1). As step 21b provides that N1=1 and NRtoP=0, algorithm PDES1−1 is unprotected and is equivalent to a conventional DES−1 process.
Finally, the last DES encryption step (step 22) is protected and is executed by calling algorithm PDES1 which then calls algorithm PRDES1, by defining the maximum number N1 of round executions and the number of rounds to protect NRtoP.
The example described in Annex 2 relates to AES 128 of 10 rounds but the invention may also be applied to AES 192 of 12 rounds and to AES 256 of 14 rounds.
The process is executed by means of an algorithm PAES1 (“Protected AES”) and an algorithm PRAES1 (“Protected Round AES”) or round algorithm. Algorithm PRAES1 is a sub-function of algorithm PAES1 which is called by this latter at each new iteration of round number i.
In algorithm PAES1, steps 33, 34, 34.1, 34.2, 35, 35.1 implement rule 4 described above, and thus determine the number of executions of a round as a function of its rank and of the parameter NRtoP. Steps 34.3 and 35.2 are calls to the round function executed by algorithm PRAES1.
Algorithm PRAES1 executes the sub-round operations described in table 5 in Annex 1 (AddRoundKey, SubByte, ShiftRow, and MixColumn), in and of themselves known to the skilled person. The structure of rounds executed by algorithm PRAES1 is shown in
In algorithm PRAES1, the sub-rounds AddRoundKey, SubByte, and ShiftRow are included in the iterative loop 43 and are thus each repeated as many times as the number of iterations of the variable j. The operation MixColumn is equally included in la loop 43 for all values of round number i different than 10. Loop 43.6 is executed when i is equal to 10 and is included in loop 43 only for round 10. It comprises a new generation of sub-keys (step 43.6.1) and the second execution of the operation AddRoundKey (step 43.6.2).
As previously, the random permutation operation executed at step 42 allows the selection of the Ni first sub-keys of the set of sub-keys SKi,0 to SKi,N1-1 to form a set of sub-keys SKi,p0 to SKi,pj for j from 0 to Ni−1. When Ni=N1, all the sub-keys are used. When Ni=1, only the true sub-key SKi,0 is used (i.e. the sub-key corresponding to the true key K0). This random permutation operation also allows the sub-keys to be classed in a random order for the execution of the loop 43.
It will be understood by the skilled person that various other algorithms implementing the principles of the invention may also be provided to execute the AES process.
In embodiments of the invention based on the notion of modularity, the multiple execution of a round comprises:
The previously described rules, relating to the determination of the number of executions of each round, are conserved. However, the way in which each round is executed several times is modified. In other words, each sub-round, and more particularly, each encryption operation that comprises each sub-round, is considered as a “module” having its own number of executions.
As an example,
This embodiment allows the execution time of the encryption process to be further accelerated by limiting, within rounds executed several times, the number of sub-rounds that are themselves executed several times. It may comprise the provision of several independent hardware functions or “material modules”, each executing a sub-round or a sub-round operation, instead of and in place of a single hardware round function comprising all the sub-rounds.
This modularity allows, on one hand, to multiply the sub-function calls during a round and to vary the number of these calls as a function of the round currently performed, but also to define sub-functions useable for several encryption methods. In other words, instead of providing a coprocessor dedicated to a determined encryption process, embodiments of the invention provide several hardware accelerators useable by several encryption processes, each one implementing a sub-round operation. Thus, in the example shown in
By precaution, a countermeasure may be provided to protect the sub-rounds that are only executed once against side channel attacks. This countermeasure may in particular be a masking countermeasure. Thus, in
The choice of a sub-round protection mode, by masking or by multiple executions, may be made as a function of the nature of the operation that comprises the sub-round. To this end, the sub-rounds that comprise a linear operation and those that comprise a non-linear operation in the mathematical sense of the term are distinguished. In particular, an operation is non linear when its execution is based on a determined tabled stored in memory.
Masking example of a linear operation:
The protected operation produces the same result as the unprotected operation.
Masking example with a non-linear operation “S”:
A DPA or CPA attack knowing M may allow the key K to be found by predicting the value S(Xi).
As previously, the protected operation produces the same results as the unprotected operation.
Because the masking of a table with a plurality of mask requires a large memory space, a masking countermeasure has the inconvenience of occupying a large memory space in the case of a non-linear operation. Thus, to reduce the memory space used, the same mask, for example a mask of 8 bits, is generally used for all sub-rounds of the round or for all the values of the table. The masking is therefore called “single order” as opposed to a higher order masking, which uses a plurality of random masks.
Nevertheless, single order masking introduces a weakness against attacks by higher-order DPA. However, if the non-linear masked single order operation is executed several times with false keys, the “true” operation will be lost in a sea of false operations and the result of an attack will be comparable to noise. Certain embodiments of the invention thus provide multiple executions of non-linear masked single order operations. In this case, and advantageously, it is not necessary to provide a higher order mask because it is almost impossible, with the current body of knowledge, to carry out a higher order attack on an operation executed several times with a single order masking.
In summary, in certain embodiments, the linear operations are protected by multiple executions, or by a higher order masking, or else by a single order masking and multiple executions, whereas the non-linear operations are preferably protected by a single order masking and multiple executions.
Thus, in the process CP4 shown in
Countermeasure 4 offers a higher level of security than those offered by countermeasures 2 and 3, which offer higher levels of security that that offered by countermeasure 1. Nevertheless, searching for a better ratio between execution time and protection against attacks, countermeasures 2 and 3 already offer an excellent level of protection. Furthermore, one can add random executions within these operations.
Reference is now made to Annex 3, an integral part of the description, which describes, in the form of executable algorithms, realization examples of encryption methods protected according to the invention, implementing the notion of modularity.
The process is executed by means of an algorithm PDES2 and of a round algorithm PRDES2 appearing in Annex 3. Algorithm PDES2 differs from algorithm PDES1 in that it comprises initial steps 54, 55 of generating a first mask U0 and of generating left and right parts U0,L and U0,R of the mask, followed by a step 56 of masking left and right parts L0, R0 of the message M. Further, step 6.3 to call algorithm PRDES1 is replaced by a step 58.3 to call algorithm PRDES2, and step 7.2 to call algorithm PRDES1 is replaced by a step 59.2 to call algorithm PRDES2. Finally, when all the rounds have been executed by means of algorithm PRDES2, a step 60 of demasking the result is provided. The operation IPinverse then allows the encrypted message C to be obtained.
Round algorithm PRDES2 uses the same encryption operations and comprises the same sub-rounds as algorithm PRDES1, but implements the notion of modularity. It receives as Input Data, as previously:
Round algorithm PRDES2 also receives, as input data, a random mask Ui-1. The random mask is the mask U0 generated by algorithm PDES2 at step 54, or a mask Ui-1 provided by the preceding execution of algorithm PRDES2, calculated at step 78.
Sub-round 1 comprises the linear Expansive Permutation operation and is only executed once at step 75 with a higher order masking. Sub-round 2, arranged in the iterative loop 76, comprises the linear XOR operation and is executed several times at step 76.1 with a higher order masking. Sub-round 3 comprises the non linear Substitution operation, also present in loop 76, and is executed several times at step 76.3 in unmasked form, as it is preceded by a demasking step 76.2. The result of this operation is then masked again at step 76.4. Finally, sub-round 4, which comprises the linear XOR operation, is only executed once with a higher order masking at step 77. A mask Ui of rank i for the next round is then calculated at step 78 and an update of mask Ui-1 is performed at step 79. The algorithm then returns the result Li, Ri and the mask Ui.
It will be understood by the skilled person that various other algorithms implementing the principles of the invention may be provided to execute the DES process.
The process is executed by means of an algorithm PAES2 and of a round algorithm PRAES2 appearing in Annex 3. Algorithm PAES2 differs from algorithm PAES1 in that it comprises a step 92 of generating an initial random mask Uo and a step 93 of masking message M. Step 34.3 to call algorithm PRAES1 is replaced by a step 95.3 to call algorithm PRAES2 and the step 35.2 to call algorithm PRAES1 is replaced by a step 96.2 to call algorithm PRAES2. When all the rounds have been executed, the final result C is unmasked at step 97 to obtain the encrypted message C.
Round algorithm PRAES2 uses the same encryption operations and comprises the same sub-rounds as algorithm PRAES1, but implement the notion of modularity.
Thus, in algorithm PRAES2, sub-round 1 comprising the linear AddRoundKey operation (step 104.1) is included in the iterative loop 104 and is executed several times with a higher order masking. Sub-round 2 comprising the non linear SubByte operation (step 104.3) is executed several times in the unmasked form, after a demasking step 104.2. The result of this sub-round is then masked again at step 104.4. Sub-round 3 comprising the linear ShiftRow operation is not within the loop 104 and is only executed once at step 105, with a higher order masking. Sub-round 4, comprising the linear MixColumn operation (step 106.1), of rounds 1 to 9 is also not within the loop 104 and is only executed once, with a higher order masking. Sub-round 4, comprising the linear AddRoundKey operation, of round 10 (step 107.3.1) is executed several times with a higher order masking within the loop 107, after a new generation of sub-keys (step 107.1) and step of updating the mask (step 107.2).
It will clearly appear to the skilled person that various other algorithms implementing the principles of the invention may be provided to execute the AES process.
The invention applies in a general manner to all types of symmetric block encryption processes comprising rounds. Embodiments of the invention based on the modularity notion may be applied to all processes of this type in which each round comprises a plurality of sub-rounds.
Embodiments of an encryption process according to the invention may implement only the second aspect of the invention relating to the modularity of sub-rounds, without the first aspect of the invention providing a variable number of executions of rounds as functions of their rank. Such embodiments may therefore comprise an identical number of executions of each round, but a different number of executions of each sub-round within a round executed several times, certain sub-rounds being executed only once, preferably in masked form, and other sub-rounds being executed several times, in masked or unmasked form.
A microcircuit configured to execute a process according to the invention is itself susceptible to various embodiments. For example, the algorithms appearing in Annex 2 and Annex 3 may be executed by the CPU of the principal processor or partly by the CPU and by a coprocessor. In particular, the algorithms PDES1, PDES2, PTDES, PAES1, PAES2 may be executed by the CPU and the rounds algorithms PRDES1, PRDES2, PRAES1, PRAES2 may be executed by a coprocessor or by hardware accelerators. Algorithms PRDES2 and PRAES2 based on the modularity principle may advantageously be executed by a modular coprocessor or several hardware accelerators in parallel forming the equivalent of a modular coprocessor, allowing the CPU to call each sub-round function independently of the others, with or without masking, for a single or multiple execution of these functions.
Circuit ICCT may be of the contact type (wired communication port), of the contactless type (NFC, Wifi, Bluetooth®, etc. interface), or of both types. In certain applications, in particular in the framework of an authentication process of the device SDV, the message to encrypt M is received by the intermediary of the communication interface circuit ICCT and the encrypted message C is communicated to the exterior also by the intermediary of this interface circuit.
Memory MEM1 may comprise a volatile memory zone and an electrically programmable non volatile memory zone. The non volatile memory may comprise a secure zone comprising a secret key K. The random or pseudo-random generator RGEN is used by the processor or the coprocessor to generate the false keys and/or random masks of the type described above. The coprocessor may be dedicated to the execution of rounds of a determined encryption, or be of the modular type as described above, for the execution of hardware functions allowing the processor to execute each sub-round independently of the others.
| Number | Date | Country | Kind |
|---|---|---|---|
| 12 50272 | Jan 2012 | FR | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/FR2012/000546 | 12/21/2012 | WO | 00 | 7/8/2014 |
