Encryption processing method and encryption processing device

Abstract

An increase in safety from attacks by use of hardware-like methods by small-sized hardware is achieved. An encryption processing device includes a logical circuit capable of programmably setting logics for executing cipher processing, a memory that stores plural pieces of logical configuration information corresponding to an identical cipher processing algorithm, and a CPU that selectively sets plural logics corresponding to an identical cipher processing algorithm in the logical circuit. Even in processing using an identical cipher key, by changing the logic of the logical circuit for each processing, power consumption in cipher processing can be varied, and places a timing in which malfunctions occur can be varied. Moreover, an increase in the scale of hardware for realizing plural logics can be curbed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an encryption processing device according to the present invention;

FIG. 2 is a drawing for explaining Sbox definition, which is a part of the algorithm of AES handled in the encryption processing device;

FIG. 3 is a block diagram showing a communication system including the encryption processing device;

FIG. 4 is a drawing for explaining a procedure when a communication device included in a communication system shown in FIG. 3 receives encrypted information;

FIG. 5 is a drawing for explaining a logical configuration example realized based on logical configuration information in a reconfigurable logical circuit included in the encryption processing device;

FIG. 6 is another drawing for explaining a logical configuration example realized based on logical configuration information in a reconfigurable logical circuit included in the encryption processing device;

FIG. 7 is another drawing for explaining a logical configuration example realized based on logical configuration information in a reconfigurable logical circuit included in the encryption processing device;

FIG. 8 is another drawing for explaining a logical configuration example realized based on logical configuration information in a reconfigurable logical circuit included in the encryption processing device;

FIG. 9 is another drawing for explaining a logical configuration example realized based on logical configuration information in a reconfigurable logical circuit included in the encryption processing device;

FIG. 10 is another drawing for explaining a logical configuration example realized based on logical configuration information in a reconfigurable logical circuit included in the encryption processing device; and

FIG. 11 is a drawing for explaining an inverse calculation correspondence table usable in the encryption processing device.

Claims

1. A cipher processor, comprising: a logical circuit capable of programmably reconfiguring plural logic configurations for executing cipher processing;a plurality of algorithmically identical cipher processing portions, wherein each of said plurality of algorithmically identical cipher processing portions is respectively corresponded to each of said plural logic configurations;wherein one of said plural logic configurations is selectively reconfigured to a second of said plural logic configurations by said logical circuit.

2. The cipher processing method according to claim 1, wherein, before cipher processing is performed in the logical circuit, the selected one of the plural logic configurations corresponding to an algorithmically identical cipher processing algorithm is selectively reconfigured based on at least one of a cipher processing procedure in the logical circuit, execution timing of the cipher processing in the logical circuit, and logical configuration information regarding differences in power consumptions involved in the cipher processing.

3. An encryption processing device comprising: a logical circuit capable of programmably reconfiguring to ones of a plurality of logic sets, wherein each of said logic sets executes an identical cipher processing; anda CPU that selectively directs the logical circuit to reconfigure to ones of the logic sets corresponding to the identical cipher processing.

4. An encryption processing device comprising: a logical circuit capable of programmably setting to a plurality of logics for executing cipher processing;a memory that stores a plurality of logical configurations correspondent to ones of the plurality of logics, each corresponding to one identical cipher processing; anda CPU that manages a selective setting by the logical circuit to ones of the plurality of logics for performance of the identical cipher processing based one of the logical configurations in the memory.

5. The encryption processing device according to claim 4, wherein, before the cipher processing is performed, the CPU selectively sets the plurality of logics to one logic that is algorithmically identical to a previous one of the logics.

6. The encryption processing device according to claim 4, wherein, before the cipher processing is performed in the logical circuit, the CPU selectively sets the plurality of logics based on at least one of a cipher processing procedure in the logical circuit, execution timing of the cipher processing in the logical circuit, and the logical configurations regarding differences in power consumptions for the cipher processing.

7. The encryption processing device according to claim 4, wherein the logical configurations include configuration information obtained by arithmetic processing by the CPU.

8. The encryption processing device according to claim 4, wherein at least one of the logical configurations is encrypted before being stored in the memory.

9. The encryption processing device according to claim 4, wherein the memory is a nonvolatile memory.

10. The encryption processing device according to claim 4, wherein the logical circuit is constructed by one of FPGA and PLD.

11. The encryption processing device of claim 4, wherein the setting to ones of the plurality of logics modifies power consumption such that communication security is increased over other available ones of the plurality of logics.

12. The encryption processing device of claim 4, wherein the setting to ones of the plurality of logics modifies malfunction analysis such that communication security is increased over other available ones of the plurality of logics.