Patent Application
20240405970
The present invention relates generally to encryption systems, and specifically to an encryption system for a constrained environment.
Encryption technology has existed for hundreds of years to encode information in documents to obfuscate the content of such encoded documents from adverse parties. In more recent decades, wireless and computer data is encoded by encryption methods to prohibit access to wireless communications and software files by adverse parties. One such manner of encryption is defined in a number of encryption standards, such as Advanced Encryption Standard (AES) as detailed in Federal Information Processing Standards (FIPS) Publication 197. The AES encryption methodology describes a number of different encryption methodologies that provide increasingly greater encryption capability based on having increasingly longer key lengths (e.g., AES-256 over AES-192, and AES-192 over AES-128). As encryption technology has advanced, more complicated encryption may be required to provide for greater security to mitigate decryption by adverse parties. However, the circuitry required for more advanced encryption algorithms can be more complicated, can be larger in size, and can require more power than simpler encryption algorithms.
One example includes a security device system. The system includes a constrained environment housing and operational components configured to implement a security function. The system further includes an integrated circuit (IC) configured to implement a 256-bit Advanced Encryption Standard (AES-256) encryption algorithm, the IC comprising fewer than 5,000 gate equivalents and operating at a power of less than 1.5 microwatts to be accommodated in the constrained environment housing.
Another example includes a non-transitory computer readable medium comprising machine-readable instructions. The machine-readable instructions can be executed to generate a State module in a hardware description language (HDL) code. The State module can be configured to store an encryption state. The instructions can also be executed to generate a RoundKey module in the HDL code. The RoundKey module can be configured to store an original encryption key for a 256-bit Advanced Encryption Standard (AES-256) encryption algorithm. The instructions can also be executed to generate a KeyExpansion module in the HDL code. The KeyExpansion module can be configured to implement an iterative key expansion operation in which the original encryption key is expanded to generate an encryption subkey of a key schedule in each of a plurality of iterations having a quantity defined by the AES-256 encryption algorithm. The instructions can also be executed to generate an AddRoundKey module in the HDL code. The AddRoundKey module can be configured to combine an encryption round key corresponding to one of the original encryption key and the encryption subkey of one of the iterations with the encryption state to modify the encryption state in each of the iterations. The instructions can further be executed to synthesize the HDL code to generate an integrated circuit (IC) design based on the HDL code, and to fabricate an IC based on the HDL code.
Another example includes a radio frequency identification (RFID) tag system. The system includes a transponder configured to wirelessly communicate with an RFID reader via wireless signals and a memory configured to store sensitive data. The system further includes an integrated circuit (IC) configured to implement a 256-bit Advanced Encryption Standard (AES-256) encryption algorithm configured to encrypt the sensitive data.
The present invention relates generally to encryption systems, and specifically to an encryption system for a constrained environment. The encryption system described herein can correspond to a 256-bit Advanced Encryption Standard (AES-256) encryption algorithm that operates in compliance with the Federal Information Processing Standards Publication 197 AES (FIPS PUB 197). The AES-256 encryption algorithm can be implemented on an integrated circuit (IC), such as an application specific integrated circuit (ASIC) or field-programmable gate array (FPGA) in a constrained environment. As described herein, the term “constrained environment” refers to an environment that can accommodate the IC in a limited three-dimensional space and/or with limited power. For example, the design of the AES-256 encryption algorithm can be implemented (e.g., in Verilog) and synthesized (e.g., in Synplify Pro S-2021.09 for a Xilinx Spartan7 XC7S25 FPGA) to provide a circuit that occupies 820 lookup tables (LUTs). As is known in the art, a single LUT can be equivalent to a quantity of six two-input NAND gates. Therefore, the synthesis for an ASIC that implements the AES-256 encryption algorithm described herein results in a circuit that is less than approximately 5,000 gate equivalents (GEs), which can consume approximately a single microwatt (u W) of power. Therefore, as described herein, the IC on which the AES-256 encryption algorithm operates can be fabricated to have fewer than approximately 5,000 GEs and can consume less than 1.5 u W of power to be able to be accommodated in the constrained environment described herein, while still operating in compliance with FIPS PUB 197.
As an example, the security device described herein that can accommodate the IC that implements the AES-256 encryption algorithm in a constrained environment can be a radio frequency identification (RFID) tag. However, other examples of a constrained environment can include a wireless device that implements a Wi-Fi Protected Access 3 (WPA3) security protocol that may require the AES-256 encryption algorithm, Edge Computing and/or Security Networking that may require the AES-256 encryption algorithm, Near-field Communication (NFC) devices that may be designed in a small and power efficient form-factor, compact application of Internet of Things (IoT), or any of a variety of other devices that may be require a small form-factor design and/or a very low power consumption.
The IC can be fabricated from a hardware description language (HDL) code, such as Verilog. The IC can be designed based on inputs to the HDL code, which can then be synthesized to generate the IC design for fabrication using any of a variety of IC fabrication tools. As described herein, the AES-256 encryption algorithm can be implemented based on improvements to the modules therein to achieve significant reduction in the GEs, power consumption, and clock cycles. The reduction in size resulting from the reduction in GEs, as well as the increase in power efficiency and clock cycles can allow for the IC to operate the AES-256 encryption algorithm with improved size, weight, and power (SWaP) over conventional circuits that implement an AES-256 encryption algorithm. Therefore, the IC configured as an ASIC or an FPGA can implement the AES-256 encryption algorithm in a compact form-factor that enables use in the constrained environment (e.g., an RFID tag). As an example, the improvements to the modules can include the use of same circuits for different functions, such as for column mixing of the encryption state and key expansion of the original key, as described in greater detail herein.
To be accommodated in the constrained environment housing 104, the IC 102 can be fabricated to have fewer than approximately 5,000 gate equivalents (GEs) and can consume less than 1.5 μW of power while still being able to implement the AES-256 encryption algorithm. For example, some highly secure locations or applications may require a greater level of security encryption/decryption than is possible with other encryption algorithms, such as AES-128 or AES-192. Such lesser encryption algorithms that have a more limited level of security capability may be able to be accommodated in smaller convenient packages. However, to achieve sufficient security requirements, more applications require the more complex encryption/decryption capability of the AES-256 encryption algorithm, which is typically operated on a large circuit and with greater power consumption to be able to accommodate the significantly greater processing that is required for implementing the AES-256 encryption algorithm. However, as described herein, the IC 102 can be designed to operate the AES-256 encryption algorithm in a constrained environment, unlike conventional AES-256 encryption algorithm circuits, and thus within the constrained environment housing 104.
In the example of
The AES-256 encryption algorithm 200 includes a State module 202 that is configured to store an encryption state 204. The encryption state 204 can initially be provided as an input to the State module 202 as either a plaintext input (“P_TXT”) for encryption or a ciphertext input (“C_TXT”) for decryption. The encryption state 204 is thus modified responsive to operation of the AES-256 encryption algorithm 200 and output from the State module 202, and thus from the corresponding IC 102, as a signal CODE. As described herein, the term “signal”, as applied to the communication to, from, or between modules of the AES-256 encryption algorithm 200, can refer to a set of bits in a register. Thus, the set of bits in a register corresponding to a “signal” are provided from a register or accessed by another register via the modules of the AES-256 encryption algorithm 200. The modified encryption state 204 can thus be output as the signal CODE corresponding to a ciphertext code in response to an encryption procedure, or to a plaintext code in response to a decryption procedure. As an example, the State module 202 can be implemented as a 128-bit register that stores the encryption state 204. The register can be arranged in a matrix of four rows and four columns of bytes, such as defined by the Federal Information Processing Standards (FIPS) Publication 197.
The encryption state 204 is accessed from the State module 202, demonstrated as a signal ST, by a SubRows module 206. The SubRows module 206 is demonstrated in the example of
By combining the operations of the SubBytes and ShiftRows operations, the SubRows module 206 applies an S-Box transformation to each byte of the encryption state 204 via the first S-Box 208 and shifts the respective transformed byte a number of bytes based on the row index. As described herein, the first S-Box 208 includes both forward operation circuitry for an encryption procedure and inverse operation circuitry for a decryption procedure. The SubRows module 206 can thus output a modified encryption state, demonstrated in the example of
The encryption state 204 (e.g., the next encryption state corresponding to the modified encryption state SR_ST) is also accessed from the State module 202, demonstrated as the signal ST, by a MixColumn module 210. The MixColumn module 210 is configured to perform a mathematical transformation of each column of the encryption state 204. The mathematical transformation can be implemented in a MixColumn operation for encryption and in an inverse MixColumn operation for decryption. The MixColumn operation and inverse MixColumn operation are implemented as bit-wise shifts of the column(s) of the encryption state in combination with exclusive-OR (XOR) logic operations. For example, the MixColumn operation can be performed as a Galois Field (GF) matrix multiplication (e.g., GF (28)) with a given one of the columns of the encryption state 204 in a given iteration. At each iteration, the MixColumn module 210 outputs the transformed encryption state, demonstrated as a signal ST_MX. As described in greater detail herein, the MixColumn module 210 can be programmed in the HDL code to provide for a significant reduction in complexity, and therefore a significant reduction in GEs.
The MixColumn module 300 includes a MixColumn operational circuit 302 and an inverse enable circuit 304. The MixColumn operational circuit 302 is demonstrated as receiving the encryption state (e.g., the encryption state 204) in an encryption procedure, demonstrated as a signal ST_EN, or in a decryption procedure, demonstrated as a signal ST_DE. The MixColumn operational circuit 302 is demonstrated as providing the transformed encryption state ST_MX as an output. Therefore, the MixColumn operational circuit 302 is configured to provide the MixColumn operation on the encryption state 204 as either the state ST_EN for an encryption procedure or the state ST_DE in a decryption procedure. Therefore, the MixColumn operational circuit 302 provides the same MixColumn function for both encryption and decryption. In other words, the same circuit (e.g., the MixColumn operational circuit 302) is used for the encryption state 204 in both encryption and decryption procedures, as opposed to two separate dedicated circuits for the encryption procedure and the decryption procedure, respectively.
The inverse enable circuit 304 is demonstrated as receiving a mode input MODE that can correspond to a toggle between the encryption and decryption procedures. The inverse enable circuit 304 can thus operate in cooperation with the MixColumn operational circuit 302 to provide the MixColumn operation for a decryption procedure using the same circuitry that is used for an encryption procedure. The inverse enable circuit 304 can be configured as only a small addition to the complexity of the MixColumn module 300, and thus provides only a nominal addition to the GEs of the MixColumn operational circuit 302. With the addition of the inverse enable circuit 304, by implementing the MixColumn operational circuit 302 as a single circuit for both encryption and decryption procedures, as opposed to two separate dedicated circuits for encryption and decryption procedures, respectively, the MixColumn module 300 can be significantly more simplified, and thus arranged in a much more compact manner (e.g., with fewer GEs) than a typical MixColumn module in a conventional AES-256 encryption algorithm.
As described above, the encryption state 204 can be expressed as a four row and four column matrix, demonstrated by:
As described above, the MixColumn operation can be performed as a GF (28) matrix multiplication with a given one of the columns of the encryption state 204 in a given iteration, as demonstrated by:
The matrix multiplication for an inverse MixColumn operation, as provided during a decryption procedure, can be expressed in a similar manner. For example, the inverse MixColumn operation can also be performed as a GF (28) matrix multiplication with a given one of the columns of the encryption state 204 in a given iteration, as demonstrated by:
As described above, the MixColumn operational circuit 302 can be implemented as the same circuit for the encryption state 204 in both encryption and decryption procedures. To accomplish the use of a single MixColumn operational circuit 302 for both encryption and decryption procedures, the matrix multiplication of Equation 2 can be factored into a GF (28) matrix multiplication of a matrix with the given one of the columns of the encryption state 204 in a given iteration, as follows:
Therefore, by implementing the inverse MixColumn operation for decryption by using the same MixColumn operational circuit 302 with which the MixColumn operation for encryption is implemented, the complexity of the MixColumn module 300 can be significantly reduced based on the resource sharing between the encryption and decryption procedures. Accordingly, the MixColumn module 300 can have significantly fewer GEs than a typical MixColumn module for a conventional AES-256 encryption algorithm.
Referring back to the example of
The RoundKey module 212 provides an encryption round key (e.g., a portion of the original encryption key 218 or an encryption subkey), demonstrated in the example of
The AddRoundKey module 216 is configured to combine the encryption round key KY (e.g., a portion of the original encryption key 218 and/or an encryption subkey) with the transformed encryption state ST_MX. As described above, the original encryption key 218 can be a 256-bit code, such that the original encryption key 218 can includes two 128-bit portions. As an example, each of the encryption subkeys can be a 128-bit code. Therefore, the AddRoundKey module 216 can be configured to combine the 128-bit encryption round key KY with the 128-bit transformed encryption state ST_MX by implementing a bit-wise XOR logic function. The AddRoundKey module 216 can thus output a modified encryption state, demonstrated in the example of
The RoundKey module 402 is configured to store the original encryption key 408 that can correspond to a specific dedicated encryption key for the AES-256 encryption algorithm 200. As an example, the original encryption key 408 can be received by the IC 102 from an external device (e.g., that also provides the data to be encrypted/decrypted) or can be saved in a memory on the associated security device (e.g., security device 100). The original encryption key 218 can be a 256-bit, and can be a 256-bit (32-byte) encryption key, as required by the FIPS-197 standard that defines the AES-256 encryption algorithm 200. In the example of
The RoundKey module 402 also includes a key register 414 that is configured to store the encryption round keys, such as a pair of the encryption round keys, at a given time. For example, the key register 414 can be a 32-byte register, such that the key register can be configured to store a pair-wise combination of encryption round keys, and thus a pair-wise combination of the first original key portion 410, the second original key portion 412, and at least one encryption subkey of a key schedule (e.g., both of the key portions 410 and 412, one of the key portions 410 or 412 and an encryption subkey, or two encryption subkeys) in each iteration of an iterative key expansion operation 416 in which the original encryption key 408 is expanded to generate an encryption subkey of the key schedule in each of a plurality of iterations.
As an example, as encryption subkeys are written to the key register 414, the encryption round keys that were stored in the key register 414 can be replaced by the newly generated encryption subkeys from the iterative key expansion operation 416 in the key register 414. As an example, one of the previous encryption round keys that are stored in the key register 414 can be overwritten to accommodate storage of the newly generated encryption subkey from the iterative key expansion operation 416. For example, the newly generated encryption subkey in each iteration can overwrite one of the two 128-bit blocks of the key register 414 in which the encryption round keys are stored, such as in an alternating manner, after the respective one of the encryption round keys has already been provided to the AddRoundKey module 406. In this manner, the encryption subkeys that are generated by the KeyExpansion module 404 are overwritten in the key register 414 by newly generated encryption subkeys when the encryption round key in the key register 414 is no longer needed by the key expansion system 400. As a result, the KeyExpansion module 404 can provide the key expansion operation in a much more compact manner than a conventional key expansion operation in which all of the encryption subkeys of a key schedule are generated at once, and are thus all stored in a much larger register before the encryption subkeys are needed and continue to be stored after the encryption subkeys are no longer needed.
The RoundKey module 402 provides an encryption round key (e.g., a portion of the original encryption key 408 and/or an encryption subkey), demonstrated in the example of
In the example of
For example, in the first iteration, the RoundKey module 402 provides the first original key portion 410 as the encryption round key KY to the AddRoundKey module 406, and provides the first original key portion 410 as the encryption round key KY to the KeyExpansion module 404. The iterative key expansion operation 416 thus generates a first encryption subkey based on the first original key portion 410. The first encryption subkey is provided to the RoundKey module 402, demonstrated as a signal SUB_KY, to be saved in the key register 414, and thus overwriting the first original key portion 410 in the key register 414.
In the second iteration, the RoundKey module 402 provides the second original key portion 412 as the encryption round key KY to the AddRoundKey module 406, and provides the second original key portion 412 as the encryption round key KY to the KeyExpansion module 404. The iterative key expansion operation 416 thus generates a second encryption subkey based on the second original key portion 412. The second encryption subkey SUB_KY is provided to the RoundKey module 402 to be saved in the key register 414, and thus overwriting the second original key portion 412 in the key register 414.
In the third iteration, the RoundKey module 402 provides the first encryption subkey as the encryption round key KY to the AddRoundKey module 406, and provides the first encryption subkey as the encryption round key KY to the KeyExpansion module 404. The iterative key expansion operation 416 thus generates a third encryption subkey based on the first encryption subkey. The third encryption subkey SUB_KY is provided to the RoundKey module 402 to be saved in the key register 414, and thus overwriting the first encryption subkey in the key register 414. The key expansion operation continues in this manner for each of the remaining twelve iterations, for fifteen total iterations, with the encryption round key KY being provided to the AddRoundKey module 406 in each iteration.
Therefore, as described in the example of
However, as described above, because the RoundKey module 402 only provides a single round key at a time to the KeyExpansion module 404 and the AddRoundKey module 406, the iterative key expansion operation 416 only generates new encryption subkeys of the key schedule when the encryption subkeys are needed to be applied to the KeyExpansion module 404 and the AddRoundKey module 406. Thus, the RoundKey module 402 can overwrite the encryption round keys in the key register 414 that are no longer needed by the KeyExpansion module 404 and the AddRoundKey module 406. In this manner, the key register 414 can be fabricated as being an only 32-byte register in length while still allowing a full key schedule to be iteratively generated and provided to the KeyExpansion module 404 and the AddRoundKey module 406 by the iterative key expansion operation 416. Therefore, as opposed to a conventional KeyExpansion module that requires 240-bytes of registers to hold an entire key schedule that is generated at a single instance instead of iteratively generated, the KeyExpansion module 404 can be fabricated as having significantly fewer GEs and significantly less power consumption than a conventional KeyExpansion module.
At the conclusion of the iterative key expansion operation 416, the final two encryption subkeys of the key schedule are stored in the key register 414. Therefore, during a subsequent decryption procedure, the RoundKey module 402 can start by providing the last encryption subkey of the key schedule to the KeyExpansion module 404 and the AddRoundKey module 406, such that the AddRoundKey module 406 can combine the last encryption subkey to the modified encryption state ST_MX to generate the next modified encryption state NXT_ST. The KeyExpansion module 404 can thus generate previous encryption subkeys via the iterative key expansion operation 416 in reverse order of the key schedule. In the last two iterations of the reverse iterative key expansion operation during the decryption procedure, the RoundKey module 402 can provide the original encryption key 408 to the AddRoundKey module 406 (e.g., in reverse order of the second original key portion 412 followed by the first original key portion 410) to complete the decryption procedure. Accordingly, the RoundKey module 402 and the KeyExpansion module 404 can operate in the same efficient manner for the decryption procedure, using only the 32-byte key register 414 and iterative generation of encryption subkeys as needed, as provided in the encryption procedure. (*** INVENTORS, HOW IS THE KEY EXPANSION OPERATION REVERSED IN A DECRYPTION PROCEDURE IF THERE IS NO INVERSE OPERATION OF THE S-BOX IN THE KEYEXPANSION MODULE?***)
The AddRoundKey module 406 is configured to combine the encryption round key KY with the transformed encryption state ST_MX in each iteration. As described above, each of the encryption round keys (e.g., the first and second original key portions 410 and 412 and the encryption subkeys) can be arranged as 128-bit codes. Therefore, the AddRoundKey module 406 can be configured to combine the 128-bit encryption round key KY with the 128-bit transformed encryption state ST_MX by implementing a bit-wise XOR logic function. The AddRoundKey module 406 can thus output a modified encryption state, demonstrated in the example of
The SubRows module 502 includes a first S-Box 506 and the KeyExpansion module 504 includes a second S-Box 508. As an example, both the first and second S-Boxes can be configured as of any of a variety of different types of Rijndael S-Boxes that provides an 8-bit S-Box transformation, such as the Canright S-Box. The first and second S-Boxes 506 and 508 can be configured to operate concurrently during implementation of the AES-256 encryption algorithm. For example, while the SubRows module 502 is performing the SubRows operation via the first S-Box 506 on a modified version of the encryption state 204, the KeyExpansion module 504 can be performing the iterative key expansion operation to generate a next encryption subkey via the second S-Box 508. Concurrent operation of the first and second S-Boxes 506 and 508 provides for a more efficient implementation of the AES-256 encryption algorithm 200.
In the example of
In the example of
However, the KeyExpansion operation implements only forward operation, and thus does not require an inverse operation circuit. Therefore, by providing the second S-Box 508 to include only a forward operation circuit 514, and to not include an inverse operation circuit, the second S-Box 508 can be provided as a significantly more efficient circuit, as opposed to a KeyExpansion S-Box that is merely a copy of the SubBytes S-Box in a conventional AES-256 encryption algorithm. As a result, the quantity of GEs can be decreased in the circuit design, and the operational power consumption of the second S-Box 508 can be decreased relative to the first S-Box 506. Accordingly, providing the second S-Box 508 to include only a forward operation circuit 514 can contribute to accommodating the IC 102 on which the AES-256 encryption algorithm 200 operates in the constrained environment.
The RFID tag 602 also includes a transponder 608 and a memory 610. The tag reader 604 includes a transmitter 612 and a receiver 614 (e.g., parts of a transceiver device), and also includes a memory 616. As an example, the transmitter 612 can be configured to emit an RF signal that is received by the transponder 608. The transponder 608 can thus receive the RF signal and transmit an RF response signal. The RF signal and RF response signal are demonstrated generally at 618. For example, the memory 610 can be configured to store encrypted sensitive data. As another example, the memory 610 can be configured to store an original encryption key (e.g., the original encryption key 408).
The RFID system 600 can be implemented for an encryption procedure or a decryption procedure via the AES-256 encryption algorithm 200. In an encryption procedure, the transmitter 612 can be configured to provide an encryption request that includes sensitive data to the RFID tag 602 via the RF signal. As an example, the RF signal can also include an original encryption key (e.g., saved in the memory 616) that is transmitted from the tag reader 604 to the RFID tag 602. In the example of the RF signal including the original encryption key, the memory 616 can also include a database that associates encryption keys (e.g., including the original encryption key) with RFID tag information (e.g., including the RFID tag 602). Alternatively, the original encryption key can be stored in the memory 610. The transponder 608 can receive the RF signal and can encrypt the sensitive data via the AES-256 encryption algorithm operating on the IC 606. The encrypted sensitive data can be stored in the memory 610 and/or can be transmitted back to the tag reader 604 via the RF response signal provided by the transponder 608, such that the receiver 614 can receive the RF response signal and save the encrypted sensitive data in the memory 616.
In a decryption procedure, the transmitter 612 can be configured to provide a decryption request that includes sensitive data to the RFID tag 602 via the RF signal. As an example, the RF signal can also include an original encryption key (e.g., saved in the memory 616) that is transmitted from the tag reader 604 to the RFID tag 602. In the example of the RF signal including the original encryption key, the memory 616 can also include the key database that associates encryption keys with RFID tag information. Alternatively, the original encryption key can be stored in the memory 610. The transponder 608 can receive the RF signal and can decrypt the sensitive data via the AES-256 encryption algorithm operating on the IC 606. The decrypted sensitive data can be transmitted back to the tag reader 604 via the RF response signal provided by the transponder 608, such that the receiver 614 can receive the RF response signal and save the decrypted sensitive data in the memory 616.
As described above, the AES-256 encryption algorithm 200 can provide a significantly greater encryption security than other encryption/decryption algorithms (e.g., AES-128 or AES-192). Therefore, the RFID system 600 can be implemented in a very high level security environment in which the level of security provided by the AES-256 encryption algorithm 200 is required. As also described above, the AES-256 encryption algorithm 200 can be designed to be spatially efficient with minimal power consumption. Therefore, the IC 606 on which the AES-256 encryption algorithm 200 is implemented can be provided in the constrained environment housing that is provided by the RFID tag 602, which is otherwise too small and unable to provide sufficient power (e.g., via magnetic flux power transfer) to accommodate a conventional circuit that implements an AES-256 encryption algorithm. Accordingly, by designing the AES-256 encryption algorithm 200 to have less than 5,000 GEs and to consume less than 1.5 microwatts of power, the AES-256 encryption algorithm 200 can be implemented on the IC 606 that can be accommodated in the constrained environment of the RFID tag 602 to allow both convenient and high-level security encryption/decryption.
In view of the foregoing structural and functional features described above, a methodology in accordance with various aspects of the disclosure will be better appreciated with reference to
What have been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Additionally, where the disclosure or claims recite “a,” “an,” “a first,” or “another” element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements. As used herein, the term “includes” means includes but not limited to, and the term “including” means including but not limited to. The term “based on” means based at least in part on.
This application claims priority from U.S. Patent Application Ser. No. 63/505,618, filed 1 Jun. 2023, which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63505618 | Jun 2023 | US |
