Energy-efficient error-correction-detection storage

Abstract

A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

Description

FIELD OF THE INVENTION

The subject matter presented herein relates generally to computer memory.

BACKGROUND

Personal computers, workstations, and servers commonly include at least one processor, such as a central processing unit (CPU), and some form of memory system that includes dynamic, random-access memory (DRAM). The processor executes instructions and manipulates data stored in the DRAM.

DRAM stores binary bits by alternatively charging or discharging capacitors to represent the logical values one and zero. The capacitors are exceedingly small. Their ability to store charge can be hindered by manufacturing variations or operational stresses, and their stored charges can be upset by electrical interference or high-energy particles. The resultant changes to the stored instructions and data produce undesirable computational errors. Some computer systems, such as high-end servers, employ various forms of error detection and correction to manage DRAM errors, or even more permanent memory failures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 details a memory system 100 that employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data.

FIG. 2 shows an example of row Row[i] of FIG. 1 with a flowchart 200 outlining a succession of read accesses to that row, all of which can be initiated by a single read request from an external processor seeking 64 B of read data.

FIG. 3 illustrates how the extra four bytes 241 of 32 B column-block Col[63] is used to store repair elements in one embodiment.

FIG. 4 details a memory system 400 that employs an addressing scheme similar to the one detailed above in connection with FIG. 1.

FIG. 5 illustrates how mapping logic 500 remaps physical addresses PA[39:0] responsive to an Apso configuration value stored in a local register 505, an Apso value of six in this configuration.

FIG. 6 is a table 600 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=111b.

FIG. 7 is a table 700 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=101b.

FIG. 8 is a table 800 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=100b.

FIG. 9 is a table 900 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=011b.

FIG. 10 is a table 1000 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=010b.

FIG. 11 is a table 1100 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=001b.

FIG. 12 is a table 1000 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=000b.

FIG. 13 depicts a cold memory system 1300 in accordance with one embodiment.

FIG. 14 depicts an address-mapping scheme in accordance with another embodiment that performs three column transactions per row activation.

FIG. 15 details an embodiment of mapping logic 1400 of FIG. 14.

DETAILED DESCRIPTION

FIG. 1 details a memory system 100 that employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. When a given row is opened responsive to an access request for data, the EDC code for that data is in the same row and is thus available without opening another row. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. Moreover, the addressing scheme partitions the memory in support of this efficiency without requiring the processor or controller issuing the access requests to have an understanding of the memory partition. Memory system 100 thus supports a power-efficient EDC scheme that is compatible with legacy systems.

Memory system 100 includes sixteen data aggregators 105, one of which is shown, each servicing memory requests from a memory controller and/or processor (not shown) via eight ten-conductor 6Q/4D primary links. One or more aggregators 105 can be integrated-circuit (IC) memory buffers that buffer and steer signals between an external processor and DRAM components. Each primary link 6Q/4D communicates with a corresponding memory slice 107, each of which includes an 8 GB memory component, a stack of four fourth-generation, low-power, double-data-rate (LPDDR4) memory die in this example. Each LPDDR4 die includes two sets of eight banks 109 coupled to a DRAM interface 113 that communicates data and control signals between the DRAM stacks and a serializer/deserializer SERDES 117 via respective local sixteen-trace channels 114. A local controller 115 in each slice 107 steers data via interface 113 responsive to access requests received from the corresponding 6Q/4D primary link.

In this example, one hundred twenty-eight 8 GB slices 107 provide a total of 1 TB of memory space addressable via forty-bit physical addresses PA[39:0] (2⁴⁰ B=1 TB). From the requesting processor's perspective, the seven most-significant bits PA[39:33] specify a slice 107; bits PA[32:18] specify a row Row[i] of memory cells in banks 109; bits PA[17:15] specify a local channel 114; bits PA[14:11] specify a rank/bank; bits PA[10:5] specify a column; and bits PA[4:0] specify a byte. Of the rank/bank bits PA[14:11], three bits identify the rank and one bit distinguishes between two devices per secondary channel.

The external processor employing memory system 100 is configured to perceive memory system 100 as providing 896 GB. This first region, seven eighths of the usable capacity, is available to the external processor via slice-address bits Slice[6:0] in the range from 0000000b to 1101111b. In this context, “usable” memory refers to memory available to the local and remote processors, and is distinct from redundant columns of memory cells and related repair circuitry commonly included in DRAM devices to compensate for defective memory resources (e.g., defective memory cells).

Local controllers 115 can be configured to send an error message responsive to external memory requests that specify a slice address above this range (Slice[6:4]=111XXXXb]). The remaining eighth of the memory capacity, a second region of 112 GB in slice address range Slice[6:0]=111XXXXb, is inaccessible to the external processor but available to local controllers 115 to store e.g. EDC codes. Seven-eighths of the 1 TB of usable storage capacity of memory system 100 is thus allocated for data storage and one eighth reserved for e.g. EDC code storage.

Local controllers 115 remap physical address PA[10:8] to the three MSBs PA[39:37] so that the three MSBs specify the most-significant column-address bits Col[5:3]. The remaining address fields are shifted right three places in this example but can be otherwise rearranged in other embodiments. The three most-significant bits PA[39:37] of the physical address should never be 111b because the remote processer is address constrained to a maximum of 110111b. Because local controllers 115 remap the three most-significant bits to column-address bits Col[5:3], requests directed to memory system 100 will never be directed to column addresses 111XXXb. These high-order column addresses are thus reserved for EDC codes.

In the example of FIG. 1, a read request from an external processor seeks sixty-four bytes (64 B) of data from memory system 100. The controller 115 associated with the addressed one of slices 107 uses the remapped physical address to issue successive local read requests to columns Col[j] and Col[j+1] of a row Row[i], receiving 32 B for each column access. The controller 115 issues a third local read request to row Row[i] column Col[56+j/8] to read from one column in the second region. Eight bytes of this 32 B column access provides an EDC code that the local controller 115 uses to detect and correct for errors. An error-detection code that does not support error correction can also be used.

Local controllers 115 take advantage of the remapped column-address bits to store data and related EDC codes in the same row of the same bank 109. As is typical in DRAM memory devices, a row of memory cells is “opened” in response to an access request, a process in which the values stored in each cell of the open row are sensed and latched. A column address then selects a column of latched bits to communicate via an external bus. Opening a row takes time and power. Reading the latched bits from different columns of the same open row is thus relatively fast an efficient. Likewise, local controllers 115 open only one row to write data and an associated EDC code the controllers 115 calculate from the data using well-known techniques.

FIG. 2 shows an example of row Row[i] of FIG. 1 with a flowchart 200 outlining a succession of read accesses to that row, all of which can be initiated by a single read request from an external processor seeking 64 B of read data. In this example the read data is encrypted for storage in the first region of the memory. Local controller 115 uses EDC codes and encryption/decryption keys stored in the second region of the memory to both correct for errors and decrypt requested data.

Beginning with step 205, the selected local controller 115 directs a first access request to column Col[001000b] (or Col[08] decimal), receiving an encrypted 32 B column block 210 in response. Local controller 115 sends a second read request 215 to column Col[001001b] (Col[09]) of the same row Row[i] to obtain a second encrypted 32 B column block 220. A third read access 225 to Col[111001b] (Col[57]) reads a 32 B column block comprised of four 8 B cachelines, one cacheline for each pair of columns Col[001XXXb]. The selected local controller 115 uses the 8 B EDC cacheline 230 associated with columns Col[001000b,0010001b] to detect and correct for errors (235) in column blocks 210 and 220, and thus to provide 64 B of error-corrected data 240.

In this embodiment the error corrected data is encrypted, and column Col[111111b] (Col[63]) stores 28 byte-wide keys, one for each pair of columns in the first region, leaving an extra four bytes 241 for other purposes. In step 245, the selected local controller 115 reads the 1 B key 250 associated with columns Col[001000b,0010001b] to decrypt error-corrected data 240 (process 255) and thus provide 64 B of error-corrected, decrypted data 260. This data is passed to the SERDES 117 in the selected slice 107 and transmitted to the external processor that conveyed the initial read request (step 265). The order of column accesses to the same row can be different in other embodiments.

FIG. 3 illustrates how the extra four bytes 241 of 32 B column-block Col[63] is used to store repair elements in one embodiment. Each 2 KB (2¹⁴b) row includes two 16-bit repair elements 300A and 300B, one to substitute for one erroneous bit from the lower 213 bits in the same row and another to substitute one erroneous bit from the upper 213 bits. The same column access that provides the decryption key also yields repair elements 300A and 300B, which local controller 115 associates with respective halves of the bit addresses and employs to store replacement bits for defective bit addresses.

Local controller 115 can uses repair element 300A (300B) to store: (1) a 13-bit address to identify a defective bit location in the lower half (upper half) of the corresponding row; (2) a replacement bit D to replace a suspect bit read from the defective location; (3) a valid bit V set when local controller 115 noted the defective location and employed the repair element; and (4) a parity bit P local controller 115 set to one or zero during writes to the repair element such that the sum of the set of bits in the repair element is always even (or odd).

During a read transaction, local controller 115 considers whether either or both repair elements corresponds to a bit address retrieved in any column access of the pending transaction. If so, and if the valid and parity bits V and P indicate the availability of a valid, error-free replacement bit D, then control logic 115 substitutes the bit read from the defective location with replacement bit D. Control logic 115 may await consideration of repair elements 300A and 300B before applying ECC and decryption steps. For reduced latency, ECC and decryption steps may begin before and during consideration of repair elements 300A and 300B to be repeated with a replacement bit if a corresponding repair element is noted.

FIG. 4 details a memory system 400 that employs an addressing scheme similar to the one detailed above in connection with FIG. 1. Memory system 400 includes some number of aggregators 402, one of which is shown, each servicing memory requests from an external processor (not shown) via eight ten-conductor 6Q/4D primary links. Each primary link 6Q/4D communicates with a corresponding memory slice 403, each of which includes two 8 GB memory components, a stack of four fourth-generation, low-power, double-data-rate (LPDDR4) memory die in this example. Each LPDDR4 die includes two sets of eight banks 109 coupled to a DRAM interface 407 that communicates data and control signals between the DRAM stacks and a serializer/deserializer SERDES 117 via respective local sixteen-trace channels 409. A local a local controller 404 in each slice 403 steers data via interface 407 responsive to access request received from the corresponding 6Q/4D primary link.

Control logic (FIG. 5) within each local controller 404 alters the addressing scheme for local memory accesses responsive to a control value Apso that can be stored in a local configuration register (FIG. 5) to support 2, 4, 6, 8, 10, 12, 14, or 16 aggregators 402 and associated memory resources. This memory scheme therefore offers a range of available memory, as summarized in a table 420. The addressing scheme and related circuitry of system 400 can be used when the number of memory components (e.g. LPDDR4 stacks 405) is not a power of two.

Table 420 highlights a configuration corresponding to Apso value six (110b) in which fourteen aggregators 402 each support eight slices 403, and each slice provides access to two stacks 415 of four 8 GB memory devices, providing 896 GB of usable memory. Of this memory, 56/64th is used for data storage and 7/64th for EDC. The remaining 1/64th is available for other uses. Each of the 112 6Q/4D primary links provides a data bandwidth of 9.6 GB/s for a total primary data bandwidth of 1,075 GB/s. Each secondary link provides a data bandwidth of 4.977 GB/s for a total secondary bandwidth of 4459 GB/s.

FIG. 5 illustrates how mapping logic 500 remaps physical addresses PA[39:0] responsive to an Apso configuration value stored in a local register 505, an Apso value of six in this configuration. A forty-bit physical address PA[39:0] (FIG. 1) arriving with an external memory request is remapped such that the three most-significant column bits ColM lie between the three most-significant slice bits SliceM and the four least-significant slice bits SliceL.

Slice bits SliceM are conveyed as physical slice address Aps[2:0] and column bits ColM are conveyed as physical column address Apc[2:0]. These six bits define sixty-four blocks in processor address space 510A/B. The region of processor address space 510A/B unavailable to the external processor is cross-hatched in space 510B.

Mapping logic 500 remaps addresses in which column address ColM is 111b to a higher address range, as indicated by arrows, to reserve column addresses Col[111XXXb] for EDC values, etc., as detailed in connection with memory system 100 of FIG. 1. Referring to mapping logic 500, when column address ColM is any value other than 111b physical slice address Aps[2:0] is used as the high-order memory slice address Ams[2:0] and physical column address Apc[2:0] is used as the high-order memory column address Amc[2:0]. When column address ColM is 111b, an AND gate causes a pair of multiplexers to substitute physical slice address Aps[2:0] for the value in register 505 and to change column address Apc[2:0] to a sum of slice address Aps[2:0] and the inverse of the Apso value in register 505.

FIG. 6 is a table 600 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=111b. Address space unavailable to the requesting processor is crossed out. All of the available memory is available to the local controller.

FIG. 7 is a table 700 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=101b. Address space unavailable to the requesting processor and local controller is crossed out.

FIG. 8 is a table 800 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=100b. Address space unavailable to the requesting processor and local controller.

FIG. 9 is a table 900 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=011b. Address space unavailable to the requesting processor and local controller is crossed out.

FIG. 10 is a table 1000 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=010b. Address space unavailable to the requesting processor and local controller is crossed out.

FIG. 11 is a table 1100 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=001b. Address space unavailable to the requesting processor and local controller is crossed out.

FIG. 12 is a table 1000 illustrating how mapping logic 500 of FIG. 5 maps physical addresses Aps[2:0] and Apc[2:0] to memory addresses Ams[2:0] and Amc[2:0] when register 505 is loaded with a configuration value Apso=000b. Address space unavailable to the requesting processor and local controller is crossed out.

FIG. 13 depicts a cold memory system 1300 in accordance with one embodiment. The adjective “cold” refers to operating temperature. The memory subsystem operates at e.g. 77K, whereas the processor subsystem operates at e.g. 4K. Memory system 1300 includes sixteen aggregators 1315 in the 77K domain, each connected to the 4K domain via eight primary 6Q/4D links. As in the example of FIGS. 4 and 5, mapping logic 500 is part of local controller 115. In other embodiments some or all of this control functionality is provided on a primary controller 1320 in the 4K domain that serves e.g. N processors that initiate memory transactions with the DRAM stacks in the manner detailed previously. When mapping logic 500 is placed in aggregators 1315, the different capacity cases adjusts the number of stacks per aggregator {2,4,6,8,10,12,14,16} and the number of 6Q/4D LINK groups per aggregator {1,2,3,4,5,6,7,8}. The number of aggregators 1315 is fixed at sixteen. When mapping logic 500 is placed in the steering logic in 4K domain, the different capacity cases adjusts the number of aggregators {2,4,6,8,10,12,14,16}. The number of 6Q/4D link groups per aggregator 1315 is fixed at eight, and the number of stacks 415 per aggregator 1315 is fixed at sixteen. In either case the six Q links for each 6Q/4D slice communicate 8×6 bits at 10 Gb/s, whereas the four D links communicate 8×4 bits at 10 Gb/s.

FIG. 14 depicts an address-mapping scheme in accordance with another embodiment that performs three column transactions per row activation. Mapping logic 1400 maps the three most-significant bits of the physical address to the three most-significant column-address bits ColM and the next two bits to the two most-significant slice bits SliceM. The memory system employing this scheme is assumed to have a number of slices that is not a power of two, ninety-six in this example. The address-mapping scheme of FIG. 14 is similar to that of FIG. 4 except that the column and slice fields are reversed, and the slice field uses but two bits. Mapping logic 1400 uses high-order address blocks to fill holes in the memory address space.

FIG. 15 details an embodiment of mapping logic 1400 of FIG. 14. Mapping logic 1400 is simpler than mapping logic 500 of the prior embodiment, but becomes more complex if the SliceM field is extended to three or more bits.

While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or “coupling,” establishes some desired electrical communication between two or more circuit nodes, or terminals. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.

Claims

1. A method of accessing a memory comprising memory cells arranged in rows of the memory cells and columns of the memory cells, the method comprising: receiving a physical address having most-significant address bits specifying one of the columns of the memory cells and row-address bits specifying one of the rows of the memory cells;receiving data and an error-detection-and-correction (EDC) code corresponding to the data;writing the data to first contiguous ones of the memory cells in the specified row and the specified column of the memory cells; andwriting the EDC code corresponding to the data in second contiguous ones of the memory cells in the specified row of the memory cells.

2. The method of claim 1, wherein the memory comprises memory devices and the most-significant address bits specify one of the memory devices.

3. The method of claim 1, wherein each of the rows of the memory cells includes a number of the memory cells that is a power of two.

4. The method of claim 1, wherein the memory cells are dynamic, random-access memory cells.

5. The method of claim 1, further comprising activating the one of the rows of memory cells for a row activation and writing the data and the EDC code during the row activation.

6. The method of claim 5, further comprising activating the one of the rows of memory cells for a second row activation and reading the data and the EDC code during the second row activation.

7. The method of claim 5, further comprising activating the one of the rows of memory cells for a second row activation, reading the data responsive to a first column access and a second column access during the second row activation, and reading the EDC code responsive to a third column access during the second row activation.

8. The method of claim 1, wherein the row of the memory cells includes a total number of the memory cells and the first contiguous ones of the memory cells number seven eighths of the total number of the memory cells in the row.

9. The method of claim 8, wherein the second contiguous ones of the memory cells number seven sixty-fourths of the total number.

10. The method of claim 1, further comprising: sending an encryption key with the data and the EDC code to the memory; andstoring the encryption key in the specified row.

11. The method of claim 10, wherein the specified row of the memory cells includes a total number of the memory cells and the encryption key includes a total number of bits that is 1/512 of the total number of the memory cells in the specified row.

12. The method of claim 1, wherein the memory includes a number of memory devices that is a power-of-two.

13. The method of claim 1, wherein the most-significant address bits consist of three column bits.

14. The method of claim 13, wherein the three column bits select between the first contiguous ones of the memory cells and the second contiguous ones of the memory cells.

15. An integrated-circuit (IC) memory buffer comprising: an external interface to receive an external write request specifying a physical memory address and write data; anda memory interface to issue successive local memory requests responsive to the external write request, the local memory requests including: a first local memory request specifying a row of memory cells and a first column of the memory cells, the first column of the memory cells to store a first subset of the write data;a second local memory request specifying the row of the memory cells and a second column of the memory cells, the second column of the memory cells to store a second subset of the write data; anda third local memory request specifying the row of the memory cells and a third column of the memory cells, the third column of the memory cells to store an error-detection-and-correction (EDC) code corresponding to the write data.

16. The IC of claim 15, wherein the memory interface performs a row activation on the row of memory cells and stores the first subset of the write data, the second subset of the write data, and the EDC code responsive to the row activation.

17. The IC of claim 15, wherein the first column of memory cells and the second column of memory cells are contiguous memory cells and the third column of memory cells are contiguous memory cells separate from the first column of memory cells and the second column of memory cells.

18. The IC of claim 15, wherein the first column of the memory cells, the second column of the memory cells, and the third column of the memory cells in the row of the memory cells total three eighths of a total number of the memory cells in the row of the memory cells.

19. A memory controller for accessing a memory having memory cells arranged in rows and columns, the memory controller comprising: an external interface to receive an external memory request specifying a physical memory address to store write data; andmeans for sending the write data and an error-detection-and-correction (EDC) code corresponding to the write data to a row of the memory cells responsive to the external memory request;wherein the means for sending issues: a first local memory request specifying the row of the memory cells and a first column of the memory cells, the first column of the memory cells to store a first subset of the write data;a second local memory request specifying the row of the memory cells and a second column of the memory cells, the second column of the memory cells to store a second subset of the write data; anda third local memory request specifying the row of the memory cells and a third column of the memory cells, the third column of the memory cells to store the EDC code corresponding to the write data.

20. The memory controller of claim 19, further comprising means for deriving the EDC code from the write data.