1. Field of the Invention
The present invention relates to addressing schemes for reducing power consumption necessary to address a display.
2. Description of Related Technology
Microelectromechanical systems (MEMS) include micro mechanical elements, actuators, and electronics. Micromechanical elements may be created using deposition, etching, and or other micromachining processes that etch away parts of substrates and/or deposited material layers or that add layers to form electrical and electromechanical devices. One type of MEMS device is called an interferometric modulator. As used herein, the term interferometric modulator or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In certain embodiments, an interferometric modulator may comprise a pair of conductive plates, one or both of which may be transparent and/or reflective in whole or part and capable of relative motion upon application of an appropriate electrical signal. In a particular embodiment, one plate may comprise a stationary layer deposited on a substrate and the other plate may comprise a metallic membrane separated from the stationary layer by an air gap. As described herein in more detail, the position of one plate in relation to another can change the optical interference of light incident on the interferometric modulator. Such devices have a wide range of applications, and it would be beneficial in the art to utilize and/or modify the characteristics of these types of devices so that their features can be exploited in improving existing products and creating new products that have not yet been developed.
The following detailed description is directed to certain specific embodiments. However, the teachings herein can be applied in a multitude of different ways. In this description, reference is made to the drawings wherein like parts are designated with like numerals throughout. The embodiments may be implemented in any device that is configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or pictorial. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and/or displays, display of camera views (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry). MEMS devices of similar structure to those described herein can also be used in non-display applications such as in electronic switching devices.
Conventional approaches to reducing power consumption in MEMS display devices have included various techniques that each tends to compromise the user experience by decreasing the quality of the image displayed to the user. These approaches have included decreasing the resolution or complexity of displayed images, decreasing the number of images in the sequence over a given time period, and decreasing the grayscale or color intensity depth of the image. Other suggestions have been made to reduce power consumption by different methods of addressing the display, however, they have been too complex, such that they require more power to solve the computation than power saved from the addressing of the display. Methods and devices are described herein which are configured to reduce power consumption by determining a row-addressing order based on attributes of the image data, and reducing the number of column charging transitions necessary to write an image to the display. One embodiment provides a method of efficiently computing a row-addressing order for a display device and addressing the display.
One interferometric modulator display embodiment comprising an interferometric MEMS display element is illustrated in
The depicted portion of the pixel array in
The optical stacks 16a and 16b (collectively referred to as optical stack 16), as referenced herein, typically comprise several fused layers, which can include an electrode layer, such as indium tin oxide (ITO), a partially reflective layer, such as chromium, and a transparent dielectric. The optical stack 16 is thus electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The partially reflective layer can be formed from a variety of materials that are partially reflective such as various metals, semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials.
In some embodiments, the layers of the optical stack 16 are patterned into parallel strips, and may form column electrodes in a display device as described further below. The movable reflective layers 14a, 14b may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the column electrodes of 16a, 16b) to form rows deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, the movable reflective layers 14a, 14b are separated from the optical stacks 16a, 16b by a defined gap 19. A highly conductive and reflective material such as aluminum may be used for the reflective layers 14, and these strips may form row electrodes in a display device. Note that
With no applied voltage, the gap 19 remains between the movable reflective layer 14a and optical stack 16a, with the movable reflective layer 14a in a mechanically relaxed state, as illustrated by the pixel 12a in
In one embodiment, the processor 21 is also configured to communicate with an array driver 22. In one embodiment, the array driver 22 includes a row driver circuit 24 and a column driver circuit 26 that provide signals to a display array or panel 30. The cross section of the array illustrated in
As described further below, in typical applications, a frame of an image may be created by sending a set of data signals (each having a certain voltage level) across the set of column electrodes in accordance with the desired set of actuated pixels in the first row. A row pulse is then applied to a first row electrode, actuating the pixels corresponding to the set of data signals. The set of data signals is then changed to correspond to the desired set of actuated pixels in a second row. A pulse is then applied to the second row electrode, actuating the appropriate pixels in the second row in accordance with the data signals. The first row of pixels are unaffected by the second row pulse, and remain in the state they were set to during the first row pulse. This may be repeated for the entire series of rows in a sequential fashion to produce the frame. Generally, the frames are refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second. A wide variety of protocols for driving row and column electrodes of pixel arrays to produce image frames may be used.
When a release voltage VCREL is applied along a common line, all interferometric modulator elements along the common line will be placed in a relaxed state, alternatively referred to as a released or unactuated state, regardless of the voltage applied along the segment lines. The release voltage VCREL and the high and low segment voltages VSH and VSL are selected accordingly. In particular, when the release voltage VCREL is applied along a common line, the potential voltage across the modulator (alternatively referred to as a pixel voltage) is within the relaxation window (see
When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD
When an addressing voltage is applied on a common line, such as high addressing voltage VCADD
In certain embodiments, only a high or a low hold voltage and address voltage may be used. Using both positive and negative hold and address voltages, however, allows the polarity of write procedures to be alternated, inhibiting charge accumulation which could occur after write operations of only a single polarity.
During the first line time 60a, none of common lines 1, 2, or 3 are being addressed. A release voltage 70 is applied on common line 1. The voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70. A low hold voltage 76 is applied along common line 3. Thus, the modulators (1,1), (1,2), and (1,3) along common line 1 remain in a relaxed state for the duration of the first line time 60a, the modulators (2,1), (2,2), and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2), and (3,3) along common line 3 will remain in their previous state. The segment voltages applied along segment lines 1, 2, and 3 will have no effect on the state of the interferometric modulators, as none of common lines 1, 2, or 3 are being addressed during line time 60a.
During the second line time 60b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied. The modulators along common line 2 remain in a relaxed state, and the modulators (3,1), (3,2), and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage 70.
During the third line time 60c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the pixel voltage across modulators (1,1) and (1,2) is greater than the positive stability window of the modulators, and modulators (1,1) and (1,2) are actuated. Because a high segment voltage 62 is applied along segment line 3, the pixel voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and is within the positive stability window of the modulator. Modulator (1,3) thus remains relaxed. Also during line time 60c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage, leaving the modulators along common lines 2 and 3 in a relaxed position.
During the fourth line time 60d, the voltage on common line 1 is at a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. Common line 2 is now addressed by decreasing the voltage on common line 2 to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the pixel voltage across modulator (2,2) is below the negative stability window of the modulator, causing the modulator (2,2) to actuate. Because a low segment voltage 64 is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state.
Finally, during the fifth line time 60e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at a low hold voltage, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth hold time 60e, the 3×3 pixel array is in the state shown in
In the timing diagram of
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48, and a microphone 46. The housing 41 is generally formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including but not limited to plastic, metal, glass, rubber, and ceramic, or a combination thereof. In one embodiment the housing 41 includes removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 of exemplary display device 40 may be any of a variety of displays, including a bi-stable display, as described herein. In other embodiments, the display 30 includes a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD as described above, or a non-flat-panel display, such as a CRT or other tube device. However, for purposes of describing the present embodiment, the display 30 includes an interferometric modulator display, as described herein.
The components of one embodiment of exemplary display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the exemplary display device 40 can communicate with one or more devices over a network. In one embodiment the network interface 27 may also have some processing capabilities to relieve requirements of the processor 21. The antenna 43 is any antenna for transmitting and receiving signals. In one embodiment, the antenna transmits and receives RF signals according to the IEEE 802.11 standard, including IEEE 802.11(a), (b), or (g). In another embodiment, the antenna transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna is designed to receive CDMA, GSM, AMPS, W-CDMA, or other known signals that are used to communicate within a wireless cell phone network. The transceiver 47 pre-processes the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also processes signals received from the processor 21 so that they may be transmitted from the exemplary display device 40 via the antenna 43.
In an alternative embodiment, the transceiver 47 can be replaced by a receiver. In yet another alternative embodiment, network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. For example, the image source can be a digital video disc (DVD) or a hard-disc drive that contains image data, or a software module that generates image data.
Processor 21 generally controls the overall operation of the exemplary display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 21 then sends the processed data to the driver controller 29 or to frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation, and gray-scale level.
In one embodiment, the processor 21 includes a microcontroller, CPU, or logic unit to control operation of the exemplary display device 40. Conditioning hardware 52 generally includes amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. Conditioning hardware 52 may be discrete components within the exemplary display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 takes the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and reformats the raw image data appropriately for high speed transmission to the array driver 22. Specifically, the driver controller 29 reformats the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as a LCD controller, is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. They may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
Typically, the array driver 22 receives the formatted information from the driver controller 29 and reformats the video data into a parallel set of waveforms that are applied many times per second to the hundreds and sometimes thousands of leads coming from the display's x-y matrix of pixels.
In one embodiment, the driver controller 29, array driver 22, and display array 30 are appropriate for any of the types of displays described herein. For example, in one embodiment, driver controller 29 is a conventional display controller or a bi-stable display controller (e.g., an interferometric modulator controller). In another embodiment, array driver 22 is a conventional driver or a bi-stable display driver (e.g., an interferometric modulator display). In one embodiment, a driver controller 29 is integrated with the array driver 22. Such an embodiment is common in highly integrated systems such as cellular phones, watches, and other small area displays. In yet another embodiment, display array 30 is a typical display array or a bi-stable display array (e.g., a display including an array of interferometric modulators).
The input device 48 allows a user to control the operation of the exemplary display device 40. In one embodiment, input device 48 includes a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a touch-sensitive screen, a pressure- or heat-sensitive membrane. In one embodiment, the microphone 46 is an input device for the exemplary display device 40. When the microphone 46 is used to input data to the device, voice commands may be provided by a user for controlling operations of the exemplary display device 40.
Power supply 50 can include a variety of energy storage devices as are well known in the art. For example, in one embodiment, power supply 50 is a rechargeable battery, such as a nickel-cadmium battery or a lithium ion battery. In another embodiment, power supply 50 is a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell, and solar-cell paint. In another embodiment, power supply 50 is configured to receive power from a wall outlet.
In some implementations control programmability resides, as described above, in a driver controller which can be located in several places in the electronic display system. In some cases control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
The details of the structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example,
In embodiments such as those shown in
Some embodiments of the invention involve utilizing a row-addressing order based on attributes of image data in order to update a display array using a reduced number of column voltage transitions. In order to reduce the number of column charge transitions, the system can create a row-addressing order based on the content of the image data to be written to the array. By ordering the row addressing with image content in mind, similar rows can be strobed one after the other, thereby reducing the total number of column transitions needed to write an image to the display.
Each of the display elements 801 has a reflective state, wherein the display element 801 reflects certain wavelengths of light, and a non-reflective state, wherein the display element 801 reflects almost no light. As used herein, a display element 801 may also be referred to as being “dark” or in an actuated state (i.e. non-reflective state), or as being in a “color” or non-actuated state (i.e. reflective state).
In one embodiment, the state of each display element 801 can be represented by a bit. The value of the bit corresponds to whether the display element 801 is in a dark state (e.g., 0) or a color state (e.g., 1). In an exemplary embodiment the state of each display element 801 in each color row of a pixel is represented by the most significant bits (MSB) and a least significant bit (LSB). Accordingly, the state of all of the display elements 801 of a given pixel can be represented by the MSB and LSB for each color. In one embodiment, the state of the 2 left-most display elements 801 of a given color row of a given pixel are represented by the MSB and the state of the right most display element 801 of a given color row of a given pixel is represented by the LSB. For example, the state of red display elements 842, 844 are represented by the MSB of the red color row of pixel 840 and the state of red display element 846 is represented by the LSB of the red color row of pixel 840. Similarly in this example, the state of green display elements 848, 850 are represented by the MSB of the green color row of pixel 840 and the state of green display element 846 is represented by the LSB of the green color row of pixel 840. Further in this example, the state of blue display elements 854, 856 are represented by the MSB of the blue color row of pixel 840 and the state of blue display element 858 is represented by the LSB of the blue color row of pixel 840. In this exemplary embodiment, pixel 840 has three MSB, one for each color row, and three LSB, one for each color row. For example, a MSB of 10 and LSB of 1 for the red color row of pixel 840, corresponds to display elements 842 and 846 being in a color state and display element 844 being in a dark state.
It should be noted that the above described array is merely an exemplary array and one skilled in the art will recognize that the array may include more or fewer lines and more or fewer columns. Further, the lines may include more or fewer color rows, and the sets of columns may include more or fewer bits. Additionally, the colors of the rows may include fewer, more, or alternate colors, e.g., cyan, magenta, yellow, and/or white.
One factor determining the power consumption from driving an interferometric modulator display is the charging and discharging of the line capacitance for the columns receiving the image data. This is due to the fact that the column voltages are switched at a very high frequency (up to the number of columns multiplied by one less than the number of rows in the array for each frame update period), compared to the relatively low frequency of the row pulses (one pulse per row per frame update period). In fact, the power consumed by the row pulses generated by row driver circuits may be ignored when estimating the power consumed in driving a display without sacrificing an accurate estimate of total power consumed. Accordingly, the term “column” as used herein is defined as the set of display inputs that receive image data at a relatively high signal transition frequency. The term “rows” is defined as the set of display inputs that receive a periodic applied signal that is independent of the display data and is applied at a relatively low frequency to each row, such as the row strobes described above. The terms “row” and “column” do not therefore imply any geometric position or relationship.
One equation for estimating the energy consumed by writing to an entire column, ignoring row pulse energy, is:
(Energy/col)=½*count*Cline*|VCH2−VCL2| (1)
The power consumed in driving an entire array is the energy required for writing to every column divided by time or:
where:
It should be noted that these equations are applicable to driving voltages such as those shown in
For a given frame update frequency (f) and frame size (number of columns), the power required to write to the display is linearly dependent on the frequency of the data being written. Of particular interest is the “count” variable in (1), which depends on the frequency of changes in display element states (actuated or relaxed) in a given column. Thus, by reducing the number of column voltage transitions involved in writing to the display, the amount of power consumed by the display is reduced.
In another embodiment the addressing order may be included in the image file. In this embodiment, the image data may be processed before hand and the addressing order associated with the image data in a single file.
At step 1414 of the process 1400, it is determined whether all the lines of the array have been addressed. If it is determined all lines have been addressed the process 1400 continues to a step 1422 described below. If it is determined all the lines have not been addressed, the process 1400 proceeds to a further step 1416. In step 1416, a first color row is addressed by array driver 22 for each line that has not yet been addressed. For example, if an array includes lines 1-5 and lines 2 and 4 have not been addressed, a first color row of line 2 and line 4 is addressed. The first color row is selected from the set of color rows in each line. In an exemplary embodiment, the first color row is the top-most color row of each line. In another embodiment, each line includes a red row, a blue row, and a green row. In one embodiment, the first color row is the blue row. The process 1400 then proceeds to a step 1418 where a second color row of the set of color rows not yet addressed in each line is selected. The second color row is addressed by array driver 22. In the exemplary embodiment, the second color row is the second color row from the top color row of each line. In one embodiment, the second color row is the green row. The process 1400 then proceeds to a step 1420 where a third color row of the set of color rows not yet addressed in each line is selected. The third color row is addressed by array driver 22. In the exemplary embodiment, the third color row is the third color row from the top color row of each line. In one embodiment, the third color row is the red row. In a further step 1422, it is determined whether to continue to a next image. If the decision is made to continue, the process 1400 returns to step 1402. If the decision is made not to continue, the process 1400 ends.
In one embodiment the MSB of the red color row of the selected pixel is compared to the MSB of the green color row. Further the LSB of the red color row is compared to the LSB of the green color row. In one embodiment, the comparison comprises an exclusive-or (xor) performed by xor gates. In this embodiment the xor between the MSBs results in a 0 or 1 value and the xor between the LSBs results in a second 0 or 1 value. In an exemplary embodiment, the result of the xor between the MSBs is multiplied by 2 and summed with the xor between the LSBs. This sum is added to the value of A. Process 1500 then continues to a step 1508.
In step 1508, the state of the green display elements of the pixel is compared to the state of the blue display elements of the pixel. An approximation of the similarity between the state of the green display elements and the blue display elements is then made. In one embodiment the MSB of the green color row is compared to the MSB of the blue color row. Further the LSB of the green color row is compared to the LSB of the blue color row. In one embodiment, the comparison comprises an exclusive-or (xor) performed by xor gates. In this embodiment the xor between the MSBs results in a 0 or 1 value and the xor between the LSBs results in a second 0 or 1 value. In an exemplary embodiment, the result of the xor between the MSBs is multiplied by 2 and summed with the xor between the LSBs. This sum is added to the value of B. Process 1500 then proceeds to a step 1510.
In step 1510, the state of the blue display elements of the pixel is compared to the state of the red display elements of the pixel. An approximation of the similarity between the state of the blue display elements and the red display elements is then made. In one embodiment the MSB of the blue color row is compared to the MSB of the red color row. Further the LSB of the blue color row is compared to the LSB of the red color row. In one embodiment, the comparison comprises an exclusive-or (xor) performed by xor gates. In this embodiment the xor between the MSBs results in a 0 or 1 value and the xor between the LSBs results in a second 0 or 1 value. In an exemplary embodiment, the result of the xor between the MSBs is multiplied by 2 and summed with the xor between the LSBs. This sum is added to the value of C. Next, in a decision step 1512, it is determined by processor 21 if the current pixel is the last pixel of the line (i.e., all the pixels of the selected line have been selected). In an exemplary embodiment, the last pixel of the line is the right most pixel of the line. If it is determined the pixel is not the last pixel, the process 1500 returns to step 1504. If it is determined the pixel is the last pixel of the line, the process 1500 continues to a step 1514.
In step 1514, the row addressing order is determined for the selected line. The row order is based on the comparisons made in steps 1506-1510. If the color rows for the selected line are not similar, then the line is set to be addressed by entire array color row sequence. In an exemplary embodiment, similarity is determined by summing the determined A and B values and comparing the sum to a threshold value using a comparison register. This sum is an approximation of the number of column voltage transitions necessary for addressing the selected line in per line row sequence. If the sum is greater than the threshold value, the line is set to be addressed by entire array color row sequence. If the sum is less than the threshold value, the line is set to be addressed by per line row sequence. In an exemplary embodiment, the threshold value is programmable. In another embodiment, the threshold value is fixed. In one embodiment, the threshold value is around 0.4*numSegs, where numSegs is the maximum number of column voltage transitions necessary for a given line. As described above with respect to
If the sum of A and B is less than the threshold value, the per line row sequence for the line is selected to minimize the number of column voltage transitions required to address color rows of a line. In one exemplary embodiment, the addressing sequence is chosen according to a comparison of the values of A, B, and C using comparison registers. If A is the maximum value, the line is set to be addressed in green, blue, red order. If B is the maximum value, the line is set to be addressed in blue, red, green order. If C is the maximum value, the line is set to be addressed in red, green, blue order. In one embodiment, the row addressing order for a line is indicated by a flag value for the line. It should be noted that one of ordinary skill in the art will recognize that other color addressing sequences may be used without increasing complexity of computation.
Process 1500 then continues to a decision step 1516, where it is determined whether the currently selected line is the last line of the image (i.e., all lines have been selected). If the line is not the last line of the image, the process 1500 returns to step 1502. If the line is the last line of the image, the process 1500 ends.
In an exemplary embodiment, the hardware necessary to implement process 1500 comprises 6 xor gates, 3 accumulate registers, 3 comparison registers, 2 flag bits per line, and some state machine logic.
While the above processes 1300, 1400, and 1500 are described in the detailed description as including certain steps and are described in a particular order, it should be recognized that these processes may include additional steps or may omit some of the steps described. Further, each of the steps of the processes does not necessarily need to be performed in the order it is described.
While the above detailed description has shown, described and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from the spirit of the invention. As will be recognized, the present invention may be embodied within a form that does not provide all of the features and benefits set forth herein, as some features may be used or practiced separately from others.