Claims
- 1. A system for transferring messages, comprising:
a first processor using a first data transfer protocol; a second processor using a second data transfer protocol; and non-volatile memory in communication with said first and second processors, resettably and logically decoupled from the first and second processors, storing messages being transferred between the first and second processors to ensure message recoverability in the event of a loss of communication between the second processor and the non-volatile memory.
- 2. The system of claim 1 further comprising a register for storing the state of message transfer between the first and second processors.
- 3. The system of claim 1 wherein the non-volatile memory ensures message recoverability by reestablishing communication with the second processor without the loss or doubling of messages after a loss of communication.
- 4. The system of claim 1 wherein the non-volatile memory stores messages in queues.
- 5. The system of claim 1 further comprising a plurality of second processors in communication with said non-volatile memory, each having independent access to the queues, including the same queues.
- 6. The system of claim 5 wherein the second processors are brought on-line at unscheduled times.
- 7. The system of claim 1 wherein the non-volatile memory is resettable independently of the first and second processors.
- 8. The system of claim 1 further comprising a local power source for providing power to the non-volatile memory to maintain messages stored prior to an interruption in system power.
- 9. The system of claim 8 wherein the local power source provides power for at least two minutes.
- 10. The system of claim 8 wherein the local power source provides power for at least 30 seconds.
- 11. The system of claim 1 wherein the second processor selectively obtains access to the messages in the non-volatile memory.
- 12. The system of claim 1 wherein the non-volatile memory retains messages after the transfer of messages between the first and second processors.
- 13. The system of claim 12 wherein the messages are stored in the non-volatile memory until instructed to reset.
- 14. The system of claim 1 wherein the non-volatile memory improves message transfer efficiency between said first and second processors by storing messages to provide block of message transfers.
- 15. The system of claim 1 further comprising means for detecting the loss of communication between the second processor and the non-volatile memory.
- 16. The system of claim 1 wherein the first data transfer protocol executes single message-by-single message transfers.
- 17. The system of claim 1 wherein the second data transfer protocol executes blocks of message transfers.
- 18. The system of claim 17 wherein each block includes up to about 100 messages.
- 19. The system of claim 17 wherein the rate of block message transfer is improved by as much as five times over single message-by-single message transfers.
- 20. The system of claim 1 wherein the first and second processors and non-volatile memory are on a single computer card attaching to the backplane of a computer.
- 21. A method for transferring messages between a first and at least one second processor comprising:
using a first data transfer protocol, transferring messages between the first processor and non-volatile memory; storing the messages in non-volatile memory; and using a second data transfer protocol, transferring messages between the non-volatile memory and a second processor, the non-volatile memory (a) being resettably and logically decoupled from said first and second processors and (b) ensuring message recoverability in the event of a loss of communication between the second processor and the non-volatile memory.
- 22. The method according to claim 21, wherein the transferring of messages is done in the reverse order to transfer messages from the second processor to the first processor.
- 23. The method according to claim 21 wherein the messages in the non-volatile memory are in queues.
- 24. The method according to claim 21 further including storing the state of transfer of messages between the first and second processors.
- 25. The method according to claim 21 wherein transferring messages between the second processor and non-volatile memory supports losing communication and reestablishing communication in a manner without the loss or doubling of messages.
- 26. The method according to claim 25 wherein reestablishing communication includes retrieving message transfer status.
- 27. The method according to claim 21 wherein transferring messages includes transferring messages between the non-volatile memory and a plurality of second processors.
- 28. The method according to claim 21 further comprising resetting the non-volatile memory independently of the first and second processors.
- 29. The method according to claim 21 further comprising providing a local power source to provide power to the non-volatile memory in the event of a power loss.
- 30. The method according to claim 29 wherein the local power source provides power for at least two minutes.
- 31. The method according to claim 29 wherein the local power source provides power for at least 30 seconds.
- 32. The method according to claim 21 wherein transferring messages between the second processor and non-volatile memory includes selectively obtaining access to the messages in the non-volatile memory.
- 33. The method according to claim 21 wherein storing messages includes retaining messages after the transfer between the first and second processors.
- 34. The method according to claim 33 wherein storing messages includes storing the messages in the non-volatile memory until instructed to reset.
- 35. The method according to claim 21 wherein storing messages rather than transferring messages directly between the first and second processors improves message transfer rate for at least one of the processors.
- 36. The method according to claim 35 wherein storing messages rather than transferring messages directly between the first and second processor improves the message transfer rate by at least a factor of about five .
- 37. The method according to claim 21 further comprising detecting loss of communication between the second processor and the non-volatile memory.
- 38. The method according to claim 21 wherein the first data transfer protocol executes single message-by-single message transfers.
- 39. The method according to claim 21 wherein the second data transfer protocol executes blocks of message transfer s.
- 40. The method according to claim 21 wherein transferring messages between the second processor and non-volatile memory comprises transferring a queue of messages to one second processor and the same queue to another second processor.
- 41. An adapter for transferring messages between a mainframe computer and a second processor, comprising:
a first processor using a first message transfer protocol; non-volatile memory in communication with the mainframe and second processor, resettably and logically decoupled from the mainframe and second processor, storing messages being transferred between the mainframe and second processor to ensure message recoverability in the event of a loss of communication between the second processor and adapter; and a connector using a second message transfer protocol.
- 42. The adapter of claim 41 further comprising a local power source for providing power to the non-volatile memory to maintain messages stored prior to an interruption in system power.
- 43. The adapter of claim 42 wherein the local power source provides power for at least two minutes.
- 44. The adapter of claim 42 wherein the local power source provides power for at least 30 seconds.
- 45. The adapter of claim 41 further comprising a register for storing the state of message transfer between the first and second processors.
- 46. The adapter of claim 41 wherein the non-volatile memory ensures recoverability by reestablishing communication with the second processor without the loss or doubling of messages after a loss of communication.
- 47. The adapter of claim 41 further comprising a sensor for detecting a loss of communication between the adapter and second processor.
- 48. The adapter of claim 41 wherein the non-volatile memory stores messages in queues.
- 49. The adapter of claim 41 wherein the adapter is resettable independently of the mainframe and second processors.
- 50. The adapter of claim 41 wherein the second processor selectively obtains access to the messages in the non-volatile memory.
- 51. The adapter of claim 41 wherein the non-volatile memory retains messages after the transfer of messages between the mainframe and second processors.
- 52. The adapter of claim 41 wherein the messages are stored in the non-volatile memory until instructed to reset.
- 53. The adapter of claim 41 wherein the adapter improves message transfer efficiency between said first and second processors by storing messages to provide block of message transfers.
- 54. The adapter of claim 41 wherein the first data transfer protocol executes single message-by-single message transfers.
- 55. The adapter of claim 41 wherein the second data transfer protocol executes blocks of message transfers.
- 56. The adapter of claim 55 wherein each block includes up to about 100 messages.
- 57. The adapter of claim 55 wherein the rate of block message transfer is improved by as much as five times over single message-by-single message transfers.
- 58. The adapter of claim 41 wherein the adapter is a single computer card attaching to the backplane of a message transfer unit.
- 59. The adapter of claim 58 wherein the message transfer unit is a message queue server.
- 60. The adapter of claim 59 wherein the message queue server emulates a tape drive.
RELATED APPLICATION(S)
[0001] This application claims the benefit of U.S. Provisional Application No. 60/209,054, filed Jun. 2, 2000, entitled “Enhanced EET-3 Channel Adapter Card,” by Haulund et al.; U.S. Provisional Patent Application No. 60/209,173, filed Jun. 2, 2000, entitled “Message Director,” by Yarbrough; and is related to co-pending U.S. Patent Application, filed concurrently herewith, Attorney Docket No. 2997.1004-001, entitled “Message Queue Server System” by Yarbrough; the entire teachings of all are incorporated herein by reference.
Provisional Applications (2)
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Number |
Date |
Country |
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60209054 |
Jun 2000 |
US |
|
60209173 |
Jun 2000 |
US |