The present disclosure generally relates to designs for amplifier circuits.
Modern analog applications require high gain and high speed operational transconductance amplifiers (OTAs). However, advanced nanometer-scale technology nodes face challenges in meeting such requirements. While recent design efforts have been focused on proposing different techniques and topologies to overcome the limitations of such scaled-down technologies, there is room for improvements.
In accordance with one aspect, there is provided an amplifier circuit. The circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port Vout to form a differential input stage and N subsequent gain stages, a capacitive load CL coupled to the output port Vout, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ωt of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ωt.
In some embodiments, the compensation network is further configured for positioning the Pole-Zero pairs of each stage of the multi-stage amplifier above a 3 dB frequency ωP0 of the multi-stage amplifier when compensated so as to increase a load-drive capability of the multi-stage amplifier.
In some embodiments, the capacitive load CL is in a range of pF to μF.
In some embodiments, the capacitive load CL is in a nF range.
In some embodiments, the multi-stage amplifier is a Miller RC differential-ended two-stage operational transconductance amplifier.
In some embodiments, N is an integer from 2 to 8.
In some embodiments, each of the N subsequent gain stages is a replicated common source gain stage.
In some embodiments, each of the N subsequent gain stages produces a same direct current (DC) gain as remaining ones of the N subsequent gain stages.
In some embodiments, each common source gain stage has a DC gain between about 20 dB and about 25 dB.
In some embodiments, the compensation network comprises a plurality of compensation circuits, with a compensation circuit being provided for each stage of the multi-stage amplifier, and further wherein values of the compensation circuit for a 2-stage amplifier are scaled to size the compensation circuit of higher stages.
In some embodiments, the compensation circuit for each stage of the multi-stage amplifier is a multi-Miller RC compensation circuit, the plurality of compensation circuits configured to create paths between inputs and outputs of all stages of the multi-stage amplifier.
In some embodiments, the multi-stage amplifier comprises a plurality of compensation resistors and a plurality of compensation capacitors, further wherein, when a new stage is added to the multi-stage amplifier, a size of the compensation resistors of preceding stages of the multi-stage amplifier is reduced to increase a frequency of Zeros of the new stage and a size of the compensation capacitors of the preceding stages is increased to decrease a frequency of Poles of the new stage.
In some embodiments, each stage higher than the second stage comprises a compensation capacitor sized to a minimum capacitance value identified for the 2-stage amplifier.
In some embodiments, the multi-stage amplifier comprises at least one common-mode feedback circuit configured to apply biasing voltages to outputs of the stages of the multi-stage amplifier.
In some embodiments, for N s 3, the at least one common-mode feedback circuit comprises a first common-mode feedback circuit connected to an output of the second stage of the multi-stage amplifier.
In some embodiments, for N=2, the first common-mode feedback circuit is connected to an output of a second stage of the multi-stage amplifier.
In some embodiments, for N=3, the first common-mode feedback circuit is connected to an output of a third stage of the multi-stage amplifier.
In some embodiments, for N≥4, the at least one common-mode feedback circuit further comprises a second common-mode feedback circuit, the first common-mode feedback circuit connected to an output of a third stage of the multi-stage amplifier and the second common-mode feedback circuit connected to an output of each additional stage following the third stage.
Features described herein may be used in various combinations, in accordance with the embodiments described herein.
Reference is now made to the accompanying figures in which:
It will be noted that throughout the appended drawings, like features are identified by like reference numerals.
The present disclosure is directed to design techniques for enhancing the DC gain of operational amplifiers while nullifying the effects of parasitics and coupling introduced when using pole-splitting as a frequency compensation technique. The design techniques involve positioning the poles and zeros below the unity gain frequency ωt in the open-loop response of the operational transconductance amplifier (OTA) such that when closing the loop, they create a closed-loop pole-zero doublet that is clustered below the high frequency closed loop pole located at ωt. The lower the frequency of the zeros, regardless of the low frequency poles location (whether they are at DC and/or at low frequencies), the better the performance. The zeros are positioned lower than the poles in order to boost the unity gain frequency. With large gain amplifiers, the excess residual tail response time, due to the closed-loop Pole-Zero (P-Z) doublet, can be minimized to provide a single-time-constant response, using a trade-off between speed and loads. By cascading a plurality of OTA stages, the gain can be increased and the delay caused by the closed-loop P-Z doublets can be minimized. The capacitive load can range from pF to nF.
In one embodiment, a scalable OTA design is described that maintains stability in closed-loop applications while enabling the cascade of many OTA gain-stages. The design uses a Frequency Compensation Technique (FCT) that enables stable scalability through systematic positioning of the poles and zeros of the many-stage OTA circuit.
As previously noted, the purpose of the proposed architecture is to provide a uniform scalable DC gain, where each gain-stage produces the same DC gain. Hence, it is proposed to bias all gain stages at the same voltage, and for all transistors' sizes of the CS gain stages to be identical. The gain stages are biased with the current mirror transistors being used MCM, M5 and M7,i for the ith gain stage, with i=2, . . . , N (see
The circuit uses a differential-ended configuration. In
where Ai is the gain provided by the ith gain stage, with Ai=gmRO, gm is the transconductance of each stage, RO is the output resistance of each stage and N is the number of stages needed to achieve the required DC gain.
In some embodiments, N=8 and the architecture provides a scalable DC gain in the range of 50 dB to 200 dB with an increment of 25 dB per stage. In some embodiments, other increments are used per stage, such as, but not limited to, 20 dB or a value substantially close to 20 dB. Therefore, each stage is designed to achieve a DC gain of a given value (including the differential input-stage), which determines the required sizes of all transistors to meet power consumption and overdrive voltage requirements. The DC gain per stage also defines the values of the small-signal parameters (i.e. gm and RO) of all transistors.
The open-loop input-output transfer function of the circuits of
where AO,N is the DC gain of the required number of stages, ωP0 is the 3-dB frequency, ωPi and ωZi are the frequencies of open-loop Pole-Zero Pairs (P-ZPs) which are produced by the compensation circuit of each stage, with ωPi being the frequency of the ith pole and ωZi being the frequency of the ith zero.
Usually, in conventional FCTs, these P-ZPs are either pushed to frequencies much higher than ωt or positioned at the same exact frequency to get full P-Z cancellation. However, these conventional FCTs are associated with many disadvantages that prevent most proposed designs from scaling beyond 4-stages. Unlike conventional FCTs, the goal of the proposed scalable FCT is to position the open-loop P-ZPs at frequencies below ωt and above ωP0, without P-Z exclusion or cancellation, such that:
ωP0<ωz1<ωP1<ωz2<ωP2< . . . <ωzi<ωPi<ωt (3)
By doing so, the unity-gain frequency is no longer equal to the Gain-Bandwidth Product (GBP), but it is now given by:
To position the P-ZPs according to Eqn. (3), one can size the R-C compensation circuit based on the exact equations for each pole and each zero. This can be done for the 2- and 3-stage OTAs. However, moving to the 4-stage and higher OTAs, using these equations may become complicated as the coupling between stages becomes more significant. Accordingly, the proposed FCT avoids such levels of complexity by designing the compensation circuit of the 2-stage OTA first (i.e. RC1,(2-stage.) and CC1,(2-stage.)) and then scaling these values for higher stages.
According to equation (2), the OTA may have a different number of poles and zeros based on the value of N. For example, according to
where CO,1 represents the total shunt capacitance to ground on the output node of the first stage of the OTA (i.e. is the total parasitic capacitance seen at the input of the second stage), CL represents the capacitive load, CC1 represents the compensation capacitor of the first stage, RC,1 represents the compensation resistor of the first stage, gm,2 represents the transconductance of the second stage, RO,1 represents the output resistance of the first stage, RO,2 represents the output resistance of the second stage.
When designing the 2-stage OTA 202, the upper limit of ωt, which is the third (parasitic) pole ωP_Parastric, is defined as:
as there is no design control over this parasitic pole. This upper value—which depends on the technology node—will determine the mechanism of scalability for higher stages. According to Eqn. (4), one can increase ωt by increasing AO,2 (i.e. the DC gain for N=2), ωP0, ωP1 and reducing ωZ1. However, since AO,2 has already been selected based on the designed-for gain of the system, and ωP1 is fixed for a certain CL (here assumed to be 1 pF), one can increase ωt by increasing ωP0 and decreasing ωZ1.
In one embodiment, increasing ωt can be achieved by increasing ωP1, or, in other words, by reducing the value of CC1 according to Eqn. (6). The new position of ωP1 after reducing CC1 is shown (in solid lines) in
To re-position ωZ1 according to Eqn. (3) and shift it from higher to lower frequencies as seen in
where θP,i is the phase of the ith-pole and θZ,i is the phase of the ith-zerd.
To achieve this at the circuit level, and according to Eqns. (5) and (7), one can start with a minimum value of CC1,(2-stage) (e.g., that is at least five times the maximum parasitic capacitance) given by a certain CMOS technology (i.e., slightly higher than CO,1). Then, RC1,(2-stage) (˜kΩ) is increased in value to achieve the required PM so that (ωt≤ωP_Parasitic), or until the value of RC becomes impractical in the given CMOS technology. This may allow the R-C circuit to occupy a small-silicon area. Also, increasing ωt should be done such that the Phase Margin (PM) is greater than some desired value. At this point the design of the 2-stage OTA 202 is complete and values of CC1,(2-stage) and RC1,(2-stage) are shown in Table I.
To design the 3-stage OTA, a new gain-stage is added to the 2-stage OTA, as depicted in
Instead of deriving new equations for the poles and zeros for each stage separately, and by knowing that the P-ZPs have an inverse relationship with RC and CC, the values which were found for the 2-stage OTA can be scaled to size the compensation circuits of higher OTA stages. Since the poles and zeros are positioned according to Eqn. (3) and since the maximum ωt is defined, the sizes of the R-C compensation circuit components follow a certain pattern in order to position the P-ZPs when a new gain-stage is added. This scalable pattern can be seen in Table I and can be described as follows: whenever a new stage is added, the compensation resistors of the previous stage are reduced to increase the frequency of the zero of the new OTA stage, and hence reduce ωt to its previously defined upper limit. Then, the values of the compensation resistors can be sized according to the following constraints:
R
Ci,(N-stage)
≤R
Ci,[(N-1)-stage],1≤i≤N−1 (10)
and
R
C(N-1),(N-stage)
≤R
C(N-2),(N-stage) (11)
where the new compensation resistor (i.e. RC(N-1),(N-stage)) is initially sized according to the condition defined in Eqn. (11) to ensure that the new arrangement of the zeros follows the condition defined in Eqn. (3). For the compensation capacitors, the opposite pattern is followed. Whenever a new stage is added, the compensation capacitors of the previous stages are increased in size to decrease the frequency of the poles of the new OTA stage, and hence help in reducing ωt. The values of the compensation capacitors found for the 2-stage OTA can be adjusted according to the following constraint equations:
C
C(i-1),(N-stage)
=C
C(i-2),[(N-1)-stage]=,3≤i≤N (12)
and
C
Ci,(N-stage)
>C
i,[(N-1)-stage],1≤i≤N−1 (13)
Then, the new compensation capacitor (i.e. CC(N-1),(N-stage)) is sized to the minimum capacitance value, which was found for the 2-stage OTA, as follows:
C
C(N-1),(N-stage)
=C
C1,(2-stage) (14)
Since the constraint equations in Eqns. (10) to (13) show an intuitive technique of sizing the R-C compensation circuits for N≥3, and since there is no need for exact positioning of the poles and zeros, one can tweak these patterns to enhance the open-loop and closed-loop responses if necessary. For example, such tweaking can be done if an exact PM of 60° is required under CL,min of 0.5 pF. At this point the proposed scalable N-stage CMOS OTA is compensated to drive CL,min under the required PM. Also, as seen in
Table I shows an example of the sizes of the compensation resistors (RC) and compensation capacitors (CC) for the different OTA stages. Apart from RC4 in the 5-stage OTA, which is increased for better PM, all sizes follow Eqns. (10) and (14).
The approach described above may thus be used to obtain high DC gain through systematic positioning of the poles and zeros of the many-stage OTA circuit. As will be described further herein, the capacitive load (CL) driving capability of any conventional CMOS OTA with an R-C network may be extended, from the pF range to the nF range, with near-optimum small and large signal time responses. The implementation of the proposed FCT to maximize CL for a desired settling time (referred to herein as step (2)) will now be described. As described further herein, this is achieved by positioning the Pole-Zero Pair (P-ZP), created by the R-C compensation network, below the unity-gain frequency (ωt) of the compensated OTA. On doing so, the P-ZP increases the value of ωt for the compensated OTA. This additional increase in ωt would then be traded-off for the capability of being able to drive higher loads, by placing the dominant pole at a higher frequency. This positioning of the P-ZP requires the compensation resistor (RC) to be the dominant element of the chip size, while requiring the compensation capacitor (CC) to be near the value of parasitic capacitances in the circuit. Accordingly, an area-efficient design is achieved.
The objective is to modify the positioning of the poles and the zeros of the two-stage OTA so that the capacitive load driving capability and the unity-gain bandwidth of the OTA are maximized, with the OTA exhibiting a stable closed-loop response. This is further constrained by requiring the settling time of a unity-gain closed-loop configuration to be bound by some value denoted by TSD. This can be mathematically expressed as follows:
where ωt,initial is the initial value of the unit gain frequency ωt.
It should be noted that this problem includes both small and large-signal effects. Eqn. (15) contains a two-dimensional objective function involving ωt and CL, which are inversely inter-dependent. That is, if CL increases, ωt decreases. This makes it difficult to identify the maximum. Instead, this design problem can be performed in two steps using the following sequential, non-iterative procedure. The first step is to solve the problem expressed as:
This can be performed using small-signal AC analysis, and hence takes little time to perform with a transistor-level simulator. This step places the poles and the zeros at desired frequency locations for maximum ωt while having the minimum required capacitive load, CL,min, (say 0.5 pF). Next, a transient analysis is performed on the OTA in a closed-loop configuration subject to an input step Vin with different load conditions, i.e.:
While this can be executed in a sequential, non-iterative manner, the result is not optimal but orders of magnitude simpler to implement with improved results.
According to Eqn. (21) below, and since AO is pre-defined, the first step of boosting ωt, initial is achieved by increasing ωP1, or, in other words, by reducing the value of CC. The new value of ωt, initial will be referred to as ωt, boosted. Pushing ωP1 to higher frequencies, by continuing to reduce CC, allows ωP2 to become the 3-dB frequency of the OTA instead of ωP1. This may become useful when inserting the large CL. However, reducing the value of CC only is not a desirable design practice because it may alter the stability of the OTA; where ωP1 may move towards ωP2, and at the same time ωZ1 may shift to higher frequencies (as can be seen from Eqn. (16)). Therefore, the gain roll-off may drop to values around −40 dB/dec, and thus, the Phase Margin (PM) may also highly drop. But, if one can properly re-position ωZ1, after reducing CC, such that:
ωP2<ωZ1<ωP1<ωt,boosted (18)
The zero counteracts the effect of the two poles on the gain-roll-off and the PM. As a result, the stability issue can be controlled and the new ωt,boosted can be expressed as:
To re-position ωZ1 according to Eqn. (18), one can increase the value of RC. As a result, the impact of modifying the R-C compensation network, compared to the conventional design, is shown in
Since AO is pre-defined, and ωP2 is almost independent of the R-C network, Eqn. (19) indicates that the maximum value of ωt,boosted (i.e. near-optimum) can be achieved, ideally, by increasing ωP1 while decreasing ωZ1. However, the limitation of the upper value of ωt,boosted is ωP3, seen in Eqn. (15), as there is no design control over this parasitic pole. Also, increasing ωP1 while decreasing ωZ1 should be done so that the PM is greater than some desired value (see
To achieve this at the circuit level, one can start with the minimum possible value of CC given by a certain CMOS technology (i.e. slightly higher than the parasitic capacitance Cparasitics). Then, RC is increased in value so that (ωt,boosted≤ωP3), or until the value of RC becomes impractical in the given CMOS technology. Accordingly, with this, the first step of the design process, described by Eqn. (16), would have been completed.
Since the design achieved through step (1) was still loaded with a very small capacitance of 1 pF, the settling time of the closed-loop amplifier would be very short. Indeed it is assumed to be much shorter than the desired settling time TSD, and hence an increase in settling time can be traded-off for a higher CL. To find this limit, one sweeps on the step response of the closed-loop amplifier beginning with the 1 pF load and increases it until the desired settling time is reached. The input can be driven with a step input whose magnitude can be in the small or large-signal range. There are no constraints on the input condition. At this point, the maximum CL has been identified, and the final ωt becomes:
ωt,final=AOωP2 (20)
If ωt,final does not meet the requirements on TSD, one can re-adjust the reference design of the OTA by optimizing the biasing voltages and the aspect ratios. If this still does not allow ωt,final to meet the requirements on TSD, then a two-stage OTA is not suited for the given application.
Since the design achieved through step (1) is transferring the dependency of the dominant pole to ωP0 (i.e., CL,min), it is desirable to distinguish between compensating the OTAs with CL only and the proposed FCT. Interestingly, one can remove the R-C compensation circuit and rely only on CL to position ωP0 below ωt while leaving the P-Z pairs (i.e., ωP1, ωZ1, ωP2, ωZ2 . . . ωPi and ωZi) without being controlled. On doing so, the stability can be achieved once CL,min is increased such that ωt is shifted to frequencies much lower than the P-Z pairs. However, this technique is associated with some drawbacks. First, this technique is technology dependent, in other words, leaving the P-Z pairs without being controlled may allow the parasitic capacitances (which are technology dependent) to decide their frequency positions. Second, this technique works if a large CL,min is required (i.e., in the range of tens of nano-Farads). Also, this large CL,min is increasing with the addition of extra gain stages, due to the increase in AO,N (i.e., ωt). For these reasons and others, this dependency of the dominant pole on CL is not a desirable design practice in some embodiments. Nevertheless, this will not be an issue in the proposed FCT, since the P-Z pairs have already been positioned at the required frequencies. Consequently, one can define the range of CL that prevents the P-Z pairs from alternating the OTA's stability. To capture the shortage of relying on CL only to compensate the OTA, and to discuss the advantages of the proposed FCT in increasing CL-drivability of the proposed OTA,
The PM is an open-loop parameter that can indicate the closed-loop step response behavior.
Starting with the design that was loaded with a very small CL (i.e., CL,min=0.5 pF) and achieved a sufficient PM (say 60°), the impact of increasing CL on the PM can be investigated. According to Eqn. (5), increasing CL,min will result in shifting ωP0 to lower frequencies, thus, shifting ωt to lower frequencies as well. As can be seen in
As illustrated in
Still referring to
Still referring to
Since the P-Z pairs will have no impact on ωt in this region, the unity-gain frequency will be referred to as ωt,final (seen in
According to Eqn. (17), the range of CL that corresponds to a desired settling time will now be defined. For a design loaded with a very small capacitance (i.e., CL,min=0.5 pF), the settling time (TS,initial) of the closed-loop amplifier would be very short. Indeed, it is assumed to be much shorter than the desired settling time TSD, and hence an increase in settling time can be traded-off for a higher CL. Knowing that TSD is widely varying based on the required application, one can define a range of CL's that corresponds to a range of different settling time values by searching on the step response of the closed-loop amplifier beginning with CL,min. This can be simply done by increasing CL, starting from CL,min, until the desired settling time is reached, as long as CL≤CL,max. At this point, the desired CL (CL,desired) can be identified. Here, Vin can be driven with a step input whose magnitude can be in the small or large-signal range. There are no constraints on the input condition. Increasing CL, starting from CL,min, may result in different closed-loop responses based on the P-Z pair's positions, as can be seen on the right hand side of
Referring now to
To verify the proposed scalable OTA design, simulations were performed where the proposed 2-, 3-, and 4-stage OTA designs have been compared with previously reported different OTA designs. Measurement-based works, where CMOS OTAs can drive a wide range of CLS (i.e., not only a single CL driving capability), have been reported.
The results of the comparison highlight the need for an OTA with wide-ranging drivability features, even if the OTA settles in seconds.
For the purpose of comparing the present design method with prior design methods, a small signal figure-of-merit (FOMS) and a large signal figure-of-merit (SIFOML) are defined as:
The comparison shows that the proposed 3-stage OTA outperforms other reported works in FOMS and SIFOML, then comes the proposed 2-stage OTA. As for the proposed 4-stage OTA, it outperforms other 4-stage designs in its FOMS, but it has a low SIFOML at CL,max=100 μF due to the long settling time of such large CL. Also, looking at the OTAs' metrics individually, one can see that the proposed 4-stage OTA has the highest CL,max of 100 μF. Moreover, the proposed 3-stage and 4-stage OTA have the maximum CL drivability of 1,000,000×, followed by the proposed 2-stage OTA with a CL drivability of 10,000×. Finally, the proposed differential-ended 2-stage OTA occupies the smallest silicon area of 0.0021 mm2.
To further verify the proposed design technique, the standard TSMC 65 nm CMOS process was used to design the OTA of
For the 2- and 3-stage OTA, the CMFB circuit of
Once the OTA is designed for the required DC gain, the proposed FCT is verified by designing the compensation circuits according to steps (1) and (2) (i.e., Eqns. (16) and (17)), so that ωt is enhanced to a near-optimum value to allow the OTA to drive a wide CL range.
The proposed FCT starts by designing the 2-stage OTA's R-C compensation circuit (according to step (1)) having CL,min=0.5 pF. Therefore, the value of CC1,(2-stage) has been selected to be almost 5 times the value of the parasitic capacitance given by the technology (i.e. CC1=50 fF). For RC1,(2-stage), the value has been swept starting from 1 kΩ, and kept increasing till RC1,(2-stage) reached a value of 21 kΩ. Thus, ωt has become 293.2 MHz. This value of ωt is near optimum as PM=70.9°, which is a reasonable value to indicate stability. The frequency positions of the poles and the zero after designing the 2-stage OTA's R-C circuit according to step (1) are shown in Table II below.
Clearly, these values are satisfying Eqn. (3) and the parasitic pole is twice the value of ωt. Following the scalable technique given by Eqs. (10) to (13), the R-C compensation circuits of the 3- and 4-stage OTAs are designed as shown in Table III below.
Based on these values, Table II shows all open-loop frequency parameters. Even though Eqn. (3) has not been fully satisfied for 3- and 4-stages, where some P-Z pairs are having ωPi at frequencies less than ωZi, the PM has reached values around 60°. Also, ωt is at high frequencies and the parasitic poles are still higher than ωt.
If a very large CL is required, one can increase the value of IM6,N to keep the SR within sufficient values. However, by designing the OTA to have a high IM6,N, the power consumption may increase. This will become a trade-off between CL, SR, and power consumption. The post-layout power consumption in the proposed designs is 106 μW, 180.1 μW, and 243.5 μW for the 2-, 3-, and 4-stage OTAs, respectively. Also, one should consider that this value is for a fully differential-ended topology.
Even though many resistors are being used in the proposed OTAs, the noise has not been affected that much, because the resistors mainly affect the noise of the output stage, while the 1st stage noise is the dominant noise. Therefore, the post-layout input referred noise at 10 kHz is 82.2 nV/√Hz for the 2- and 3-stage OTAs and 78.1 nV/√Hz, for the 4-stage OTA.
After designing the proposed OTAs to properly drive CL,min of 0.5 pF, the goal is to define the range of CL under which the 2-, 3-, and 4-stage OTAs' closed-loop responses are stable, and to find the corresponding settling time for this range of CL. Therefore, similar steps of creating
As for the proposed 3-stage OTA, the closed-loop response is always stable as the PM does not reach the instability region (i.e., shaded area 702 of
As for the proposed 4-stage OTA, the PM behavior follows Case (3) of
To clearly measure the improvement that has been done by the proposed FCT on CL-drivability of CMOS OTAs, one can compensate the proposed OTAs with the conventional FCT (i.e., which relies on CL only to compensate the OTA) and compare the results.
The results in
Subsequently,
By comparing these measurement results with the schematic and post-layout simulation results found during the verification, one can conclude that these results are in general agreement with one another. Thus, the proposed FCT is being applied properly. It should be noted, however, that the 4-stage OTA has a CL,1 and CL,2 values that is slightly different than what was predicted by simulation, i.e., 40 pF versus 100 pF for CL,1, and 100 nF versus 10 nF for CL,2.
To ensure the robustness of the proposed design, excessive process corners and Monte-Carlo (MC) simulations have been conducted for different OTAs' parameters, under different CL'S, in open-loop and closed-loop configurations. This was conducted for both schematic-based and post-layout-based designs.
As can be seen in Table VI, all process corners, for all metrics, indicates no unforeseen sensitivity issues. It is clear from these simulations that the proposed OTA design is highly robust under PVT variations.
The above demonstrates that it is possible to extend the load driving capability of conventional Miller-RC CMOS OTAs by positioning the compensation network's P-ZP in a way that increases the OTA's ωt. The additional increase in ωt can then be traded-off for higher loads by transferring the dependency of the dominant pole to CL. As described herein, the technique of providing a compensation network coupled to a multi-stage amplifier using “low-frequency zeros” is applied. The compensation network is configured to position Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ωt of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ωt. The resulting amplifier circuit is shown to have enhanced gain, near optimum small- and large-signal time responses, and the ability to drive large capacitive loads.
The design techniques as described herein are applicable to any feedback system having a transfer function behaviour, such as but not limited to servo loop systems, quantum computing, neural networks, analog-to-digital converters, digital-to-analog converters, and the like.
Although the embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
This patent application claims priority of U.S. provisional Application Ser. No. 63/190,961, filed on May 20, 2021, the entire contents of which are hereby incorporated by reference.
Number | Date | Country | |
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63190961 | May 2021 | US |