Embodiments of this invention relate to switching networks used in an interconnection fabric and, in particular, can be used with programmable logic circuits.
A programmable logic circuit, also referred to as field programmable gate array (FPGA) is an off the shelf integrated logic circuit which can be programmed by the user to perform logic functions. Circuit designers define the desired logic functions and the circuit is programmed to process the signals accordingly. Depending on logic density requirements and production volumes, programmable logic circuits are superior alternatives in terms of cost and time to market. A typical programmable logic circuit is composed of logic cells where each of the logic cells can be programmed to perform logic functions on its input variables. Additionally, interconnect resources are provided throughout the programmable logic circuit which can be programmed to conduct signals from outputs of logic cells to inputs of logic cells according to user specification.
As technology progresses to allow for larger and more sophisticated programmable logic circuits, both the number of logic cells and the required interconnect resources increases in the circuit. Competing with the increased number of logic cells and interconnect resources is the need to keep the circuit size small. One way to reduce the required circuit size is to reduce the interconnect resources while maintaining a certain level of connectivity. Therefore, it can be seen that as the functionality implemented on the chip increases, the interconnection resources required to connect a large number of signals can be quickly exhausted. The trade-offs are either to provide for a lower utilization of logic cells in a circuit while keeping the circuit size small or to provide more routing resources that can increase the circuit size dramatically.
There has been steady attempts of using switching networks such as cross bar or Clos networks as the basis of an interconnection fabrics used in the field of programmable logic circuits. L. M. Spandorfer in 1965 describes possible implementation of a programmable logic circuit using neighborhood interconnection, and connections through multiple conductors using switches in a Clos network.
Reddy et al. in U.S. Pat. No. 6,417,694 discloses an architecture where inter-super-region, inter-region, and local conductors are used. A cross-bar scheme is used at the lowest level (using MUXs) for the local wires to have universal access to the inputs of the logic elements. Reddy et al. in U.S. Pat. No. 5,883,526 discloses various schemes having circuit reduction techniques in the local cross-bar.
Reblewski et al. in U.S. Pat. No. 6,594,810 describes an architecture building a programmable logic circuit using crossbar devices recursively. Wong in U.S. Pat. No. 6,693,456 and U.S. Pat. No. 6,940,308 use Benes switching networks as the interconnection fabric for programmable logic circuit.
At the base level of circuit hierarchy, multiple-input Look Up Table (LUT) logic cells are commonly used. There are two advantages in using a LUT as the base logic cell. One advantage is that the LUT allows programmable implementation of any Boolean functions having up to the multiple-input and one output. Another advantage is that the multiple inputs are interchangeable and logically equivalent. Hence, it does not matter which signal connecting to which input pin of the LUT for the LUT to function correctly as long as those signals connect to the respective inputs of the LUT.
A common problem to be solved in any programmable logic circuit is that of interconnectivity, namely, how to connect a first set of conductors or pins carrying signals to a second multiple sets of conductors to receive those signals where the logic cells originating the signals and the logic cells receiving the signals are spread over a wide area in an integrated circuit (i.e., M number of outputs from M or less number of logic cells where one or more outputs of each logic cells connects to inputs of one or more logic cells). A conventional solution is to use a cross bar switch where every conductor of the first set is connectable to every conductor in the second multiple sets of conductors directly through a switch. Unfortunately, this approach is impractical in most cases. Prior solutions in one degree or another try to divide the connectivity problem into multiple pieces using a divide and conquer strategy where local clusters of logic cells are interconnected and extended to other clusters of logic, either through extensions of local connections or using longer distance connections. These prior interconnect schemes are ad hoc and mostly based on empirical experiences. A desired routing model or interconnect architecture should enable or guarantee full connectivity for a large number of inputs and outputs over a large part of the circuit all the time.
U.S. Pat. Nos. 6,975,139, 7,256,614 and 7,417,457 by the present inventors describe one type of switching network (L-SN) of the conventional design in which the L-SN has (L+2) levels of conductors with L-level(s) of intermediate conductors of Ii number of conductors including D[i] sets of conductors for i=[1:L], L≧1 and Σi=[1:L+1](Ii−1×D[i]) number of switches where the 0-th level of pins or conductors of I0 number of pins or conductors selectively couple to the (L+1)-th level of pins or conductors of (D[L+1]×Πj=[1:L]D[j]) number of pins or conductors including D[L+1] sets of pins or conductors through the L level(s) of intermediate conductors and Σi=[1:L+1](Ii−1×D[i]) number of switches of the L-SN. A variable, DS[i] which is at least two, is defined as DS[i]=(Ii−1/Ii)×D[i] for i=[1:L+1]. A DS[i]-tuple is DS[i] number of conductors of the (i−1)-th level of conductors with the characteristics that the DS[i]-tuple selectively couple to one conductor, through a respective DS[i] number of switches, in each of the D[i] sets of conductors of the i-th level of conductors of the L-SN for i=[1:L+1]. Additionally, in the L-SN, the Ii−1 number of conductors of the (i−1)-th level can be organized into (Ii−1/DS[i]) groups of DS[i]-tuples for i=[1:L+1].
Two related patent applications by the present inventors, U.S. patent application Ser. No. 12/327,702 and U.S. patent application Ser. No. 12/327,704, disclosed alternative L-PSN with different switch coupling schemes operating on conductors between two consecutive levels of conductors where the permutable switching network (L-PSN) having Πj=[1:L+1](Ij−1×D[j]) number of switches and L-level(s) of intermediate conductors of Ii number of conductors having D[i] sets of conductors for i=[1:L] to connect the 0-th level of pins or conductors of I0 number of pins or conductors to the (L+1)-th level of pins or conductors of (D[L+1]×Πj=[1:L] D[j]) number of pins or conductors having D[L+1] sets of pins or conductors through the L level(s) of intermediate conductors and Σj=[1:L+1](Ij−1×D[j]) number of switches of the L-PSN with different switch coupling schemes from the conventional L-SN for L>1.
U.S. patent application Ser. No. 12/327,704 uses the same DS[i]-tuple definition in a L-PSN as those in the U.S. Pat. Nos. 6,975,139, 7,256,614 and 7,417,457. An L-PSN of this application uses the same DS[i]-tuple definition having the coupling characteristics of the DS[i]-tuples.
A weaker version of a DS[i]-tuple, denoted as W-DS[i]-tuple, is defined as DS[i] number of conductors of the (i−1)-th level of conductors which are selectively coupled to one conductor, through a respective DS[i] number of switches, in just one of the D[i] sets of conductors of the i-th level of conductors of the L-PSN for i=[1:L+1]. Thus a W-DS[i]-tuple which are selectively coupled to one of the D[i] sets of the Ii number of conductors can be different from any other W-DS[i]-tuple which are selectively coupled to a different set of the D[i] sets of conductors.
The labels Ii−1, Ii, DS[i], D[i] in
As an illustration of the conventional designs,
In the conventional L-SN and L-PSN designs illustrated in
Similarly, in the conventional L-PSN design illustrated in
The objectives, features, and advantages of the present invention will be apparent from the following detailed description in which:
A new L-level(s) permutable switching network (L-PSN) with L-level(s) of intermediate conductors of Ii number of conductors having D[i] sets of conductors for i=[1:L] to connect the 0-th level of pins or conductors of I0 number of pins or conductors to the (L+1)-th level of pins or conductors of (D[L+1]×Πj=[1:L]D[j]) number of pins or conductors having D[L+1] sets of pins or conductors through the L level(s) of intermediate conductors where at least (Ij−1×D[j]+Ij×Q) number of switches are used to selectively couple between (j−1)-th level of pins or conductors if Ij−1 number of conductors and the j-th level of pins or conductors with Ij number of conductors for an j selected from [1:L+1] and Q at least equal to one and Q is less than (Ij−1−DS[j]). An L-PSN of this application uses the same DS[i]-tuple and W-DS[i]-tuple definitions discussed above. Some of the differences of the L-PSN in this application, compared with the conventional L-SN or L-PSN are in the increased number of switches and the schemes in which those switches are used to couple two levels of conductors.
Some embodiments of the L-PSN of this application can be applied to a wide range of applications, as a L-PSN, either fully or used in conjunction with a conventional L-SN, L-PSN or other switching network schemes, to provide a large switch network that can be used in switching networks, routers, and programmable logic circuits. Some embodiments of the permutable switching network of this present invention provides enhanced connectivity or routability over the conventional design, including the handling multicasting signals.
In the following descriptions, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and circuits are shown in block diagram form in order to avoid unnecessarily obscuring the present invention. For purpose of description, unless otherwise specified, the terms program controlled switch and switch are interchangeable in the context of this description; the terms program configured logic cell, logic cell, cell, Look Up Table (LUT), programmable logic cell are interchangeable in the context of this description; the terms conductor, pin, line are interchangeable in the context of this description; signal, net, signal net are interchangeable in the context of this description which generally refers to a conductor carrying signal from a source to destination(s); while port and conductors or a set of conductors are interchangeable in the context of this description where a port has a set of pins or conductors. Thus a net associated with a conductor of a 0-th level of I0 number of conductors or pins generally carries a signal which is to be selectively connected, through a permutable switching network (L-PSN), to one or more conductors or pins, each of which is selected from one of the (L+1)-th level of conductors (D[L+1]×Πi=[1:L]D[i])) number of conductors including D[L+1] sets of conductors through L-level(s) of intermediate conductors of Ii number of conductors having D[i] sets of conductors for i=[1:L]. Thus it should be clear, for one skilled in the art, that the terms conductor, pin, line, signal, net are interchangeable depending on the context of this description. The terms, Ii conductors or Ii number of conductors, are generally referred to the conductors of the i-th level of conductors for i=[0:L+1] in the L-PSN and can be used either indicating of the number or set of conductors of the i-th level of conductors. The notations [ ] and ( ) sometimes are used interchangeably to indicate one or more objects (elements) such as conductors or pins being grouped together while D[i] or DS[i] are parameters associated with the switch couplings between the (i−1)-th level of conductors and the i-th level of conductors. It should also be noted that the present invention describes embodiments which use program control means to set the states of switches utilized, this control means can be one time, such as fuse/anti-fuse technologies, or re-programmable, such as SRAM (which is volatile), FLASH (which is non-volatile), Ferro-electric (which is non-volatile), etc. Hence the present invention pertains to a variety of processes, including, but not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), fuse/anti-fuse, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) such as FLASH, and Ferro-electric processes.
In some embodiments, the design and/or layout of the integrated circuits described above can be performed by a computing machine (e.g., a server, a personal computer, etc.) in response to instructions embodied in a machine-readable storage medium of an article of manufacture. Some examples of a machine-readable storage medium include any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus. Furthermore, data representing the design and/or layout of the integrated circuits described above can be embodied in a machine-readable storage medium of an article of manufacture.
When a program controlled switch is used to interconnect one conductor to another conductor, a driver circuit may be coupled to the switch to improve the speed of the signal traversing those conductors; thus a switch can be comprised of a driver circuit. Additionally, if multiple conductors (signals) fan-in to a conductor through program controlled switches, it is possible to use a MUX scheme, if desired, to either reduce loading on the conductor or to reduce circuit size, or both, depending on the process technology used. In the case where a MUX is used, the multiple switches are converted into a new switching mechanism where, the number of control states are the same as the number of switches; connectivity is enabled by choosing the particular state (corresponding to the switch when multiple switches were used) in connecting two conductors and the states are determined by program control; as an example, in a four to one MUX there are four states to control the selection of which one of the four inputs is connected to the one output hence each state corresponds to a respective switch which can be program controlled.
In this application, various alternative schemes of switch couplings operating on DS[i]-tuples or W-DS[i]-tuples between the (i−1)-th level of conductors and the i-th level of conductors are described to enhance connectivity or routing in the presence of multicasting signals. In many L-PSN illustrations in this application, a DS[i]-tuple (but not necessarily W-DS[i]-tuples) will be mostly drawn as having consecutively labeled numbers.
The new L-PSN has the following formulations:
For at least one i selected from [1:L+1] and Q is selected from [1:(Ii−1−DS[i]−1)],
PSN-(A): Each conductor of the Ii−1 number of conductors of the (i−1)-th level of conductors selectively couples to at least (D[i]+Q) number of conductors of the i-th level of conductors selected from at least one conductor in each set of the D[i] sets of conductors of the i-th level of conductors of Ii number of conductors through a corresponding number of switches.
PSN-(B): The Ii−1 number of conductors of the (i−1)-th level of conductors selectively couple to the conductors of each set of the D[i] sets of conductors of the i-th level of conductors through at least (Ii−1+(Ii/D[i])×Q) number of switches with a total of at least (Ii−1×D[i]+Ii×Q) number of switches coupling between the two levels of conductors.
For ease of discussions, the switches corresponding to the conventional designs in U.S. Pat. Nos. 6,975,139, 7,256,614 and 7,417,457 and the two related applications, U.S. patent application Ser. Nos. 12/327,702 and 12/327,704, will be denoted by squares in the figures and those Ii number of additional switches will be denoted by circles in the figures; additionally, when a switch is selected for use to connect two conductors, the corresponding square or circle denoting the switch is blackened in the illustrations.
It can be readily determined, for one skilled in the art, that each of the switching networks illustrated in the embodiments of
The switches represented by squares in the embodiment of
Similarly, the square switches in the new L-PSN with DS[i]=D[i]=4, Ii−1=Ii=32 and Q=1 illustrated in
It is readily determined, for one skilled in the art, that the eight nets where nets 101 and 102 each carries the same signal connection specification (0), connecting to a pin in the 0-th K-port; nets 103 and 104 each carries the same signal connection specification (1), connecting to a pin in the 1st K-port; net 105 carries the signal connection specifications (0,1), connecting to a respective pin in the 0-th K-port and the 1st K-port; with nets 106, 107 and 108 each carries the same signal connection specification (2), connecting to a pin in the 2nd K-port illustrated using
The eight nets example where net 101 carries the signal connection specifications (0,1,2,3), connecting to a respective pin in the 0-th K-port, the 1st K-port, the 2nd K-port and the third K-port; net 104 carries the signal connection specifications (1,2,3,4); net 107 carries the signal connection specifications (2,3,4,5); net 110 carries the signal connection specifications (3,4,5,6); net 113 carries the signal connection specifications (0,1,5,7); net 116 carries the signal connection specifications (0,4,6,7); net 119 carries the signal connection specifications (1,5,6,7) and net 122 carries the signal connection specifications (0,2,6,7) illustrated using
The same eight nets can be fully connected or routed using the L-PSN switching network illustrated in the embodiment of
Similarly, the signal connection specifications of the same eight nets example with 32 K-port pins can be routed using the new L-PSN illustrated in
In the new L-PSN illustration of
In the new L-PSN illustration of
It can be readily determined, for one skilled in the art, that there are multiple solutions for the eight nets example with 32 pins in the new L-PSN illustrated in
The various embodiments of the new L-PSN illustrated in
The various embodiments illustrated in
For i=1 and Q=1, a new L-PSN with four levels of conductors, I0, I1, I2 and I3, where I0=I1=I2=24 and I3=32 are illustrated in
In the localized cases, which are respectively illustrated in the embodiment 1 of
It can be readily determined, for one skilled in the art, that a larger granularity of conductors of the Ii number of conductors, e.g. ((Ii/Πj=[0:i]D[j])×T) for T>1, can selectively couple to a respective number of Ii+1 number of conductors, e.g. ((Ii+1/Πj=[0:i]D[j])×T), which are organized as D[i+1] sets of conductors of size ((Ii+i/Πj=[0:i+1]D[j])×T) each, through (T×((Ii/Πk=[0:i]D[k])+((Ii+1/Πk=[0:i+1]D[k])×Q))) number of switches for each of the D[i+1] sets, thus a total of (T×D[i+1]×((Ii/Πk=[0:i]D[k])+((Ii+1/Πk=[0:i+1]D[k])×Q))) number of switches. For example, the embodiment in 5 of
There are thus several ways of viewing the localized groupings of the Ii number of conductors of the i-th level of conductors for i=[1:L+1]: (1) The Ii number of conductors comprise D[i] sets of conductors having (Ii/D[i]) number of conductors in each of the D[i] sets of conductors; (2) the Ii number of conductors comprise Πj=[0:i]D[j] groups of conductors having (Ii/Πj=[0:i]D[j]) number of conductors in each group; and (3) the Ii number of conductors comprise D[i] sets of conductors where each of the D[i] sets of conductors comprise Πj=[0:i−1]D[j] groups of (Ii/Πj=[0:i]D[j]) number of conductors.
In the global case, the parameter “T” described above is the product sum of the prior D[j]s, namely, T=Πj=[0:i]D[j]; thus the Ii number of conductors of the i-th level of conductors selectively couple to D[i+1] set of conductors of the Ii+1 number of conductors with (Ii+1/D[i+1]) number of conductors in each set through a total of ((Ii×D[i+1])+(Ii+1×Q)) number of switches as illustrated in the embodiment of
The generalized L-PSN formulations illustrated so far always refers to (Ii−1+((Ii/D[i])×Q)) number of switches which are used to selectively couple the conductors of an (i−1)-th level of conductors of Ii−1 number of conductors to the conductors of one set of the D[i] sets of conductors of the i-th level of conductors of Ii number of conductors, where a subset of conductors of the (i−1)-level of conductors selectively couple to a subset of conductors of the i-th level of conductors prescribed by the formulations of PSN-(A) and PSN-(B) for at least one i selected from [1:L+1] and Q is selected from [1:(Ij−1−DS[j]−1)] in the L-PSN.
Based on the conventional designs described in U.S. Pat. Nos. 6,975,139, 7,256,614 and 7,417,457, switch couplings between two levels of conductors can have a minimum of (Ij−1−D[j]+1) number of switches for j≠i where j=[1:L+1] which selectively couple between the Ij−1 number of conductors of the (j−1)-th level of conductors and the conductors of each of the D[j] sets of conductors of the Ij number of conductors of the j-th level of conductors while the switch couplings between the (i−1)-th level of conductors and the i-th level of conductors meeting the PSN-(A) and PSN-(B) formulations can be viewed as a minimal new L-PSN. Thus an L-PSN can have many variations and the decisions to design a specific implementation of the L-PSN is generally based on the specific design or engineering objectives such as layout, speed and ease of software to handle routing, etc.
It can be readily determined, for one skilled in the art, that the embodiments of
It is readily clear, for one skilled in the art, that the schemes described in this application has DS[i] number of conductors of the (i−1)-th level of conductors selectively couple to at least (Q+1) conductors of each of the D[i] sets of conductors of the i-th level of conductors through (DS[i]+Q) number of switches (or alternatively the Ii−1 number of conductors selectively couple the Ii number of conductors through (Ii−1×D[i]+Ii×Q) number of switches) for Q selected from [1:(Ij−1−DS[j]−1)] meeting the PSN-(A) and PSN-(B) formulations.
The embodiment of
For the case where Ii−1=Ii, as illustrated in the embodiment of
It is readily obvious for one skilled in the art that most of the various embodiments illustrated so far illustrate the switch couplings between two levels of conductors; switch couplings between consecutive numbers of multiple levels of conductors can be constructed, with either the new schemes, the conventional schemes or a combination of schemes discussed in this application.
The L-PSN switching networks can be used in conjunction with other interconnection mechanisms to form an interconnection fabric, for programmable logic circuits such as Field Programmable Gate Arrays (FPGAs) or used in a general interconnection network such as a network router. When an L-PSN is too small, there is no appreciable advantage, in terms of switch count, compared with many alternative interconnection schemes of many conventional designs; for a 1-PSN, for example, both D[1] and D[L+1] should be at least three; for an L-PSN, at least one of the D[i] should be greater than two and DS[i] in general should be at least two where L is greater than one.
Thus the L-PSN scheme can be used to enhance the selective connectivity or routability of a netlist compared to a corresponding conventional L-PSN when there are one or more multicasting signals without adding more switches or conductors to the switching network. Using numerous embodiments and illustrations, a detailed description in building various enhanced multistage permutable switching networks is provided and used in various combinations to provide interconnect, both for inputs and outputs, for programmable logic circuits.
Thus, some embodiments of permutable switching network have been described. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
This is a continuation of application Ser. No. 12/491,089, filed Jun. 24, 2009 now U.S. Pat. No. 7,999,570, which is hereby incorporated by reference.
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Number | Date | Country | |
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20110267104 A1 | Nov 2011 | US |
Number | Date | Country | |
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Parent | 12491089 | Jun 2009 | US |
Child | 13179342 | US |