The present disclosure is related to methods and devices related to serial bus devices. More specifically, the present disclosure is directed to methods and devices providing for a serial bus controller that is able to interact with serial bus devices in parallel with a processor that is executing other operations.
Integrated circuits (ICs) are more expensive when they have more pins. To reduce the number of pins in an IC package, many ICs use a serial bus to transfer data. Some examples of such low-cost serial buses include SPI, I2C, UNI/O, and 1-Wire. The serial nature of the serial bus dictates that each device is queried in turn sequentially. During device startup or wake-up, there are a number of operations that need to be performed to boot up or wake up the device. This boot-up or wake-up process often includes checking the status (including existence) of various attached devices and writing to those devices.
Current System Management Bus configuration relies on a single controller in the southbridge to query every device in the system when the system BIOS requests information from those devices.
A subsequent device is not queried until the query of the previous device is completed. Similarly, instructions that need to be written out to devices from the CPU are done in a serial manner. Additionally, various devices sit idle during portions of startup as the CPU performs other operations. Both the idle time of the devices and the serial progression through the devices (querying and writing) incur a time cost that delays completion of a boot up sequence for a computing device. Clearly, the more devices in a given system, the larger boot time delay imposed thereby. Large server systems with multiple CPU's can have a larger number of DIMMs, for example 64 DIMMs or more, as well as additional devices to be queried. The time it takes to read all of those devices may cause an operator to think that the system is not booting up because there can be no display until after memory is initialized.
Accordingly, there exists a need for an improved method and apparatus that reduces the time incurred by serial progression through the devices.
There further exists a need for such improved method and apparatus that is compatible with existing serial architecture.
a is a diagram showing existing computing architecture;
b is a communication chart showing exemplary communications implemented on the architecture of
a is a diagram showing computing architecture employing a “Super Hub” of the present disclosure;
b is a communication chart showing exemplary communications implemented on the architecture of
a is a diagram showing another embodiment of computing architecture of the present disclosure;
b is a communication chart showing a first embodiment of communications implemented on the architecture of
c is a communication chart showing a second embodiment of communications implemented on the architecture of
d is a communication chart showing a third embodiment of communications implemented on the architecture of
In an exemplary and non-limited embodiment, aspects of the invention are embodied in a method and device for retrieving system data needed for boot up and/or wake-up. A bus hub is provided that retrieves needed data prior to such data being requested by the processor. The bus hub then stores the data. When a request is received for the data from the processor, the bus hub responds by sending the stored data.
Briefly, in one example, a method of providing information about at least one device to a processor is provided including storing a first piece of information about a first device at a bus hub; receiving a request from the processor for the first piece of information stored at the bus hub; and responding to the request by sending the stored first piece of information to the processor.
In another example, a method of enacting settings for at least one circuit device is provided including receiving first settings for a first device from a processor; storing the first settings at a bus hub; and issuing one or more instructions to the first device, the instructions, when received by the first device, enacting the first settings.
In yet another example, a bus hub is provided including a first input/output port operable to perform one or more of receiving queries from, receiving instructions from, and providing information to a processor; a second input/output port operable to perform one or more of sending queries to, sending instructions to, and receiving information from a system component; and a memory operable to perform one or more of storing information received from the system component and storing instructions received from the processor.
In still another example, a method of performing boot-up and/or wake-up is provided including: retrieving system information needed by a processor for boot-up/wake-up prior to such information being requested by the processor; storing the system information in a location accessible to the processor; receiving a request from the processor for the stored system information; and providing the stored system information to the processor.
In another example, a computer readable medium is provided containing non-transitory instructions thereon, that when interpreted by at least one processor cause the at least one processor to: request first information; and receive the first information from a bus hub, the bus hub having obtained and stored the first information prior to issuance of the request for the first information.
a&b are a diagram and communications chart, respectively, showing how the prior art handles devices. In sum, on power-up (or wake-up from a sleep mode or other reduced power setting) as part of a power-on self-test or otherwise—i.e., transition to an operational state from a non-operational state (that latter including a reduced operational state), CPU 10 and BIOS send out queries for attached devices 1, 2, 3, 4, 5, 6, 7, 8, etc. to determine what devices are connected to CPU 10. In one example, the queried devices 1, 2, 3, 4, 5, 6, 7, 8 are memory devices that utilize the Serial Presence Detect (SPD) standard. Herein, devices 1, 2, 3, 4, 5, 6, 7, 8 will be discussed as memory devices. However, it should be appreciated that the concepts discussed herein can be used for any System Management Bus compatible devices, including but not limited to those employing I2C (such as game consoles, PC's, servers, and mobile devices). Other non-limiting examples of suitable devices include a laptop's rechargeable battery subsystem, temperature sensors, fan sensors, voltage sensors, lid switches and clock chips.
As shown in
Turning now to
As shown in
Additionally, it should be appreciated that the embodiment of
a shows an embodiment where a separate bus 50 is supplied that directly connects CPU 10 to SM Super Hub 40. In the provided embodiment, bus 50 is a high speed bus that is faster than bus 48 between Main SM Bus Controller 15 and SM Hub 20.
d shows a communication chart for the hardware of
As previously noted, at power-up, SM Super Hub 40 does not wait for a query from CPU 10 to engage memory modules 5-8. At power-up SM Super Hub 40 begins to query memory modules 5-8. SM Super Hub 40 then stores the responses from memory modules 5-8 in storage 42. The querying of memory modules 5-8 is being done at the same time as CPU 10 is performing other boot operations. At the point when CPU 10 sends out a query for memory module 5, the response data is already present at storage 42 of SM Super Hub 40. Additionally, the query is sent directly to SM Super Hub 40 rather than being routed through SM bus Controller 15. SM Super Hub 40 thus responds to the query without having to query memory module 5 in between query from and response to CPU 10. Subsequent queries received by SM Super Hub 40 relating to memory modules 6-8 are similarly responded to.
b shows a communication chart for the hardware of
It should be appreciated that the compression techniques shown in
c shows another embodiment communication chart that while discussed with reference to the hardware of
Memory at CPU 10 stores state information for memory modules 5-8. Upon power-up or wake-up, SM Super Hub 40 queries modules 5-8 in the manner discussed above. SM Super Hub 40, via storage 42, also has an indication of the previous status reported to CPU 10. SM Super Hub 40 then compares the newly obtained state information for modules 5-8 with the previously reported state information.
At the point in the startup sequence where memory modules 5-8 are to be checked, CPU 10 issues a query to SM Super Hub 40 asking if there has been any change to the status of modules 5-8. If there has been no change, then SM Super Hub 40 can respond with that fact. CPU 10 then knows that it can use the values stored at CPU 10. If there has been a change, then SM Super Hub 40 replies by sending a compressed response that provides the status of each of modules 5-8. In this way, the query sent by CPU 10 is similar to a “Conditional Get” HTTP command with an implied “If modified since—last report” reference point. This construct both economizes the amount of data sent if there is no change and economizes on the data that is sent and how soon it is sent if there is a change to modules 5-8.
To this point, SM Super Bus 40 has been discussed as a device that queries devices 5-8 and reports back to CPU 10 to allow a serial bus architecture to achieve efficiencies more closely approximating parallel processing buses. The described architecture can also be utilized to distribute commands and writes from CPU. As shown in
Additional examples of the write functionality are shown in
The above detailed description and the examples described therein have been presented for the purposes of illustration and description only and not for limitation. For example, the operations described may be done in any suitable manner. The method may be done in any suitable order still providing the described operation and results. It is therefore contemplated that the present embodiments cover any and all modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and claimed herein. Furthermore, while the above description describes hardware in the form of a processor executing code, hardware in the form of a state machine, or dedicated logic capable of producing the same effect are also contemplated.
The software operations described herein can be implemented in hardware such as discrete logic fixed function circuits including but not limited to state machines, field programmable gate arrays, application specific circuits or other suitable hardware. The hardware may be represented in executable code stored in non-transitory memory such as RAM, ROM or other suitable memory in hardware descriptor languages such as but not limited to RTL and VHDL or any other suitable format. The executable code when executed may cause an integrated fabrication system to fabricate an IC with the operations described herein
Also, integrated circuit design systems/integrated fabrication systems (e.g., work stations including, as known in the art, one or more processors, associated memory in communication via one or more buses or other suitable interconnect and other known peripherals) are known that create wafers with integrated circuits based on executable instructions stored on a computer readable medium such as but not limited to CDROM, RAM, other forms of ROM, hard drives, distributed memory, etc. The instructions may be represented by any suitable language such as but not limited to hardware descriptor language (HDL), Verilog or other suitable language. As such, the logic, software, and circuits described herein may also be produced as integrated circuits by such systems using the computer readable medium with instructions stored therein. For example, an integrated circuit with the aforedescribed software, logic, and structure may be created using such integrated circuit fabrication systems. In such a system, the computer readable medium stores instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to produce an integrated circuit.