Patent Application
20090040842
The present disclosure relates generally to write abort mechanisms for use with non-volatile memory.
Binary and Multi-Level Cell (MLC) NAND Flash Memory are forms of non-volatile memory (NVM) that are capable of high data storage densities and high performance, however, a power failure due to hot removal, brownout, blackout or the like can cause data corruption or loss due to the nature of the way in which data is written to this type of memory. Typically a “page” or group of bits at a time is written to the NVM. If a power failure occurs during a write cycle/program operation, something less than all of the bits of the page may be programmed successfully in the NVM. When the page containing unsuccessfully programmed bits is read back, some bits will have the new value, some will have the old value and, as a result, the page will be corrupted. In some prior approaches, complex data structures and multiple copies of host data are kept on the NVM device to ensure graceful recovery under most circumstances. This approach, unfortunately, reduces performance and data storage densities. An NVM program cycle using Flash-type memory, for example, typically takes on the order of 0.5-10 mSec, depending upon the type of memory.
This problem can be addressed through the use of a backup or secondary power source arranged to directly power the NVM such as a battery or very large-valued capacitor (on the order of 1000's of uF), but these solutions are often costly or require too much space. An improved solution would be desirable.
In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/NVM program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal.
The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more examples of embodiments and, together with the description of example embodiments, serve to explain the principles and implementations of the embodiments.
In the drawings:
Example embodiments are described herein in the context of a non-volatile memory device of the type having a controller controlling the reading and writing of data from/to an associated non-volatile memory array. Those of ordinary skill in the art will realize that the following description is illustrative only and is not intended to be in any way limiting. Other embodiments will readily suggest themselves to such skilled persons having the benefit of this disclosure. Reference will now be made in detail to implementations of the example embodiments as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following description to refer to the same or like items.
In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.
In accordance with this disclosure, the components, process steps, and/or data structures described herein may be implemented using various types of operating systems, computing platforms, computer programs, and/or general purpose machines. In addition, those of ordinary skill in the art will recognize that devices of a less general purpose nature, such as hardwired devices, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herein. Where a method comprising a series of process steps is implemented by a computer or a machine and those process steps can be stored as a series of instructions readable by the machine, they may be stored on a tangible medium such as a computer memory device (e.g., ROM (Read Only Memory), PROM (Programmable Read Only Memory), EEPROM (Electrically Eraseable Programmable Read Only Memory), FLASH Memory, Jump Drive, and the like), magnetic storage medium (e.g., tape, magnetic disk drive, and the like), optical storage medium (e.g., CD-ROM, DVD-ROM, paper card, paper tape and the like) and other types of program memory.
In embedded applications of NVM, where hot removal is not a substantial issue (e.g., due to the memory device being relatively inaccessible, soldered in place, or the like) it is possible to leverage the inherent capacitance of the system (e.g., power supply capacitors and printed circuit board capacitance) to allow for successful completion of “pending” or in-process NVM program or write cycle.
Turning to
To utilize this feature of large power supplies, a voltage supervisor circuit 304, as shown in
In
In accordance with various embodiments, the voltage supervisor circuit 304 may be external to a package (such as, for example, a multi-chip module or other packaging technology supporting and interconnecting multiple circuit components) or die (i.e., a die from a semiconductor wafer) comprising the flash memory array 308 and controller 306 (the package or die receiving the low-voltage signal via an electrical coupling to the external voltage supervisor 310), or the voltage supervisor circuit 310 may be integrated into a package or die comprising the flash memory array 308 and controller 306, the voltage supervisor circuit 310 implemented as a part of the package or die itself, receiving the +Vcc and GND power signals from a power supply which is external to the package or die (e.g., from a host power supply 302). Similarly, the flash memory array 308 and the voltage supervisor 310 may be integrated together into a single package or die and coupled to an external controller 306. In such an implementation, a low-voltage condition is detected at the package/die comprising the array/voltage supervisor and the voltage supervisor signals back to the external controller 306. It is also contemplated that the controller 306 and voltage supervisor 310 may be integrated together in a single package/die apart from the flash memory array 308.
Note that in the implementation shown in
While embodiments and applications have been shown and described, it would be apparent to those skilled in the art having the benefit of this disclosure that many more modifications than mentioned above are possible without departing from the inventive concepts disclosed herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.
The present application may be considered to be related to co-pending U.S. patent application Ser. No. 11/______ filed on even date herewith (Attorney Docket No. SDA-1181X (060589-004), in the name of inventors Steven T. Sprouse, Dhaval Parikh and Arjun Kapoor, entitled “Enhanced Write Abort Mechanism for Non-Volatile Memory”, commonly owned herewith.
