ENHANCEMENT OF POWER ON RELIABILITY IN A DUAL POWER SUPPLY DIGITAL DEVICE WITH DOWN CONVERTER

Abstract

A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a basic circuit diagram of a down converting switching regulator for a digital device and of the input interfacing circuit for an I/O pad of the digital device according to the prior art.

FIG. 2 shows the same basic diagram of FIG. 1 modified according to the present invention.

FIG. 3 shows an alternative embodiment of the circuit arrangement of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

With reference to FIG. 2, a dual power supply digital device comprises a down converter that converts and externally applied supply voltage VDD in a regulated first supply voltage VDDIN for powering part of a logic circuitry of the digital device (core logic circuitry). A second externally applied supply voltage VDDQ is separately applied to a dedicated supply pad of the device for powering I/O buffers of the digital device. Therefore the information acquired through an input pad INPAD_N of the device at the logic reference voltage VDDQ needs to be replicated at the down converted regulated supply voltage logic reference level VDDIN at which the core logic circuitry of the digital device is powered.

As already discussed in relation to FIG. 1, this is commonly done for each input pad INPAD_N of the device by a voltage translator latch stage and by a second input buffer both powered at the regulated core supply voltage VDDIN. In practice, the latch replicates a stored inverted replica of the logic value present on the input pad INPAD_N onto the input node A of a second logic buffer powered at the regulated core supply voltage VDDIN, thus conveying the correct input logic value IN_N to the core circuitry of the digital device.

As readily identified by the portion drawn with heavier lines, according to this invention, a p-channel transistor TR1, having adequate voltage withstanding properties (preferably a high voltage type transistor with a threshold of about 700 mV), couples the input node A of the second buffer to the down converter core supply voltage VDDIN and has a control gate connected to the second supply voltage VDDQ that powers the input buffers of the digital device. This simple addition to the logic voltage level translating circuit of interface of each input pad of the device ensures that whenever the input node A could be floating (e.g. VDDQ=ground potential) and the second supply voltage VDDQ finally applied to the device after having applied the VDD supply voltage, the same node A is securely in a known state, notably A=VDDIN (i.e. at the logic state 1).

If the input pin in question is the reset pin of the device, that will ensure that before its logic value at the INPAD is read at power on, the logic value seen by the digital core is IN_N=GND (i.e. a logic state 0). A low state reset value will ensure a global resetting of the digital chip that will bring it in a known and safe condition. Upon the eventual rising of the VDDQ voltage the transistor TR1 will gradually be turned off and will finally reach a nonconductive state.

As may be observed, the presence of a down converter and of the added transistor TR1 of a relatively high threshold (for example of about 700 mV for a high voltage P-channel MOS) will further ensure that under most critical functional conditions, e.g. with a VDDQ=1.6V, the added transistor TR1 will not adversely influence the behavior of the basic interfacing circuitry.

By considering that the switching threshold is given by Vcomm=VDDIN−Vth_(TRI), for VDDQ<Vcomm the node A is forced to VDDIN; therefore, for VDDQ>Vcomm, the added p-channel transistor TR1 will not condition the signal on A that will depend on the value present on the respective I/O pad, INPAD_N.

An alternative and also preferred embodiment is illustrated in FIG. 3. The value of Vcomm may be reduced by introducing one or more transistors connected as diodes in series to the transistor TR1, as depicted in FIG. 3. Diode-connected transistors may be connected toward the VDDIN node and/or toward the ground node. The approach described herein substantially enhances the power on reliability in a dual power supply digital device with internal down converter by permitting even a non-simultaneous application of the two externally applied power supply voltages VDDQ and VDD without any spurious consequences.

Claims

1-3. (canceled)

4. A dual power supply device comprising: a down converter for converting an externally applied supply voltage to a regulated first supply voltage;at least one input/output pad;at least one first input buffer coupled to said at least one input/output pad and being powered by a second supply voltage;a voltage translator latch stage being powered by the regulated first supply voltage for replicating a stored inverted replica of a logic value on said at least one input/output pad onto a node;at least one second input buffer coupled to the node and being powered by the regulated first supply voltage; andat least one coupling transistor for coupling the node to the regulated first supply voltage, said at least one coupling transistor having a switching threshold and a control terminal connected to the second supply voltage.

5. The dual power supply device according to claim 4, further comprising at least one diode-connected transistor coupled in series with said at least one coupling transistor for adjusting the switching threshold thereof.

6. The dual power supply device according to claim 4, further comprising a dedicated pad for receiving the second supply voltage that is externally generated.

7. A digital device comprising: logic circuitry;a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering said logic circuitry;at least one input/output pad;at least one first input buffer coupled to said at least one input/output pad and being powered by a second supply voltage;a voltage translator latch stage receiving the regulated first supply voltage for replicating a stored inverted replica of a logic value on said at least one input/output pad onto a node;at least one second input buffer coupled to the node and being powered by the regulated first supply voltage; andat least one coupling transistor for coupling the node to the regulated first supply voltage, said at least one coupling transistor having a switching threshold and having a control terminal connected to said second supply voltage.

8. The digital device according to claim 7, further comprising at least one diode-connected transistor coupled in series with said at least one coupling transistor for adjusting the switching threshold thereof.

9. The digital device according to claim 7, further comprising a dedicated pad for receiving the second supply voltage that is externally generated.

10. A method for operating a dual power supply device comprising at least one input/output pad, at least one first input buffer coupled to the at least one input/output pad, a voltage translator latch stage coupled to a node, and at least one second input buffer coupled to the node, the method comprising: converting an externally applied supply voltage to a regulated first supply voltage for powering the voltage translator latch stage and the at least one second input buffer;providing a second supply voltage for powering the at least one first input buffer;operating the voltage translator latch stage for replicating a stored inverted replica of a logic value on theat least one input/output pad onto the node; and coupling the node to the regulated first supply voltage using at least one coupling transistor, the at least one coupling transistor having a switching threshold and a control terminal connected to the second supply voltage.

11. The method according to claim 10, wherein the dual power supply device further comprises at least one diode-connected transistor coupled in series with the at least one coupling transistor for adjusting the switching threshold thereof.

12. The method according to claim 10, wherein the dual power supply device further comprises a dedicated pad for receiving the second supply voltage that is externally generated.