Patent Application
20080229007
1. Field of the Invention
The present invention relates to computer memory and, more specifically, to a memory controller that allows a system configured for use with a first type of memory to use a second type of memory.
2. Description of the Prior Art
Random access memory (RAM) is used by almost every type of computational system to store data. RAM stores all sorts of information used by the processor of the system, including instructions and the data being manipulated by the system. There are many different types of RAM, each having their own data transfer formats and set of physical parameters.
One type of RAM is double-data-rate-two synchronous dynamic random access memory (DDR2 SDRAM), which is a random access memory technology used for high speed storage of the working data of a computer or other digital electronic devices. It has the ability to run its data bus at twice the clock rate, thus enabling faster bus speeds and higher peak throughputs than earlier technologies.
Another type of RAM is XDR DRAM (extreme Data Rate dynamic RAM), which competes with DDR2 SDRAM. XDR DRAM was initially designed for small, high-bandwidth consumer systems, high-performance memory applications, and high-end processing units. It eliminates some of the high pin count problems found in other types of RAM. XDR memory systems provide high memory bandwidth by sending eight data bits per clock cycle over an XIO (extreme IO) link, from a memory controller to the XDR DRAMs. An XIO link is capable of achieving signal rates of 3.2 Gbps and above, allowing a memory controller to use fewer I/O pins and therefore save on die size and cost. However, XDR memory systems are currently limited in the amount of memory capacity they can support, whereas DDR2 systems can be expanded to use more memory than current XDR systems. XDR memory also tends to be more expensive than industry standard memories such as DDR2.
In some applications, highly functional processor chips (such as the Cell chip) that are originally configured for use with XDR memory could take advantage of certain properties of DDR2 memory (e.g., the lower cost of DDR2 memory and its greater expandability), except that DDR2 memory is not compatible with such processors. This is for two reasons: first, the data stream format of XDR memory is different from that of DDR2 memory (e.g., the number and timing of refreshes is different) and, second, the physical parameters of XDR memory are different from the physical parameters of DDR2 memory (e.g., they have different signal levels and different pin counts).
Therefore, there is a need for a method and apparatus that allows a system configured to use memory of a first type (such as XDR memory) to use memory of a second type (such as DDR2 memory).
The disadvantages of the prior art are overcome by the present invention which, in one aspect, is a memory control apparatus that includes a data stream format converter and a physical layer converter. The data stream format converter is configured to convert an incoming data stream that has a data stream format corresponding to a first memory type into a format-converted data stream that has a data stream format corresponding to a second memory type. The second memory type is different from the first memory type. The physical layer converter is configured to convert the format-converted data stream into a physical-layer-converted data stream that has at least one physical parameter corresponding to the second memory type. The format-converted data stream has at least one physical parameter corresponding to the first memory type.
In another aspect, the invention is a memory controller for allowing a system to select between operating with XDR memory and operating with DDR2 memory. A data stream format converter is configured to receive an incoming XDR-format data stream from the system. The data stream format converter is also configured to insert periodically, into the XDR-format data stream, a DDR2 refresh sequence that has a periodicity corresponding to a pre-specified DDR2 refresh periodicity, thereby generating a DDR2-format data stream. A physical layer conversion chip is configured to convert each signal of the DDR2-format data stream into a corresponding signal having a signal level corresponding to pre-specified DDR2 signal levels. The physical layer conversion chip is also configured to match each signal of the DDR2-format data stream to a signal of a DDR2 memory channel.
In yet another aspect, the invention is a method of managing data in which a format of an incoming data stream from a data source that is configured to use a first type of memory is modified so as to generate a format-converted data stream that has a format corresponding to a second type of memory. The second type of memory is different from the first type of memory. At least one physical parameter of the format-converted data stream is adjusted so as to generate a physical-layer-converted data stream so that the physical-layer-converted data stream has at least one physical parameter that corresponds to the second type of memory.
These and other aspects of the invention will become apparent from the following description of the preferred embodiments taken in conjunction with the following drawings. As would be obvious to one skilled in the art, many variations and modifications of the invention may be effected without departing from the spirit and scope of the novel concepts of the disclosure.
A preferred embodiment of the invention is now described in detail. Referring to the drawings, like numbers indicate like parts throughout the views. As used in the description herein and throughout the claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise: the meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.”
As discussed above, a typical computational system is configured to use a single type of memory. However, as shown in
In one embodiment, as shown in
On the other hand, if the system is originally configured to use the first memory type and if the system is currently using memory of the second memory type, then the data stream format converter 210 generates a data stream that has a format that is compatible with the second memory type. For example the data stream format converter 210 inserts refresh events according to a refresh schedule corresponding to the second memory type. The resulting format-converted data stream is sent to a physical configuration converter 220 that converts physical layer characteristics of the format-converted data stream so as to have physical characteristics that are compatible with the second memory type. The physical layer converter can convert such physical parameters of the incoming data stream as: the signal levels (e.g., voltage) of each signal, the number of signals required (if, for example, the memory of the first type has a different pin count from the memory of a second type), and the clock frequency corresponding to the signals. The resulting physical-layer-converted data stream is then sent to memory space 232 of the second memory type.
One illustrative embodiment, as shown in
The memory space 306 includes a first memory channel 310 and a second memory channel 312. The first memory channel 310 and the second memory channel 312 each communicate with the memory controller 302 via a separate memory channel address bus 308. Each memory channel 310 and 312 includes a physical layer converter 314 (which coverts XDR signal parameters to corresponding DDR2 signal parameters) and two ranks (a first rank 316 and a second rank 318) of DDR2 memory. (More ranks, or fewer, of DDR2 memory may be added, depending upon the specific application.)
The physical layer converters 314 of the specific embodiment shown in
As shown in
The DDR2 data stream 420 employs a different refresh pattern. In a DDR2 system, all banks of all ranks of memory are refreshed in one refresh event 422. To facilitate a refresh event, a gap time delay 424 is added to the data stream prior to the refresh command 414 to allow any pending operations in the DDR2 memory space to complete. Then, after the refresh command 414, a refresh time delay period “tREF” 426 is inserted to allow all of the DDR2 memory ranks to complete the refresh. After the tREF time delay 426, ordinary operational cycles 412 are transmitted until the next refresh event 422 (which will typically happen after 720 operational cycles 412).
As shown in
The relationship between addresses on the EIB Bus and corresponding addresses on the memory channel are shown in
An additional bit must be used when the system is employing a dual-channel memory space, as shown in
In order to use a chip with an XIO interface in an application which requires large amounts of memory, a bridge chip is required which converts the XDR command and data protocols to the DDR2 command and data protocols. This solution maintains the advantage of using the XIO link (fewer pins on the expensive memory controller), but enables the advantages of DDR2 (low cost, high capacity).
The above described embodiments, while including the preferred embodiment and the best mode of the invention known to the inventor at the time of filing, are given as illustrative examples only. It will be readily appreciated that many deviations may be made from the specific embodiments disclosed in this specification without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be determined by the claims below rather than being limited to the specifically described embodiments above.
