Patent Application
20160232833
The present disclosure relates generally to an electronic display, and more particularly, to inversion imbalance compensation in an electronic display.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Generally, an electronic display may enable a user to perceive visual representations of information by successively writing image frames to a display panel of the electronic display. More specifically, an image frame may be displayed by applying positive polarity voltages and/or negative polarity voltages to the pixels in the display panel. For example, in a column inversion technique, positive polarity voltages may be applied to odd numbered columns and negative polarity voltages may be applied to even numbered columns to display a first image frame or first set of consecutive image frames. Subsequently, negative polarity voltages may be applied to the odd numbered columns and positive polarity voltage may be applied to the even numbered columns to display a second image frame or second set of consecutive image frames that occur after the first set of consecutive image frames.
As used herein, a “refresh rate” is intended to describe the frequency with which the image frames (e.g., first and second image frames) are written to the display panel. Accordingly, in some embodiment, adjusting the refresh rate of an electronic device may adjust the power consumption by the electronic display. For example, when the refresh rate is higher, the power consumption may also be higher. On the other hand, when the refresh rate is lower, the power consumption may also be lower.
In fact, in some embodiments, the refresh rate may be dynamic even between successively displayed image frames. For instance, continuing with the above example, the first image frame may be displayed with a refresh rate of 60 Hz and the second image frame may be displayed with a refresh rate of 30 Hz. As such, the negative polarity voltages may be applied to the odd numbered columns for twice as long as the positive polarity voltages. Similarly, the positive polarity voltage may be applied to the even numbered columns for twice as long as the negative polarity voltages. However, since the duration the opposite polarity voltages are applied to the display panel may be different when the refresh rate is variable, an inversion imbalance (e.g., polarization, also referred to as a bias voltage) may be accumulated in the display panel and reduce image quality.
A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects that may not be set forth below.
The present disclosure generally relates to improving quality of images displayed on an electronic display particularly when refresh rate of the electronic display is dynamic. More specifically, when the refresh rate is dynamic, the duration each successive image is displayed may vary. As such, when inversion techniques vary between applying positive polarity and negative polarity voltages to display an image frame, inversion imbalance may accumulate, thereby polarizing the pixels and reducing image quality.
Accordingly, the techniques described herein may reduce the polarization that occurs in pixels of an electronic display by accounting for the polarity and duration voltages are applied to display each image frame. In some embodiments, a timing controller in the electronic display may determine duration voltages are applied to display each image frame based on the number of lines included in corresponding image data received from an image source. Additionally, the timing controller may determine the polarity of voltages to display each frame based at least in part on inversion imbalance (e.g., polarization) accumulated in the pixels of the electronic display. For example, the timing controller may count up when a first set of voltage polarities (e.g., positive polarity applied to odd columns and negative polarity applied to even columns) is applied to the electronic display pixels and count down when a second set of voltage polarities (e.g., negative polarity applied to odd columns and positive polarity applied to even columns) is applied to the electronic display pixels. As such, the timing controller may reduce the accumulated inversion imbalance in the electronic display by applying voltage polarities that trend the counter value toward zero.
In some embodiments, the possibility of a perceivable luminance spike may be reduced by alternating the polarity of voltage applied to each pixel between positive and negative to successively display image frames. Thus, to reduce or at least maintain (e.g., not make worse) the inversion imbalance of the pixels, image frames displayed at a reduced refresh rate (e.g., less than 60 Hz) may be written to the pixels using a set of voltage polarities opposite the accumulated inversion imbalance of the display panel. Furthermore, in some embodiments, to reduce the perceivability of a reduced refresh rate, step-down intermediate refresh rates may be used. Thus, to reduce or at least maintain (e.g., not make worse) the inversion imbalance of the pixels, an even number of image frames may be displayed at each step-down intermediate refresh rate. In other words, the techniques described herein may reduce the possibility of visual artifacts caused by inversion imbalance while also reducing the possibility of luminance spikes and/or the perceivability of a reduced refresh rate in an electronic display.
Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:
One or more specific embodiments of the present disclosure will be described below. These described embodiments are only examples of the presently disclosed techniques. Additionally, in an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but may nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.
As mentioned above, an electronic display may display image frames by applying voltage to the pixels on a display panel. More specifically, the pixels may transmit light based at least in part on the magnitude of the voltage applied. However, when a direct current (DC) voltage is applied to the pixel for extended periods of time, inversion imbalance may accumulate in the pixels, thereby polarizing the pixels and reducing the displayed image quality. For example, when a positive voltage is applied to a pixel for an extended period of time, the pixel may begin to be polarized positive. As such, when a voltage is applied to the pixel, the positive polarization may cause the pixel to have a higher voltage than the applied voltage, which causes the pixel to inaccurately transmit light (e.g., a visual artifact).
Thus, it may be beneficial to utilize inversion balancing techniques to reduce the occurrence of such visual artifacts. More specifically, the possibility of polarizing a pixel may be reduced by alternating between applying positive polarity voltage and negative polarity voltages to the pixel. As used herein, a “set of voltage polarities” is intended to describe the voltage polarities applied to the pixels to display an image frame. In other words, inversion techniques generally alternate between applying a first set of voltage polarities and applying a second set of voltage polarities, such that voltage polarity applied to each pixel is positive when one set of voltage polarities is applied and negative when the other set of voltage polarities is applied.
For example, in a column inversion technique, the first set of voltage polarities may include applying positive polarity voltages to odd numbered columns and negative polarity voltages to even numbered columns, and the second set of voltage polarities may include applying negative polarity voltages to the odd numbered columns and positive polarity voltages to the even numbered columns. In other words, a first image frame may be displayed by applying the first set of voltage polarities to the pixels and a successively displayed second image frame may be displayed by applying the second set of image polarities. As such, at a constant refresh rate, the opposite polarity voltages applied to each pixel may cancel each other out and reduce the risk of inversion imbalance (e.g., polarization).
However, in some embodiments, an electronic display may have the capability to switch to a dynamic variable refresh rate. For example, the electronic display may switch from utilizing a normal refresh rate (e.g., 60 Hz per frame) to a reduced refresh rate (e.g., 45 Hz or 30 Hz per frame) and vice versa. As used herein, the “normal refresh rate” is intended to describe the refresh rate that enables the electronic display to display both static and dynamic content, and the “reduced refresh rate” is intended to describe any refresh rate lower than the normal refresh rate. For example, when a dynamic variable refresh rate is used, the refresh rate used to display the first image frame may be different from the refresh rate used to display the second image frame. In other words, the duration each set of voltage polarities is held in the pixels may vary.
In such embodiments, even alternating the polarity of the voltage applied to the pixels may still result in polarization of the pixels. For example, in an extreme case, a first image frame may be displayed at 30 Hz by applying the first set of voltage polarities, a second image frame may be displayed at 60 Hz by applying the second set of voltage polarities, a third image frame may be displayed at 30 Hz by applying the first set of voltage polarities, a fourth image frame may be displayed at 60 Hz by applying the second set of voltage polarities, and so on. In such a case, over an extended period, pixels in the odd columns may be polarized positive and the pixels in the even columns may be polarized negative.
Accordingly, as will be described in more detail below, the techniques described herein may reduce the inversion imbalance (e.g., polarization) that accumulates in pixels of an electronic display by accounting for the polarity and duration voltages are held at the pixel to display each image frame. For example, in some embodiments, an electronic display may include a display panel, which displays image frames with varying refresh rates, and a timing controller. More specifically, the timing controller may receive image data from an image source, determine polarization of the display panel, and instruct a driver in the electronic display to apply a voltage to the display panel to write an image frame on the display panel based at least in part on the polarization of the display panel. For example, to determine the polarization, the timing controller may use a counter that counts up when the first set of voltage polarities is applied and counts down when the second set of voltage polarities is applied. As such, the timing controller may reduce the inversion imbalance accumulated in the display panel by applying the set of voltage polarities that trends the counter value toward zero.
However, in some embodiments, using the same set of voltage polarities to display successive image frames may cause a perceivable luminance spike. As such, the techniques described herein may reduce the possibility of a perceivable luminance spike by alternating between the first set of voltage polarities and the second set of voltage polarities to display successive image frames. Thus, to reduce or at least maintain (e.g., not make worse) the inversion imbalance of the pixels, image frames displayed at a reduced refresh rate (e.g., less than 60 Hz) may be written to the pixels using the set of voltage polarities opposite the polarization of the display panel. For example, when pixels in the odd columns are polarized negative and pixels in the even columns are polarized positive, an image frame displayed at a reduced refresh rate may be displayed by applying a first set of voltage polarities (e.g., positive polarity applied to odd columns and a negative polarity applied to even columns). On the other hand, when pixels in the odd columns are polarized positive and pixels in the even columns are polarized negative, an image frame displayed at a reduced refresh rate may be displayed by applying the second set of voltage polarities (e.g., negative polarity applied to odd columns and a positive polarity applied to even columns).
Furthermore, abruptly reducing the refresh rate with which successive image frames are displayed may increase perceivability of the change in refresh rate. Accordingly, in some embodiments, step-down intermediate refresh rates (e.g., 45 Hz) may be used to gradually step down to a target refresh rate (e.g., 30 Hz). Thus, to reduce or at least maintain (e.g., not make worse) the inversion imbalance of the pixels, an even number of image frames may be displayed at each step-down intermediate refresh rate. For example, a first image frame may be displayed at 60 Hz by applying the first set of voltage polarities, a second image frame may be displayed at a step-down intermediate refresh rate of 45 Hz by applying the second set of voltage polarities, a third image frame may be displayed at the step-down intermediate refresh rate of 45 Hz by applying the first set of voltage priorities, and a fourth image frame may be displayed at a target reduced refresh rate of 30 Hz by applying the second set of voltage polarities.
Additionally, to further reduce the inversion imbalance, a dynamic refresh rate may be used such that image frames written with a first set of voltage polarities having the same polarity as the inversion imbalance may be displayed for a shorter duration (e.g., higher refresh rate), whereas image frames written with a second set of voltage polarities have the opposite polarity as the inversion imbalance may be displayed for a longer duration (e.g., lower refresh rate). For example, when pixels in the odd columns are polarized negative and pixels in the even columns are polarized positive, a first image frame displayed by applying a first set of voltage polarities (e.g., positive polarity applied to odd columns and a negative polarity applied to even columns) at a higher refresh rate (e.g., 65 Hz) and a second image frame displayed by applying a second set of voltage polarities (e.g., negative polarity applied to odd columns and a positive polarity applied to even columns) at a lower refresh rate (e.g., 55 Hz).
In other words, the techniques described herein may reduce the likelihood of visual artifacts caused by inversion imbalance while also reducing the possibility of luminance spikes and/or the perceivability of a reduced refresh rate in the electronic display. To help illustrate, a computing device 10 that utilizes an electronic display 12 to display image frames is described in
Accordingly, as depicted, the computing device 10 includes the display 12, input structures 14, input/output (I/O) ports 16, one or more processor(s) 18, memory 20, nonvolatile storage 22, a network interface 24, a power source 26, and image processing circuitry 27. The various components described in
As depicted, the processor 18 and/or image processing circuitry 27 are operably coupled with memory 20 and/or nonvolatile storage device 22. More specifically, the processor 18 and/or image processing circuitry 27 may execute instruction stored in memory 20 and/or non-volatile storage device 22 to perform operations in the computing device 10, such as generating and/or transmitting image data. As such, the processor 18 and/or image processing circuitry 27 may include one or more general purpose microprocessors, one or more application specific processors (ASICs), one or more field programmable logic arrays (FPGAs), or any combination thereof Additionally, memory 20 and/or non volatile storage device 22 may be a tangible, non-transitory, computer-readable medium that stores instructions executable by and data to be processed by the processor 18 and/or image processing circuitry 27. In other words, the memory 20 may include random access memory (RAM) and the non-volatile storage device 22 may include read only memory (ROM), rewritable flash memory, hard drives, optical discs, and the like. By way of example, a computer program product containing the instructions may include an operating system or an application program.
Additionally, as depicted, the processor 18 is operably coupled with the network interface 24 to communicatively couple the computing device 10 to a network. For example, the network interface 24 may connect the computing device 10 to a personal area network (PAN), such as a Bluetooth network, a local area network (LAN), such as an 802.11x Wi-Fi network, and/or a wide area network (WAN), such as a 4G or LTE cellular network. Furthermore, as depicted, the processor 18 is operably coupled to the power source 26, which provides power to the various components in the computing device 10. As such, the power source 26 may includes any suitable source of energy, such as a rechargeable lithium polymer (Li-poly) battery and/or an alternating current (AC) power converter.
As depicted, the processor 18 is also operably coupled with I/O ports 16, which may enable the computing device 10 to interface with various other electronic devices, and input structures 14, which may enable a user to interact with the computing device 10. Accordingly, the inputs structures 14 may include buttons, keyboards, mice, trackpads, and the like. Additionally, in some embodiments, the display 12 may include touch sensitive components.
In addition to enabling user inputs, the display 12 may display image frames, such as a graphical user interface (GUI) for an operating system, an application interface, a still image, or a video. As depicted, the display is operably coupled to the processor 18 and the image processing circuitry 27. Accordingly, the image frames displayed by the display 12 may be based on image data received from the processor 18 and/or the image processing circuitry 27.
As will be described in more detail below, image data received by the display 12 may be used to determine the refresh rate with which a corresponding image frame is displayed. For example, the processor 18 and/or the image processing circuitry 27 may communicate a desired refresh rate to use based on the number of vertical blank (Vblank) lines include in the image data. Generally, the number of lines (e.g., vertical blank and active lines) may directly correspond with duration an image frame is displayed because the time it takes for the display 12 to write one line is generally constant. For example, when a displayed image frame has a resolution of 2880×1800 and is displayed at 60 Hz, the image data may include 52 vertical blank lines and 1800 active lines. Thus, the duration the image frame is displayed may be described as 1852 lines.
As described above, the computing device 10 may be any suitable electronic device. To help illustrate, one example of a handheld device 10A is described in
As depicted, the handheld device 10A includes an enclosure 28, which may protect interior components from physical damage and to shield them from electromagnetic interference. The enclosure 28 may surround the display 12, which, in the depicted embodiment, displays a graphical user interface (GUI) 30 having an array of icons 32. By way of example, when an icon 32 is selected either by an input structure 14 or a touch sensing component of the display 12, an application program may launch.
Additionally, as depicted, input structure 14 may open through the enclosure 28. As described above, the input structures 14 may enable a user to interact with the handheld device 10A. For example, the input structures 14 may activate or deactivate the handheld device 10A, navigate a user interface to a home screen, navigate a user interface to a user-configurable application screen, activate a voice-recognition feature, provide volume control, and toggle between vibrate and ring modes. Furthermore, as depicted, the I/O ports 16 open through the enclosure 28. In some embodiments, the I/O ports 16 may include, for example, an audio jack to connect to external devices.
To further illustrate a suitable computing device 10, a tablet device 10B is described in
As described above, the display 12 may display image frames based on image data received from the processor 18 and/or the image processing circuitry 27. More specifically, the image data may be processed by any combination of the processor 18, the image processing circuitry 27, and the display 12 itself. To help illustrate, a portion 34 of the computing device 10 that processes and communicates image data is described in
As depicted, the portion 34 of the computing device 10 includes an image source 36, a timing controller (TCON) 38, and a display driver 40. More specifically, the image source 36 may generate image data and transmit the image data to the timing controller 38. Accordingly, in some embodiments, the source 36 may be the processor 18 and/or the image processing circuitry 27. Additionally, the timing controller 38 may analyze the received image data and instruct the driver 40 to write an image frame to the pixels by applying a voltage to the display panel of the electronic display 12. As such, in some embodiments, the timing controller 38 and the display driver 40 may be included in the electronic display 12.
To facilitate processing/analyzing the image data and/or performing other operations, the timing controller 38 may include a processor 42 and memory 44. In some embodiments, the timing controller processor 42 may be included in the processor 18 and/or the image processing circuitry 27. In other embodiments, the timing controller processor 42 may be a separate processing module. Additionally, in some embodiments, the timing controller memory 44 may be included in memory 20, storage device 22, or another tangible, non-transitory, computer readable medium. In other embodiments, the timing controller memory 44 may be a separate tangible, non-transitory, computer readable medium that stores instructions executable by the timing controller processor 42.
More specifically, the timing controller 38 may analyze the received image data to determine the magnitude of voltage to apply to each pixel to achieve the desired image frame and instruct the driver 40 accordingly. Additionally, the timing controller 38 may analyze the received image data to determine the desired refresh rate with which to display the image frame described by the image data and instruct the driver 40 accordingly.
In some embodiments, the timing controller 38 may determine the desired refresh rate based at least in part on the number of vertical blank (Vblank) lines and/or active lines included in the image data. For example, when the display 12 displays image frames with a resolution of 2880×1800, the timing controller 38 may instruct the driver 40 to display a first image frame at 60 Hz when the timing controller 38 determines that the corresponding image data includes 52 vertical blank lines and 1800 active lines. Additionally, the timing controller 38 may instruct the driver 40 to display a second image frame at 30 Hz when the timing controller 38 determine that the corresponding image data includes 1904 vertical blank lines and 1800 active lines.
Since each row of pixels in the display panel is successively written, the duration an image frame is displayed may include the number of active lines in corresponding image data. Additionally, when a vertical blank line in the corresponding image data is received, the displayed image frame may continue to be displayed. As such, the total duration an image frame is displayed may be described as the sum of the number of vertical blank lines and the number of active lines in the corresponding image data. To help illustrate, continuing with the above example, the duration the first image frame is displayed may be 1852 lines and the duration the second image frame is displayed may be 3704 lines. In other words, a line may be used herein to represent a unit of time.
As described above, the duration positive and negative voltages are applied to the display panel may polarize the pixels in the electronic display 12. As such, in some embodiments, the timing controller 38 may utilize a counter 46 to keep track of duration each sets of voltage polarities are held by incrementing/decrementing. For example, the counter 46 may increment the number of lines included in image data when the corresponding image frame is displayed with the first set of voltage polarities. On the other hand, the counter 46 may decrement the number of lines included in image data when the corresponding image frame is displayed with the second set of voltage polarities. Additionally or alternatively, the counter 46 may include a timer that keeps track of time each sets of voltage polarities are held.
As such, the timing controller 38 may reduce the inversion imbalance accumulated in pixels of the electronic display 12 by displaying subsequent image frames using a set of voltage polarities that trends the counter value toward zero. To help illustrate, one embodiment of a process 48 for successively displaying image frames on the electronic display 12 is described in
Accordingly, when image data is received from the image source 36, the timing controller 38 may determine the polarization of the electronic display 12 (process block 50). More specifically, the timing controller 38 may poll the counter 46 to determine the counter value. Based on the counter value, the timing controller 38 may determine whether the electronic display 12 is polarized toward the first set of voltage polarities or the second set of voltage polarities. For example, when the counter value is greater than zero, the timing controller 38 may determine that the electronic display 12 is polarized toward the first set of voltage polarities. On the other hand, when the counter value is less than zero, the timing controller 38 may determine that the electronic display 12 is polarized toward the second set of voltage polarities.
Additionally, the timing controller 38 may determine a refresh rate with which to display a next image frame (process block 52). More specifically, the timing controller 38 may determine the desired refresh rate based at least in part on the number lines (e.g., active and blank lines) included in the image data received from the image source 36. For example, when the display 12 has a resolution of 2880×1800, the timing controller 38 may determine that the desired refresh rate of a corresponding image frame is 60 Hz when the image data includes 52 vertical blank lines and 1800 active lines. Additionally, the timing controller 38 may determine that the desired refresh rate of a corresponding image frame is 30 Hz when the image data includes 1904 vertical blank lines and 1800 active lines.
However, at times, the refresh rate with which to display the next image frame may deviate from the desired refresh rate to reduce or at least maintain inversion imbalance in the pixels. More specifically, as will be described I more detail below, the refresh rate may be determined such that image frames displayed using a set of voltage polarities equal to polarization of the electronic display 12 are displayed for a lesser or equal duration. For example, when the desired refresh rate is a normal refresh rate, such as 60 Hz, the determined refresh rate (e.g., 65 Hz) may be greater than the desired refresh rate to facilitate reducing the inversion imbalance.
Additionally, when the desired refresh rate is a reduced refresh rate, such as 30 Hz, displaying the next image frame at the desired refresh rate may increase the inversion imbalance accumulated in the electronic display 12. For example, when the electronic display 12 is polarized toward the first set of voltage polarities, displaying the next image frame with the first set of voltage polarities at a reduced refresh rate may increase polarization toward the first set of voltage polarities. Instead, in some embodiments, the next image frame may be displayed at a normal refresh rate (e.g., 60 Hz) and the following image frame may be displayed at the desired refresh rate (e.g., 30 Hz).
Accordingly, the timing controller 38 may determine the set of voltage polarities with which to display the next image frame (process block 54). As described above, the likelihood of a luminance spike may be reduced by alternating between the first set of voltage polarities and the second set of voltage polarities such that the polarity applied to each pixel switches between positive and negative to display successive image frames. As such, the timing controller 38 may determine that the set of voltage polarities with which to display the next image frame is opposite the set of voltage polarities used to display the directly previous image frame. For example, when the previous image frame is displayed using the first set of voltage polarities, the timing controller 38 may determine that the next image frame should be displayed with the second set of voltage polarities.
The timing controller 38 may then instruct the display driver 40 to display one or more image frames by applying sets of voltage polarities to the pixels on the display panel (process block 56). More specifically, the timing controller 38 may instruct the display driver 40 to display the next image frame by applying the determined set of voltage polarities at the determined refresh rate to the display 12. Additionally, when the determined refresh rate is not the desired refresh rate, the timing controller 38 may instruct the display driver 40 to subsequently display an image frame at the desired refresh rate.
In other words, to reduce or at least maintain polarization of the electronic display 12, the next image frame may be displayed at a normal refresh rate (e.g., 60 Hz) even when the desired refresh rate is a reduced refresh rate (e.g., 30 Hz). For example, the next image frame may first be displayed at the normal refresh rate (e.g., 60 Hz) by applying the first set of voltage polarities and subsequently repeated at the desired reduced refresh rate by applying the second set of voltage polarities. In this manner, the polarization of the display panel toward the first set of voltage polarities may be decreased.
To help illustrate, a process 58 for determining refresh rate with which to display one or more image frames is described in
Accordingly, the timing controller 38 may determine whether the desired refresh rate is a reduced refresh rate (process block 60). In some embodiments, the normal refresh rate (e.g., 60 Hz) may be stored in memory 44. Accordingly, the timing controller 38 may retrieve and compare the normal refresh rate with the desired refresh rate. More specifically, when the desired refresh rate is less than the normal refresh rate, the timing controller 38 may determine that the desired refresh rate is a reduced refresh rate.
The timing controller 38 may then determine whether polarity with which to display the next image frame is equal to the polarization of the electronic display 12 (decision block 62). In some embodiments, an indication of the set of voltage polarities with which to display the next image frame and an indication of the polarization of the electronic display 12 (e.g., counter value) may be stored in memory 44. Accordingly, the timing controller 38 may retrieve and compare the set of voltage polarities with which to display the next image frame with the polarization of the electronic display 12.
When the timing controller 38 determines that their polarities are equal, the timing controller 38 may instruct the display driver 40 to display the next image frame at a normal refresh rate (process block 64) and display a following image frame at the desired reduced refresh rate (process block 66). On the other hand, when the timing controller 38 determines that they are not equal, the timing controller 38 may instruct the display driver 40 to display the next image frame at the desired reduced refresh rate (process block 66). In this manner, the polarization of the electronic display 12 may be decreased or at least maintained by displaying reduced refresh rate image frames with a set of voltage polarities opposite the polarization of the electronic display 12.
As described above, various inversion techniques may be used to write image frames to the electronic display 12. However, in each inversion technique, the voltage polarity applied to a pixel to successively display image frames generally alternates between positive and negative polarities. For example, in a column inversion technique a first set of voltage polarities may apply a positive polarity voltage to the odd columns and a negative polarity voltage to the even columns. As such, when the first set of voltage polarities is applied, a pixel in an odd column may adjust toward a positive polarization and a pixel in an even column may adjust toward a negative polarization. Moreover, since the first set of voltage polarities is applied to each of the pixels for approximately the same duration, the change in polarization for each of the pixels may generally be the same.
In fact, it may be possible to extrapolate the determined refresh rate of a single pixel to each of the pixels on the electronic display. In other words, the determined refresh rate may be the same whether based on a single pixel or the display panel as a whole. As such, process 58A as it relates to a single pixel is described in
As described in
Based on the polarization of the pixel and the voltage polarity that may be applied to display the next image frame, the timing controller 38 may then determine the refresh rate with which to display the next image frame. More specifically, when the pixel polarization and the voltage polarity with which to display the next image frame are both negative, the timing controller 38 may instruct the electronic display 12 to display the next image frame at 60 Hz (e.g., normal refresh rate) (process block 72) and display a following image frame at 30 Hz (e.g., desired reduced refresh rate) using a positive polarity voltage (process block 76). Similarly, when the pixel polarization and the voltage polarity with which to display the next image frame are both positive, the timing controller 38 may instruct the electronic display 12 to display the next image frame at 60 Hz (process block 74) and display the following image frame at 30 Hz using a negative polarity voltage (process block 78). On the other hand, when the pixel polarization and the next voltage polarity are different, the timing controller 38 may instruct the electronic display 12 to display the next image frame at 30 Hz (process blocks 76 and 78).
To help illustrate the techniques, a hypothetical display operation 80 is described in
In the depicted embodiment, the timing controller 38 may receive first image data at t0, which has a desired reduced refresh rate. In fact, the desired refresh rate may be the lowest possible refresh rate used by the electronic display. Based on the first image data, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the reduced refresh rate to display a first image frame between t0 and t1. More specifically, the first set of voltage polarities may apply a negative polarity voltage to the pixel. Thus, as depicted, the counter value decreases between t0 and t1 to indicate the duration the negative polarity voltage is applied to the pixel (e.g., duration the first set of voltage polarities is applied to the display panel).
At t1, the timing controller 38 may receive second image data, which has a desired normal refresh rate (e.g., 60 Hz). Based on the second image data, the timing controller 38 may instruct the display driver 40 to apply a second set of voltage polarities to the display panel at the normal refresh rate to display a second image frame between t1 and t2. More specifically, the second set of voltage polarities may apply a positive polarity voltage to the pixel. Thus, as depicted, the counter value increases between t1 and t2 to indicate the duration the positive polarity voltage is applied to the pixel (e.g., duration the second set of voltage polarities is applied to the display panel).
At t2, the timing controller 38 may receive third image data, which has a desired normal refresh rate (e.g., 60 Hz). Based on the third image data, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the normal refresh rate to display a third image frame between t2 and t3. Thus, as depicted, the counter value decreases between t2 and t3 to indicate the duration the negative polarity voltage is applied to the pixel.
At t3, the timing controller 38 may receive fourth image data, which has a desired reduced refresh rate (e.g., 30 Hz). Since the desired refresh rate is a reduced refresh rate, the timing controller 38 may compare the voltage polarity with which to display the next image frame and polarization of the pixel. More specifically, since the third image frame was displayed by applying a negative polarity, the timing controller 38 may determine that the next image frame may be displayed by applying a positive polarity. Additionally, the timing controller 38 may determine that the pixel is polarized negative because the counter value is negative.
Since the polarities are opposite, the timing controller 38 may instruct the display driver 40 to apply the second set of voltage polarities to the display panel at the reduced refresh rate to display a fourth image frame between t3 and t4 based on the fourth image data. Thus, as depicted, the counter value increases between t3 and t4 to indicate the duration the positive polarity voltage is applied to the pixel.
At t4, the timing controller 38 may receive fifth image data, which has a desired reduced refresh rate (e.g., 30 Hz). Since the desired refresh rate is a reduced refresh rate, the timing controller 38 may determine that the polarity with which to display a next image is negative and that the pixel is polarized negative because the counter value is negative. Since the polarities are the same, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the normal refresh rate to display a fifth image frame. In some embodiments, the fifth image frame may be displayed based on the fourth image data (e.g., repeat display of fourth image frame) or based on the fifth image data. Regardless, as depicted, the counter value decreases between t4 and t5 to indicate the duration the negative polarity voltage is applied to the pixel.
Based on the fifth image data, the timing controller 38 may then instruct the display driver 40 to apply the second set of voltage polarities to the display panel at the desired reduced refresh rate to display a sixth image frame (e.g., repeat display of fifth image frame) between t5 and t6. Thus, as depicted, the counter value increases between t5 and t6 to indicate the duration the positive polarity voltage is applied to the pixel.
In this manner, the inversion imbalance accumulated by the pixel and the display panel as a whole may be gradually reduced. In fact, since image frames displayed at a reduce refresh rate are displayed using a set of voltage polarities opposite the accumulated inversion imbalance, the amount of inversion imbalance may be bounded, for example, by the amount of polarization caused by displaying an image frame at the lowest possible refresh rate. For example, in the depicted embodiment, the inversion imbalance accumulated may be bounded by the value at t1. In other words, inversion imbalance may stay within a bounded range, which decreases the likelihood of the inversion imbalance causing perceivable visual artifacts.
As described above, displaying images at a reduced refresh rate may reduce energy consumption by the electronic display 12. Accordingly, in some embodiments, it may be desirable to maintain the electronic display 12 in a reduced refresh mode, in which successive image frames are displayed at a reduced refresh rate even when the display panel is polarized. To help illustrate the techniques, a hypothetical display operation 84 is described in
As depicted, the hypothetical display operation 84 may be generally the same as the hypothetical display operation 80 between t0 and t4. More specifically, between t0 and t1, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the reduced refresh rate to display the first image frame, between t1 and t2, the timing controller 38 may instruct the display driver 40 to apply the second set of voltage polarities to the display panel at the normal refresh rate to display the second image frame, between t2 and t3, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the normal refresh rate to display the third image frame, and between t3 and t4, timing controller 38 may instruct the display driver 40 to apply the second set of voltage polarities to the display panel at the reduced refresh rate to display the third image frame between t3 and t4. In other words, the timing controller 38 may instruct the electronic display 12 to enter a reduced refresh mode.
At t4, the timing controller 38 may receive fifth image data, which has a desired reduced refresh rate (e.g., 30 Hz). Since the electronic display 12 is in a reduced refresh mode, the timing controller 38 may determine whether to remain in the reduced refresh mode. More specifically, the timing controller 38 may determine whether to remain in the reduced refresh modes based on whether the desired refresh rate describes in the fifth image data is greater than or equal to the refresh rate used to display the fourth image frame. For example, in the depicted embodiment, since the desired refresh rate is greater than or equal, the timing controller 38 may determine that the electronic display 12 may remain in the reduced refresh mode. As such, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the reduced refresh rate to display a fifth image frame between t4 and t5′. Accordingly, as depicted, the counter value decreases between t4 and t5′ to indicate the duration the negative polarity voltage is applied to the pixel.
On the other hand, when the desired refresh rate is less than the refresh rate used to display the fourth image frame, the timing controller 38 may determine that it is desirable to briefly exit the reduced refresh mode to reduce the likelihood of the accumulated inversion imbalance exceeding the bounds (e.g., value at t1). More specifically, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the normal refresh rate to display a fifth image frame, and based on the fifth image data, to apply the second set of voltage polarities to the display panel at the desired reduced refresh rate to display a sixth image frame.
As described above, in some embodiments, intermediate step-down refresh rates may be used to reduce perceivability of changes to the refresh rate with which image frames are displayed. To help illustrate, a process 88 for displaying one or more image frame is described in
Similar to process 58, the timing controller 38 may determine whether the desired refresh rate is a reduced refresh rate (process block 90). More specifically, when the desired refresh rate is less than the normal refresh rate of the electronic display 12, the timing controller 38 may determine that the desired refresh rate is a reduced refresh rate. The timing controller 38 may then determine whether polarity with which to display the next image frame is equal to the polarization of the electronic display 12 (decision block 92). Additionally, when the timing controller 38 determines that they are equal, the timing controller 38 may instruct the display driver 40 to display the next image frame at a normal refresh rate (process block 94).
The timing controller 38 may then instruct the display driver 40 to display an even number of image frames at one or more intermediate refresh rates (process block 96). More specifically, the timing controller 38 may instruct the display driver 40 to display image frames at one or more intermediate refresh rates when the desired refresh rate is less than the refresh rate with which a directly previous image frame is displayed. Generally, the threshold amount may be set so that changes in refresh rate greater than the threshold amount may be perceivable by a user's eyes.
Thus, to reduce or at least maintain the accumulated inversion imbalance, an even number of image frames may be displayed at each intermediate refresh rate. For example, a first image frame may be displayed at an intermediate refresh rate (e.g., 45 Hz) by applying the first set of voltage polarities and a second image frame may be displayed at the intermediate refresh rate by applying the second set of voltage polarities. In this manner, the polarization caused by displaying the first image frame and the second image frame may cancel out and at least maintain (e.g., not make worse) the accumulated inversion imbalance.
The timing controller 38 may then instruct the display driver 40 to display an image frame at the desired refresh rate (process block 98). As such, the polarization of the electronic display 12 may be decreased or at least maintained while also reducing the peceivability of a reduced refresh rate by gradually reducing the refresh rate of the electronic display 12 using intermediate refresh rates.
As described above, various inversion techniques may be used to write image frames to the electronic display 12. More specifically, in each inversion technique, the voltage polarity applied to a pixel to successively display image frames generally alternates between positive and negative polarities. As such, it may be possible to extrapolate the determined refresh rate of a single pixel to each of the pixels on the electronic display.
To help illustrate the techniques, a hypothetical display operation 100 is described in
As depicted, the hypothetical display operation 100 may be generally the same as the hypothetical display operation 80 between t0 and t3. More specifically, between t0 and t1, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the reduced refresh rate to display the first image frame, between t1 and t2, the timing controller 38 may instruct the display driver 40 to apply the second set of voltage polarities to the display panel at the normal refresh rate to display the second image frame, and between t2 and t3, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the normal refresh rate to display the third image frame.
At t3, the timing controller 38 may receive fourth image data, which has a desired reduced refresh rate (e.g., 30 Hz). Since the desired refresh rate is a reduced refresh rate, the timing controller 38 may compare the voltage polarity with which to write a next image frame and polarization of the pixel. More specifically, since the third image frame was displayed by applying a negative polarity, the timing controller 38 may determine that the fourth image frame may be displayed by applying a positive polarity. Additionally, the timing controller 38 may determine that the pixel is polarized negative because the counter value is negative.
Since the polarities are opposite, the timing controller 38 may instruct the display driver 40 to determine whether the desired refresh rate in the fourth image data is lower than the refresh rate used to display the third image frame by more than a threshold amount. As in the depicted embodiment, when the desired refresh rate is lower by more than the threshold amount, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at an intermediate refresh rate (e.g., 45 Hz) to display a fourth image frame between t3 and t4 and to apply the second set of voltage polarities to the display at the intermediate refresh to display a fifth image frame between t4 and t5.
In some embodiments, the fourth image frame and the fifth image frame may be displayed based on the third image data (e.g., repeat display of third image frame), the fourth image data, or a combination thereof. For example, the fourth and fifth image frames may both be displayed based on the third image data or the fourth image data. Additionally or alternatively, the fourth image frame may be based on the third image data and the fifth image frame may be based on the fourth image data. Regardless, as depicted, the counter value increases between t3 and t4 to indicate the duration the positive polarity voltage is applied to the pixel and decreases between t4 and t5 to indicate the duration the negative polarity is applied to the pixel.
Once an even number of image frames is displayed at the intermediate refresh rate, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the desired (e.g., target) refresh rate based on the fourth image data to display a sixth image frame between t5 and t6. Thus, as depicted, the counter value increases between t5 and t6 to indicate the duration the positive polarity voltage is applied to the pixel. In this manner, the inversion imbalance accumulated by the pixel and the display panel as a whole may be gradually reduced while reducing the perceivability of reductions of refresh rate with which image frames are displayed.
As described above, in some embodiments, the determined refresh rate may deviate from a desired normal refresh rate to facilitate reducing inversion imbalance in the electronic display 12. To help illustrate, a process 104 for displaying one or more image frame is described in
Accordingly, the timing controller 38 may determine whether the desired refresh rate is a normal refresh rate (e.g., 60 Hz) (process block 106). In some embodiments, the normal refresh rate (e.g., 60 Hz) may be stored in memory 44. Accordingly, the timing controller 38 may retrieve and compare the normal refresh rate with the desired refresh rate.
More specifically, when the desired refresh rate is equal to the normal refresh rate, the timing controller 38 may then determine whether polarity with which to display the next image frame is equal to the polarization of the electronic display 12 (decision block 108). When the timing controller 38 determines that their polarities are equal, the timing controller 38 may instruct the display driver 40 to display the next image frame for a shorter duration (process block 110). More specifically, in some embodiments, the next image frame may be displayed at a higher refresh rate, such as 65 Hz, 90 Hz, 120 Hz, or greater. On the other hand, when the timing controller 38 determines that they are not equal, the timing controller 38 may instruct the display driver 40 to display the next image frame for a longer duration (process block 112).
More specifically, in some embodiments, the next image frame may be displayed at a lower refresh rate, such as 60 Hz, 55 Hz, 30 Hz, or lower (process block 112). In this manner, the polarization of the electronic display 12 may be decreased by displaying image frames written with a set of voltage polarities opposite the polarization of the electronic display 12 for a longer duration. The paring between short and long frame may be determined by the timing controller 38 to improve screening performance issue.
To help illustrate the techniques, a hypothetical display operation 114 is described in
In the depicted embodiment, the timing controller 38 may receive first image data at t0, which has a desired reduced refresh rate. Based on the first image data, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the reduced refresh rate to display a first image frame between t0 and t1. More specifically, the first set of voltage polarities may apply a negative polarity voltage to the pixel. Thus, as depicted, the counter value decreases between t0 and t1 to indicate the duration the negative polarity voltage is applied to the pixel (e.g., duration the first set of voltage polarities is applied to the display panel).
At t1, the timing controller 38 may receive second image data, which has a desired normal refresh rate (e.g., 60 Hz). Additionally, the timing controller 38 may determine that a second image frame may be displayed by applying a second set of voltage polarities (e.g., positive polarity to the pixel). Accordingly, since the second set of voltage polarities is opposite the polarization of the pixel, the timing controller 38 may determine that the second image frame may be displayed at a lower refresh rate (e.g., 55 Hz) between t1 and t2. Thus, as depicted, the counter value increases between t1 and t2 to indicate the duration the positive polarity voltage is applied to the pixel (e.g., duration the second set of voltage polarities is applied to the display panel).
At t2, the timing controller 38 may receive third image data, which has a desired normal refresh rate (e.g., 60 Hz). Additionally, the timing controller 38 may determine that a third image frame may be displayed by applying the first set of voltage polarities (e.g., negative polarity to the pixel). Accordingly, since the first set of voltage polarities is the same polarity as the polarization of the pixel, the timing controller 38 may determine that the third image frame may be displayed at a higher refresh rate (e.g., 65 Hz) between t2 and t3. Thus, as depicted, the counter value decreases between t2 and t3 to indicate the duration the negative polarity voltage is applied to the pixel (e.g., duration the first set of voltage polarities is applied to the display panel).
At t3, the timing controller 38 may receive fourth image data, which has a desired normal refresh rate (e.g., 60 Hz). Additionally, the timing controller 38 may determine that a fourth image frame may be displayed by applying a second set of voltage polarities (e.g., positive polarity to the pixel). Accordingly, since the second set of voltage polarities is opposite the polarization of the pixel, the timing controller 38 may determine that the fourth image frame may be displayed at a lower refresh rate (e.g., 55 Hz) between t3 and t4. Thus, as depicted, the counter value increases between t3 and t4 to indicate the duration the positive polarity voltage is applied to the pixel (e.g., duration the second set of voltage polarities is applied to the display panel).
At t4, the timing controller 38 may receive fifth image data, which has a desired normal refresh rate (e.g., 60 Hz). Additionally, the timing controller 38 may determine that a fifth image frame may be displayed by applying the first set of voltage polarities (e.g., negative polarity to the pixel). Accordingly, since the first set of voltage polarities is the same polarity as the polarization of the pixel, the timing controller 38 may determine that the third image frame may be displayed at a higher refresh rate (e.g., 65 Hz) between t4 and t5. Thus, as depicted, the counter value decreases between t4 and t5 to indicate the duration the negative polarity voltage is applied to the pixel (e.g., duration the first set of voltage polarities is applied to the display panel).
As depicted, the image frames may be displayed by alternating display of image frames using the second set of voltage polarities at a lower refresh rate (55 Hz) and image frames using the first set of voltage polarities at a higher refresh rate (e.g., 60 Hz) until polarization of the pixel is approximately zero at t6. Thereafter, the image frames may be displayed at the desired normal refresh rate. For example, in the depicted embodiment, at t6, the timing controller 38 may instruct the display driver 40 to display an image frame at the desired normal refresh rate (e.g., 60 Hz) by applying the first set of voltage polarities and, at t7, instruct the display driver 40 to display an image frame at the desired normal fresh rate by applying the second set of voltage polarities. In this manner, the inversion imbalance of the pixel, and the display panel as a whole, may be gradually reduced.
In other words, the inversion imbalance may be gradually reduced by increasing display duration of image frames written using a set of voltage polarities opposite polarization of the display panel and/or by decreasing display duration of image frames written using a set of voltage polarities the same polarity as polarization of the display panel. To further illustrate, a hypothetical display operation 118 is described in
Similar to hypothetical operation 114, between t0 and t1, the timing controller 38 may instruct the display driver 40 to apply the first set of voltage polarities to the display panel at the reduced refresh rate to display the first image frame. At t1, the timing controller 38 may receive second image data, which has a desired normal refresh rate (e.g., 60 Hz). Additionally, the timing controller 38 may determine that a second image frame may be displayed by applying a second set of voltage polarities (e.g., positive polarity to the pixel). Since the since the second set of voltage polarities is opposite the polarization of the pixel, the timing controller 38 may determine that the second image frame may be displayed at the desired normal refresh rate (e.g., 60 Hz) between t1 and t2′. Thus, as depicted, the counter value increases between t1 and t2′ to indicate the duration the positive polarity voltage is applied to the pixel (e.g., duration the second set of voltage polarities is applied to the display panel).
As depicted, the image frames may be displayed by alternating display of image frames using the second set of voltage polarities at the desired normal refresh rate (e.g., 60 Hz) and image frames using the first set of voltage polarities at a higher refresh rate (e.g., 120 Hz) until polarization of the pixel is approximately zero at t4′. Thereafter, the image frames may be displayed at the desired normal refresh rate. For example, in the depicted embodiment, at t4′, the timing controller 38 may instruct the display driver 40 to display an image frame at the desired normal refresh rate (e.g., 60 Hz) by applying the first set of voltage polarities and, at t5′, instruct the display driver 40 to display an image frame at the desired normal fresh rate by applying the second set of voltage polarities. In this manner, the inversion imbalance of the pixel, and the display panel as a whole, may be gradually reduced.
In other embodiments, the inversion imbalance may be gradually reduced by alternating display of image frames using the second set of voltage polarities at a lower refresh rate (e.g., 30 Hz or 45 Hz) and image frames using the first set of voltage polarities at the desired normal refresh rate (e.g., 60 Hz) until polarization of the pixel is approximately zero.
Accordingly, the technical effects of the present disclosure include improving image display accuracy by an electronic display particularly when the electronic display uses a dynamic variable refresh rate. More specifically, the inversion imbalance accumulated in pixels of the electronic display may be bounded to reduce the likelihood of polarizing the pixels to the point of causing perceivable visual artifacts. For example, in some embodiments, an image frame displayed at a reduced refresh rate may be written to the pixels using a set of voltage polarities opposite to the polarization of the pixels. Additionally, in some embodiments, an even number of image frames may be displayed at intermediate step-down refresh rates. Furthermore, in some embodiments, image frames may be displayed at a refresh rate different from a desired normal refresh rate to gradually reduce accumulated inversion imbalance. In this manner, the accumulated inversion imbalance may be bounded and gradually reduced.
The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.
